ArmPkg/ArmPkg.dec: Redefined PcdSystemMemory(Base|Size) as UINT64

The System Memory region might be out of the 32-bit memory space.

This change has been validated on the FVP AArch64 model using 4GB
of DRAM at 0x8_0000_0000:

-  # System Memory (2GB)
-  gArmTokenSpaceGuid.PcdSystemMemoryBase|0x80000000
-  gArmTokenSpaceGuid.PcdSystemMemorySize|0x80000000
+  # System Memory (4GB)
+  gArmTokenSpaceGuid.PcdSystemMemoryBase|0x800000000
+  gArmTokenSpaceGuid.PcdSystemMemorySize|0x100000000

EFI Shell and Linux kernel boot successfully.

Note: This change has not been validated on AArch32. I expect some
early assembly code to not work.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>




git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15093 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
Olivier Martin
2014-01-10 11:27:31 +00:00
committed by oliviermartin
parent 18b24f924f
commit c357fd6a1f
16 changed files with 49 additions and 49 deletions

View File

@@ -52,8 +52,8 @@
#define ARM_VE_SMB_PERIPH_SZ SIZE_64MB
// DRAM
#define ARM_VE_DRAM_BASE PcdGet32 (PcdSystemMemoryBase)
#define ARM_VE_DRAM_SZ PcdGet32 (PcdSystemMemorySize)
#define ARM_VE_DRAM_BASE PcdGet64 (PcdSystemMemoryBase)
#define ARM_VE_DRAM_SZ PcdGet64 (PcdSystemMemorySize)
// Inside the DRAM we allocate a section for the VRAM (Video RAM)
#define LCD_VRAM_CORE_TILE_BASE 0x64000000

View File

@@ -45,8 +45,8 @@
#define ARM_VE_SMB_PERIPH_SZ SIZE_64MB
// DRAM
#define ARM_VE_DRAM_BASE PcdGet32 (PcdSystemMemoryBase)
#define ARM_VE_DRAM_SZ PcdGet32 (PcdSystemMemorySize)
#define ARM_VE_DRAM_BASE PcdGet64 (PcdSystemMemoryBase)
#define ARM_VE_DRAM_SZ PcdGet64 (PcdSystemMemorySize)
// This can be any value since we only support motherboard PL111
#define LCD_VRAM_CORE_TILE_BASE 0x00000000

View File

@@ -136,18 +136,18 @@ ArmPlatformGetVirtualMemoryMap (
#ifndef ARM_BIGLITTLE_TC2
// Workaround for SRAM bug in RTSM
if (PcdGet32 (PcdSystemMemoryBase) != 0x80000000) {
if (PcdGet64 (PcdSystemMemoryBase) != 0x80000000) {
VirtualMemoryTable[++Index].PhysicalBase = 0x80000000;
VirtualMemoryTable[Index].VirtualBase = 0x80000000;
VirtualMemoryTable[Index].Length = PcdGet32 (PcdSystemMemoryBase) - 0x80000000;
VirtualMemoryTable[Index].Length = PcdGet64 (PcdSystemMemoryBase) - 0x80000000;
VirtualMemoryTable[Index].Attributes = CacheAttributes;
}
#endif
// DDR
VirtualMemoryTable[++Index].PhysicalBase = PcdGet32 (PcdSystemMemoryBase);
VirtualMemoryTable[Index].VirtualBase = PcdGet32 (PcdSystemMemoryBase);
VirtualMemoryTable[Index].Length = PcdGet32 (PcdSystemMemorySize);
VirtualMemoryTable[++Index].PhysicalBase = PcdGet64 (PcdSystemMemoryBase);
VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdSystemMemoryBase);
VirtualMemoryTable[Index].Length = PcdGet64 (PcdSystemMemorySize);
VirtualMemoryTable[Index].Attributes = CacheAttributes;
// Detect if it is a 1GB or 2GB Test Chip
@@ -159,13 +159,13 @@ ArmPlatformGetVirtualMemoryMap (
EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
EFI_RESOURCE_ATTRIBUTE_TESTED,
PcdGet32 (PcdSystemMemoryBase) + PcdGet32 (PcdSystemMemorySize),
PcdGet64 (PcdSystemMemoryBase) + PcdGet64 (PcdSystemMemorySize),
SIZE_1GB
);
// Map the additional 1GB into the MMU
VirtualMemoryTable[++Index].PhysicalBase = PcdGet32 (PcdSystemMemoryBase) + PcdGet32 (PcdSystemMemorySize);
VirtualMemoryTable[Index].VirtualBase = PcdGet32 (PcdSystemMemoryBase) + PcdGet32 (PcdSystemMemorySize);
VirtualMemoryTable[++Index].PhysicalBase = PcdGet64 (PcdSystemMemoryBase) + PcdGet64 (PcdSystemMemorySize);
VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdSystemMemoryBase) + PcdGet64 (PcdSystemMemorySize);
VirtualMemoryTable[Index].Length = SIZE_1GB;
VirtualMemoryTable[Index].Attributes = CacheAttributes;
}