Add DxeBootScriptLibNull in IntelFrameworkPkg.
Add IsaBusDxe in IntelFrameworkModulePkg. Add Pcat.h in "IntelFrameworkModulePkg/IndustryStandard" git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@2948 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
yshang1
105
IntelFrameworkModulePkg/Include/IndustryStandard/Pcat.h
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105
IntelFrameworkModulePkg/Include/IndustryStandard/Pcat.h
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/** @file
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Include file for PC-AT compatability.
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Copyright (c) 2006, Intel Corporation. All rights reserved.
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This software and associated documentation (if any) is furnished
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under a license and may only be used or copied in accordance
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with the terms of the license. Except as permitted by such
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license, no part of this software or documentation may be
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reproduced, stored in a retrieval system, or transmitted in any
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form or by any means without the express written consent of
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Intel Corporation.
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**/
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#ifndef _PC_AT_H_
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#define _PC_AT_H_
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//
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// 8254 Timer
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//
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#define TIMER0_COUNT_PORT 0x40
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#define TIMER1_COUNT_PORT 0x41
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#define TIMER2_COUNT_PORT 0x42
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#define TIMER_CONTROL_PORT 0x43
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//
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// 8259 PIC interrupt controller
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//
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#define PIC_CONTROL_REGISTER_MASTER 0x20
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#define PIC_MASK_REGISTER_MASTER 0x21
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#define PIC_CONTROL_REGISTER_SLAVE 0xA0
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#define PIC_MASK_REGISTER_SLAVE 0xA1
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#define PIC_EDGE_LEVEL_TRIGGERED_REGISTER_MASTER 0x4D0
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#define PIC_EDGE_LEVEL_TRIGGERED_REGISTER_SLAVE 0x4D1
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#define PIC_EOI 0x20
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//
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// 8237 DMA registers
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//
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#define R_8237_DMA_BASE_CA_CH0 0x00
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#define R_8237_DMA_BASE_CA_CH1 0x02
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#define R_8237_DMA_BASE_CA_CH2 0x04
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#define R_8237_DMA_BASE_CA_CH3 0xd6
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#define R_8237_DMA_BASE_CA_CH5 0xc4
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#define R_8237_DMA_BASE_CA_CH6 0xc8
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#define R_8237_DMA_BASE_CA_CH7 0xcc
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#define R_8237_DMA_BASE_CC_CH0 0x01
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#define R_8237_DMA_BASE_CC_CH1 0x03
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#define R_8237_DMA_BASE_CC_CH2 0x05
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#define R_8237_DMA_BASE_CC_CH3 0xd7
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#define R_8237_DMA_BASE_CC_CH5 0xc6
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#define R_8237_DMA_BASE_CC_CH6 0xca
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#define R_8237_DMA_BASE_CC_CH7 0xce
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#define R_8237_DMA_MEM_LP_CH0 0x87
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#define R_8237_DMA_MEM_LP_CH1 0x83
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#define R_8237_DMA_MEM_LP_CH2 0x81
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#define R_8237_DMA_MEM_LP_CH3 0x82
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#define R_8237_DMA_MEM_LP_CH5 0x8B
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#define R_8237_DMA_MEM_LP_CH6 0x89
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#define R_8237_DMA_MEM_LP_CH7 0x8A
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#define R_8237_DMA_COMMAND_CH0_3 0x08
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#define R_8237_DMA_COMMAND_CH4_7 0xd0
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#define B_8237_DMA_COMMAND_GAP 0x10
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#define B_8237_DMA_COMMAND_CGE 0x04
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#define R_8237_DMA_STA_CH0_3 0xd8
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#define R_8237_DMA_STA_CH4_7 0xd0
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#define R_8237_DMA_WRSMSK_CH0_3 0x0a
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#define R_8237_DMA_WRSMSK_CH4_7 0xd4
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#define B_8237_DMA_WRSMSK_CMS 0x04
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#define R_8237_DMA_CHMODE_CH0_3 0x0b
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#define R_8237_DMA_CHMODE_CH4_7 0xd6
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#define V_8237_DMA_CHMODE_DEMAND 0x00
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#define V_8237_DMA_CHMODE_SINGLE 0x40
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#define V_8237_DMA_CHMODE_CASCADE 0xc0
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#define B_8237_DMA_CHMODE_DECREMENT 0x20
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#define B_8237_DMA_CHMODE_INCREMENT 0x00
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#define B_8237_DMA_CHMODE_AE 0x10
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#define V_8237_DMA_CHMODE_VERIFY 0
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#define V_8237_DMA_CHMODE_IO2MEM 0x04
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#define V_8237_DMA_CHMODE_MEM2IO 0x08
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#define R_8237_DMA_CBPR_CH0_3 0x0c
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#define R_8237_DMA_CBPR_CH4_7 0xd8
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#define R_8237_DMA_MCR_CH0_3 0x0d
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#define R_8237_DMA_MCR_CH4_7 0xda
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#define R_8237_DMA_CLMSK_CH0_3 0x0e
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#define R_8237_DMA_CLMSK_CH4_7 0xdc
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#define R_8237_DMA_WRMSK_CH0_3 0x0f
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#define R_8237_DMA_WRMSK_CH4_7 0xde
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#endif
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177
IntelFrameworkModulePkg/Include/Protocol/IsaIo.h
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177
IntelFrameworkModulePkg/Include/Protocol/IsaIo.h
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/*++
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Copyright (c) 2006 - 2007, Intel Corporation
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All rights reserved. This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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Module Name:
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IsaIo.h
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Abstract:
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EFI ISA I/O Protocol
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Revision History
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--*/
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#ifndef _EFI_ISA_IO_H
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#define _EFI_ISA_IO_H
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#include <Protocol/IsaAcpi.h>
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//
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// Global ID for the ISA I/O Protocol
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//
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#define EFI_ISA_IO_PROTOCOL_GUID \
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{ 0x7ee2bd44, 0x3da0, 0x11d4, { 0x9a, 0x38, 0x0, 0x90, 0x27, 0x3f, 0xc1, 0x4d } }
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typedef struct _EFI_ISA_IO_PROTOCOL EFI_ISA_IO_PROTOCOL;
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//
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// Prototypes for the ISA I/O Protocol
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//
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typedef enum {
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EfiIsaIoWidthUint8,
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EfiIsaIoWidthUint16,
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EfiIsaIoWidthUint32,
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EfiIsaIoWidthReserved,
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EfiIsaIoWidthFifoUint8,
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EfiIsaIoWidthFifoUint16,
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EfiIsaIoWidthFifoUint32,
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EfiIsaIoWidthFifoReserved,
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EfiIsaIoWidthFillUint8,
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EfiIsaIoWidthFillUint16,
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EfiIsaIoWidthFillUint32,
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EfiIsaIoWidthFillReserved,
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EfiIsaIoWidthMaximum
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} EFI_ISA_IO_PROTOCOL_WIDTH;
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//
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// Attributes for common buffer allocations
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//
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#define EFI_ISA_IO_ATTRIBUTE_MEMORY_WRITE_COMBINE 0x080 // Map a memory range so write are combined
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#define EFI_ISA_IO_ATTRIBUTE_MEMORY_CACHED 0x800 // Map a memory range so all r/w accesses are cached
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#define EFI_ISA_IO_ATTRIBUTE_MEMORY_DISABLE 0x1000 // Disable a memory range
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//
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// Channel attribute for DMA operations
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//
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#define EFI_ISA_IO_SLAVE_DMA_ATTRIBUTE_SPEED_COMPATIBLE 0x001
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#define EFI_ISA_IO_SLAVE_DMA_ATTRIBUTE_SPEED_A 0x002
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#define EFI_ISA_IO_SLAVE_DMA_ATTRIBUTE_SPEED_B 0x004
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#define EFI_ISA_IO_SLAVE_DMA_ATTRIBUTE_SPEED_C 0x008
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#define EFI_ISA_IO_SLAVE_DMA_ATTRIBUTE_WIDTH_8 0x010
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#define EFI_ISA_IO_SLAVE_DMA_ATTRIBUTE_WIDTH_16 0x020
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#define EFI_ISA_IO_SLAVE_DMA_ATTRIBUTE_SINGLE_MODE 0x040
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#define EFI_ISA_IO_SLAVE_DMA_ATTRIBUTE_DEMAND_MODE 0x080
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#define EFI_ISA_IO_SLAVE_DMA_ATTRIBUTE_AUTO_INITIALIZE 0x100
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typedef enum {
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EfiIsaIoOperationBusMasterRead,
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EfiIsaIoOperationBusMasterWrite,
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EfiIsaIoOperationBusMasterCommonBuffer,
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EfiIsaIoOperationSlaveRead,
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EfiIsaIoOperationSlaveWrite,
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EfiIsaIoOperationMaximum
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} EFI_ISA_IO_PROTOCOL_OPERATION;
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typedef
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EFI_STATUS
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(EFIAPI *EFI_ISA_IO_PROTOCOL_IO_MEM) (
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IN EFI_ISA_IO_PROTOCOL *This,
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IN EFI_ISA_IO_PROTOCOL_WIDTH Width,
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IN UINT32 Offset,
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IN UINTN Count,
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IN OUT VOID *Buffer
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);
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typedef struct {
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EFI_ISA_IO_PROTOCOL_IO_MEM Read;
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EFI_ISA_IO_PROTOCOL_IO_MEM Write;
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} EFI_ISA_IO_PROTOCOL_ACCESS;
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typedef
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EFI_STATUS
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(EFIAPI *EFI_ISA_IO_PROTOCOL_COPY_MEM) (
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IN EFI_ISA_IO_PROTOCOL *This,
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IN EFI_ISA_IO_PROTOCOL_WIDTH Width,
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IN UINT32 DestOffset,
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IN UINT32 SrcOffset,
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IN UINTN Count
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);
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typedef
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EFI_STATUS
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(EFIAPI *EFI_ISA_IO_PROTOCOL_MAP) (
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IN EFI_ISA_IO_PROTOCOL *This,
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IN EFI_ISA_IO_PROTOCOL_OPERATION Operation,
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IN UINT8 ChannelNumber OPTIONAL,
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IN UINT32 ChannelAttributes,
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IN VOID *HostAddress,
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IN OUT UINTN *NumberOfBytes,
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OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,
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OUT VOID **Mapping
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);
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typedef
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EFI_STATUS
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(EFIAPI *EFI_ISA_IO_PROTOCOL_UNMAP) (
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IN EFI_ISA_IO_PROTOCOL *This,
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IN VOID *Mapping
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);
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typedef
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EFI_STATUS
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(EFIAPI *EFI_ISA_IO_PROTOCOL_ALLOCATE_BUFFER) (
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IN EFI_ISA_IO_PROTOCOL *This,
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IN EFI_ALLOCATE_TYPE Type,
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IN EFI_MEMORY_TYPE MemoryType,
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IN UINTN Pages,
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OUT VOID **HostAddress,
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IN UINT64 Attributes
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);
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typedef
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EFI_STATUS
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(EFIAPI *EFI_ISA_IO_PROTOCOL_FREE_BUFFER) (
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IN EFI_ISA_IO_PROTOCOL *This,
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IN UINTN Pages,
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IN VOID *HostAddress
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);
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typedef
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EFI_STATUS
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(EFIAPI *EFI_ISA_IO_PROTOCOL_FLUSH) (
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IN EFI_ISA_IO_PROTOCOL *This
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);
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//
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// Interface structure for the ISA I/O Protocol
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//
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struct _EFI_ISA_IO_PROTOCOL {
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EFI_ISA_IO_PROTOCOL_ACCESS Mem;
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EFI_ISA_IO_PROTOCOL_ACCESS Io;
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EFI_ISA_IO_PROTOCOL_COPY_MEM CopyMem;
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EFI_ISA_IO_PROTOCOL_MAP Map;
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EFI_ISA_IO_PROTOCOL_UNMAP Unmap;
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EFI_ISA_IO_PROTOCOL_ALLOCATE_BUFFER AllocateBuffer;
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EFI_ISA_IO_PROTOCOL_FREE_BUFFER FreeBuffer;
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EFI_ISA_IO_PROTOCOL_FLUSH Flush;
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EFI_ISA_ACPI_RESOURCE_LIST *ResourceList;
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UINT32 RomSize;
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VOID *RomImage;
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};
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extern EFI_GUID gEfiIsaIoProtocolGuid;
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#endif
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