SecurityPkg: Apply uncrustify changes
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3737 Apply uncrustify changes to .c/.h files in the SecurityPkg package Cc: Andrew Fish <afish@apple.com> Cc: Leif Lindholm <leif@nuviainc.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com> Reviewed-by: Jian J Wang <jian.j.wang@intel.com>
This commit is contained in:
committed by
mergify[bot]
parent
39de741e2d
commit
c411b485b6
@@ -30,10 +30,10 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
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EFI_STATUS
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EFIAPI
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DTpm2SubmitCommand (
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IN UINT32 InputParameterBlockSize,
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IN UINT8 *InputParameterBlock,
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IN OUT UINT32 *OutputParameterBlockSize,
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IN UINT8 *OutputParameterBlock
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IN UINT32 InputParameterBlockSize,
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IN UINT8 *InputParameterBlock,
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IN OUT UINT32 *OutputParameterBlockSize,
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IN UINT8 *OutputParameterBlock
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);
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/**
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@@ -64,10 +64,10 @@ DTpm2RequestUseTpm (
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EFI_STATUS
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EFIAPI
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Tpm2SubmitCommand (
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IN UINT32 InputParameterBlockSize,
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IN UINT8 *InputParameterBlock,
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IN OUT UINT32 *OutputParameterBlockSize,
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IN UINT8 *OutputParameterBlock
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IN UINT32 InputParameterBlockSize,
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IN UINT8 *InputParameterBlock,
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IN OUT UINT32 *OutputParameterBlockSize,
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IN UINT8 *OutputParameterBlock
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)
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{
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return DTpm2SubmitCommand (
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@@ -106,7 +106,7 @@ Tpm2RequestUseTpm (
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EFI_STATUS
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EFIAPI
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Tpm2RegisterTpm2DeviceLib (
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IN TPM2_DEVICE_INTERFACE *Tpm2Device
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IN TPM2_DEVICE_INTERFACE *Tpm2Device
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)
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{
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return EFI_UNSUPPORTED;
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@@ -19,7 +19,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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TPM2_PTP_INTERFACE_TYPE
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Tpm2GetPtpInterface (
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IN VOID *Register
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IN VOID *Register
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);
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/**
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@@ -31,7 +31,7 @@ Tpm2GetPtpInterface (
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**/
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UINT8
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Tpm2GetIdleByPass (
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IN VOID *Register
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IN VOID *Register
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);
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/**
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@@ -22,7 +22,7 @@ GetCachedIdleByPass (
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VOID
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)
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{
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return PcdGet8(PcdCRBIdleByPass);
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return PcdGet8 (PcdCRBIdleByPass);
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}
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/**
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@@ -35,7 +35,7 @@ GetCachedPtpInterface (
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VOID
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)
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{
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return PcdGet8(PcdActiveTpmInterfaceType);
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return PcdGet8 (PcdActiveTpmInterfaceType);
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}
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/**
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@@ -54,14 +54,14 @@ InternalTpm2DeviceLibDTpmCommonConstructor (
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//
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// Cache current active TpmInterfaceType only when needed
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//
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if (PcdGet8(PcdActiveTpmInterfaceType) == 0xFF) {
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PtpInterface = Tpm2GetPtpInterface ((VOID *) (UINTN) PcdGet64 (PcdTpmBaseAddress));
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PcdSet8S(PcdActiveTpmInterfaceType, PtpInterface);
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if (PcdGet8 (PcdActiveTpmInterfaceType) == 0xFF) {
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PtpInterface = Tpm2GetPtpInterface ((VOID *)(UINTN)PcdGet64 (PcdTpmBaseAddress));
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PcdSet8S (PcdActiveTpmInterfaceType, PtpInterface);
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}
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if (PcdGet8(PcdActiveTpmInterfaceType) == Tpm2PtpInterfaceCrb && PcdGet8(PcdCRBIdleByPass) == 0xFF) {
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IdleByPass = Tpm2GetIdleByPass((VOID *) (UINTN) PcdGet64 (PcdTpmBaseAddress));
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PcdSet8S(PcdCRBIdleByPass, IdleByPass);
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if ((PcdGet8 (PcdActiveTpmInterfaceType) == Tpm2PtpInterfaceCrb) && (PcdGet8 (PcdCRBIdleByPass) == 0xFF)) {
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IdleByPass = Tpm2GetIdleByPass ((VOID *)(UINTN)PcdGet64 (PcdTpmBaseAddress));
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PcdSet8S (PcdCRBIdleByPass, IdleByPass);
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}
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return EFI_SUCCESS;
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@@ -51,15 +51,15 @@ InternalTpm2DeviceLibDTpmCommonConstructor (
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)
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{
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mActiveTpmInterfaceType = 0xFF;
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mCRBIdleByPass = 0xFF;
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mCRBIdleByPass = 0xFF;
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//
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// Always cache current active TpmInterfaceType for StandaloneMm implementation
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//
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mActiveTpmInterfaceType = Tpm2GetPtpInterface ((VOID *) (UINTN) PcdGet64 (PcdTpmBaseAddress));
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mActiveTpmInterfaceType = Tpm2GetPtpInterface ((VOID *)(UINTN)PcdGet64 (PcdTpmBaseAddress));
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if (mActiveTpmInterfaceType == Tpm2PtpInterfaceCrb) {
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mCRBIdleByPass = Tpm2GetIdleByPass((VOID *) (UINTN) PcdGet64 (PcdTpmBaseAddress));
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mCRBIdleByPass = Tpm2GetIdleByPass ((VOID *)(UINTN)PcdGet64 (PcdTpmBaseAddress));
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}
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return EFI_SUCCESS;
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@@ -25,7 +25,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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VOID
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DumpPtpInfo (
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IN VOID *Register
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IN VOID *Register
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);
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/**
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@@ -43,10 +43,10 @@ DumpPtpInfo (
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EFI_STATUS
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EFIAPI
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DTpm2SubmitCommand (
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IN UINT32 InputParameterBlockSize,
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IN UINT8 *InputParameterBlock,
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IN OUT UINT32 *OutputParameterBlockSize,
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IN UINT8 *OutputParameterBlock
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IN UINT32 InputParameterBlockSize,
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IN UINT8 *InputParameterBlock,
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IN OUT UINT32 *OutputParameterBlockSize,
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IN UINT8 *OutputParameterBlock
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);
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/**
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@@ -79,7 +79,7 @@ Tpm2InstanceLibDTpmConstructor (
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VOID
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)
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{
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EFI_STATUS Status;
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EFI_STATUS Status;
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Status = Tpm2RegisterTpm2DeviceLib (&mDTpm2InternalTpm2Device);
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if ((Status == EFI_SUCCESS) || (Status == EFI_UNSUPPORTED)) {
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@@ -88,9 +88,11 @@ Tpm2InstanceLibDTpmConstructor (
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//
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if (Status == EFI_SUCCESS) {
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Status = InternalTpm2DeviceLibDTpmCommonConstructor ();
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DumpPtpInfo ((VOID *) (UINTN) PcdGet64 (PcdTpmBaseAddress));
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DumpPtpInfo ((VOID *)(UINTN)PcdGet64 (PcdTpmBaseAddress));
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}
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return EFI_SUCCESS;
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}
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return Status;
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}
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@@ -26,12 +26,12 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
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// Execution of the command may take from several seconds to minutes for certain
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// commands, such as key generation.
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//
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#define PTP_TIMEOUT_MAX (90000 * 1000) // 90s
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#define PTP_TIMEOUT_MAX (90000 * 1000) // 90s
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//
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// Max TPM command/response length
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//
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#define TPMCMDBUFLENGTH 0x500
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#define TPMCMDBUFLENGTH 0x500
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/**
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Check whether TPM PTP register exist.
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@@ -43,10 +43,10 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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BOOLEAN
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Tpm2IsPtpPresence (
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IN VOID *Reg
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IN VOID *Reg
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)
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{
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UINT8 RegRead;
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UINT8 RegRead;
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RegRead = MmioRead8 ((UINTN)Reg);
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if (RegRead == 0xFF) {
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@@ -55,6 +55,7 @@ Tpm2IsPtpPresence (
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//
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return FALSE;
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}
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return TRUE;
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}
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@@ -71,22 +72,24 @@ Tpm2IsPtpPresence (
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**/
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EFI_STATUS
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PtpCrbWaitRegisterBits (
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IN UINT32 *Register,
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IN UINT32 BitSet,
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IN UINT32 BitClear,
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IN UINT32 TimeOut
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IN UINT32 *Register,
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IN UINT32 BitSet,
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IN UINT32 BitClear,
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IN UINT32 TimeOut
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)
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{
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UINT32 RegRead;
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UINT32 WaitTime;
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UINT32 RegRead;
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UINT32 WaitTime;
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for (WaitTime = 0; WaitTime < TimeOut; WaitTime += 30){
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for (WaitTime = 0; WaitTime < TimeOut; WaitTime += 30) {
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RegRead = MmioRead32 ((UINTN)Register);
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if ((RegRead & BitSet) == BitSet && (RegRead & BitClear) == 0) {
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if (((RegRead & BitSet) == BitSet) && ((RegRead & BitClear) == 0)) {
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return EFI_SUCCESS;
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}
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MicroSecondDelay (30);
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}
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return EFI_TIMEOUT;
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}
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@@ -102,16 +105,16 @@ PtpCrbWaitRegisterBits (
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**/
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EFI_STATUS
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PtpCrbRequestUseTpm (
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IN PTP_CRB_REGISTERS_PTR CrbReg
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IN PTP_CRB_REGISTERS_PTR CrbReg
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)
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{
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EFI_STATUS Status;
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EFI_STATUS Status;
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if (!Tpm2IsPtpPresence (CrbReg)) {
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return EFI_NOT_FOUND;
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}
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MmioWrite32((UINTN)&CrbReg->LocalityControl, PTP_CRB_LOCALITY_CONTROL_REQUEST_ACCESS);
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MmioWrite32 ((UINTN)&CrbReg->LocalityControl, PTP_CRB_LOCALITY_CONTROL_REQUEST_ACCESS);
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Status = PtpCrbWaitRegisterBits (
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&CrbReg->LocalityStatus,
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PTP_CRB_LOCALITY_STATUS_GRANTED,
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@@ -138,52 +141,55 @@ PtpCrbRequestUseTpm (
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**/
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EFI_STATUS
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PtpCrbTpmCommand (
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IN PTP_CRB_REGISTERS_PTR CrbReg,
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IN UINT8 *BufferIn,
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IN UINT32 SizeIn,
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IN OUT UINT8 *BufferOut,
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IN OUT UINT32 *SizeOut
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IN PTP_CRB_REGISTERS_PTR CrbReg,
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IN UINT8 *BufferIn,
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IN UINT32 SizeIn,
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IN OUT UINT8 *BufferOut,
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IN OUT UINT32 *SizeOut
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)
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{
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EFI_STATUS Status;
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UINT32 Index;
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UINT32 TpmOutSize;
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UINT16 Data16;
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UINT32 Data32;
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EFI_STATUS Status;
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UINT32 Index;
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UINT32 TpmOutSize;
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UINT16 Data16;
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UINT32 Data32;
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DEBUG_CODE_BEGIN ();
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UINTN DebugSize;
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UINTN DebugSize;
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DEBUG ((DEBUG_VERBOSE, "PtpCrbTpmCommand Send - "));
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if (SizeIn > 0x100) {
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DebugSize = 0x40;
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} else {
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DebugSize = SizeIn;
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}
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for (Index = 0; Index < DebugSize; Index++) {
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DEBUG ((DEBUG_VERBOSE, "PtpCrbTpmCommand Send - "));
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if (SizeIn > 0x100) {
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DebugSize = 0x40;
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} else {
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DebugSize = SizeIn;
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}
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for (Index = 0; Index < DebugSize; Index++) {
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DEBUG ((DEBUG_VERBOSE, "%02x ", BufferIn[Index]));
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}
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if (DebugSize != SizeIn) {
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DEBUG ((DEBUG_VERBOSE, "...... "));
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for (Index = SizeIn - 0x20; Index < SizeIn; Index++) {
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DEBUG ((DEBUG_VERBOSE, "%02x ", BufferIn[Index]));
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}
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if (DebugSize != SizeIn) {
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DEBUG ((DEBUG_VERBOSE, "...... "));
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for (Index = SizeIn - 0x20; Index < SizeIn; Index++) {
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DEBUG ((DEBUG_VERBOSE, "%02x ", BufferIn[Index]));
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}
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}
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DEBUG ((DEBUG_VERBOSE, "\n"));
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}
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DEBUG ((DEBUG_VERBOSE, "\n"));
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DEBUG_CODE_END ();
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TpmOutSize = 0;
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TpmOutSize = 0;
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//
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// STEP 0:
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// if CapCRbIdelByPass == 0, enforce Idle state before sending command
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//
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if (GetCachedIdleByPass () == 0 && (MmioRead32((UINTN)&CrbReg->CrbControlStatus) & PTP_CRB_CONTROL_AREA_STATUS_TPM_IDLE) == 0){
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if ((GetCachedIdleByPass () == 0) && ((MmioRead32 ((UINTN)&CrbReg->CrbControlStatus) & PTP_CRB_CONTROL_AREA_STATUS_TPM_IDLE) == 0)) {
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Status = PtpCrbWaitRegisterBits (
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&CrbReg->CrbControlStatus,
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PTP_CRB_CONTROL_AREA_STATUS_TPM_IDLE,
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0,
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PTP_TIMEOUT_C
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);
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&CrbReg->CrbControlStatus,
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PTP_CRB_CONTROL_AREA_STATUS_TPM_IDLE,
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0,
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PTP_TIMEOUT_C
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);
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if (EFI_ERROR (Status)) {
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//
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// Try to goIdle to recover TPM
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@@ -199,7 +205,7 @@ PtpCrbTpmCommand (
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// of 1 by software to Request.cmdReady, as indicated by the Status field
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// being cleared to 0.
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//
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MmioWrite32((UINTN)&CrbReg->CrbControlRequest, PTP_CRB_CONTROL_AREA_REQUEST_COMMAND_READY);
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MmioWrite32 ((UINTN)&CrbReg->CrbControlRequest, PTP_CRB_CONTROL_AREA_REQUEST_COMMAND_READY);
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Status = PtpCrbWaitRegisterBits (
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&CrbReg->CrbControlRequest,
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0,
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@@ -210,6 +216,7 @@ PtpCrbTpmCommand (
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Status = EFI_DEVICE_ERROR;
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goto GoIdle_Exit;
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}
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Status = PtpCrbWaitRegisterBits (
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&CrbReg->CrbControlStatus,
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0,
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@@ -230,19 +237,20 @@ PtpCrbTpmCommand (
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for (Index = 0; Index < SizeIn; Index++) {
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MmioWrite8 ((UINTN)&CrbReg->CrbDataBuffer[Index], BufferIn[Index]);
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}
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MmioWrite32 ((UINTN)&CrbReg->CrbControlCommandAddressHigh, (UINT32)RShiftU64 ((UINTN)CrbReg->CrbDataBuffer, 32));
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MmioWrite32 ((UINTN)&CrbReg->CrbControlCommandAddressLow, (UINT32)(UINTN)CrbReg->CrbDataBuffer);
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MmioWrite32 ((UINTN)&CrbReg->CrbControlCommandSize, sizeof(CrbReg->CrbDataBuffer));
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MmioWrite32 ((UINTN)&CrbReg->CrbControlCommandSize, sizeof (CrbReg->CrbDataBuffer));
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MmioWrite64 ((UINTN)&CrbReg->CrbControlResponseAddrss, (UINT32)(UINTN)CrbReg->CrbDataBuffer);
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MmioWrite32 ((UINTN)&CrbReg->CrbControlResponseSize, sizeof(CrbReg->CrbDataBuffer));
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MmioWrite32 ((UINTN)&CrbReg->CrbControlResponseSize, sizeof (CrbReg->CrbDataBuffer));
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//
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// STEP 3:
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// Command Execution occurs after receipt of a 1 to Start and the TPM
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// clearing Start to 0.
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//
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MmioWrite32((UINTN)&CrbReg->CrbControlStart, PTP_CRB_CONTROL_START);
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MmioWrite32 ((UINTN)&CrbReg->CrbControlStart, PTP_CRB_CONTROL_START);
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Status = PtpCrbWaitRegisterBits (
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&CrbReg->CrbControlStart,
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0,
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@@ -254,16 +262,16 @@ PtpCrbTpmCommand (
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// Command Completion check timeout. Cancel the currently executing command by writing TPM_CRB_CTRL_CANCEL,
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// Expect TPM_RC_CANCELLED or successfully completed response.
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//
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MmioWrite32((UINTN)&CrbReg->CrbControlCancel, PTP_CRB_CONTROL_CANCEL);
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MmioWrite32 ((UINTN)&CrbReg->CrbControlCancel, PTP_CRB_CONTROL_CANCEL);
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Status = PtpCrbWaitRegisterBits (
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&CrbReg->CrbControlStart,
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0,
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PTP_CRB_CONTROL_START,
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PTP_TIMEOUT_B
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);
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MmioWrite32((UINTN)&CrbReg->CrbControlCancel, 0);
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MmioWrite32 ((UINTN)&CrbReg->CrbControlCancel, 0);
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if (EFI_ERROR(Status)) {
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if (EFI_ERROR (Status)) {
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//
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// Still in Command Execution state. Try to goIdle, the behavior is agnostic.
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//
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@@ -285,12 +293,14 @@ PtpCrbTpmCommand (
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for (Index = 0; Index < sizeof (TPM2_RESPONSE_HEADER); Index++) {
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BufferOut[Index] = MmioRead8 ((UINTN)&CrbReg->CrbDataBuffer[Index]);
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}
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DEBUG_CODE_BEGIN ();
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DEBUG ((DEBUG_VERBOSE, "PtpCrbTpmCommand ReceiveHeader - "));
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for (Index = 0; Index < sizeof (TPM2_RESPONSE_HEADER); Index++) {
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DEBUG ((DEBUG_VERBOSE, "%02x ", BufferOut[Index]));
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}
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DEBUG ((DEBUG_VERBOSE, "\n"));
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DEBUG ((DEBUG_VERBOSE, "PtpCrbTpmCommand ReceiveHeader - "));
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for (Index = 0; Index < sizeof (TPM2_RESPONSE_HEADER); Index++) {
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DEBUG ((DEBUG_VERBOSE, "%02x ", BufferOut[Index]));
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}
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DEBUG ((DEBUG_VERBOSE, "\n"));
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DEBUG_CODE_END ();
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//
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// Check the response data header (tag, parasize and returncode)
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@@ -304,7 +314,7 @@ PtpCrbTpmCommand (
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}
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CopyMem (&Data32, (BufferOut + 2), sizeof (UINT32));
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TpmOutSize = SwapBytes32 (Data32);
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TpmOutSize = SwapBytes32 (Data32);
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if (*SizeOut < TpmOutSize) {
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//
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// Command completed, but buffer is not enough
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@@ -312,6 +322,7 @@ PtpCrbTpmCommand (
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Status = EFI_BUFFER_TOO_SMALL;
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goto GoReady_Exit;
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}
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*SizeOut = TpmOutSize;
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//
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// Continue reading the remaining data
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@@ -321,11 +332,12 @@ PtpCrbTpmCommand (
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}
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DEBUG_CODE_BEGIN ();
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DEBUG ((DEBUG_VERBOSE, "PtpCrbTpmCommand Receive - "));
|
||||
for (Index = 0; Index < TpmOutSize; Index++) {
|
||||
DEBUG ((DEBUG_VERBOSE, "%02x ", BufferOut[Index]));
|
||||
}
|
||||
DEBUG ((DEBUG_VERBOSE, "\n"));
|
||||
DEBUG ((DEBUG_VERBOSE, "PtpCrbTpmCommand Receive - "));
|
||||
for (Index = 0; Index < TpmOutSize; Index++) {
|
||||
DEBUG ((DEBUG_VERBOSE, "%02x ", BufferOut[Index]));
|
||||
}
|
||||
|
||||
DEBUG ((DEBUG_VERBOSE, "\n"));
|
||||
DEBUG_CODE_END ();
|
||||
|
||||
GoReady_Exit:
|
||||
@@ -334,7 +346,7 @@ GoReady_Exit:
|
||||
// If not supported. flow down to GoIdle
|
||||
//
|
||||
if (GetCachedIdleByPass () == 1) {
|
||||
MmioWrite32((UINTN)&CrbReg->CrbControlRequest, PTP_CRB_CONTROL_AREA_REQUEST_COMMAND_READY);
|
||||
MmioWrite32 ((UINTN)&CrbReg->CrbControlRequest, PTP_CRB_CONTROL_AREA_REQUEST_COMMAND_READY);
|
||||
return Status;
|
||||
}
|
||||
|
||||
@@ -347,13 +359,13 @@ GoIdle_Exit:
|
||||
//
|
||||
// Return to Idle state by setting TPM_CRB_CTRL_STS_x.Status.goIdle to 1.
|
||||
//
|
||||
MmioWrite32((UINTN)&CrbReg->CrbControlRequest, PTP_CRB_CONTROL_AREA_REQUEST_GO_IDLE);
|
||||
MmioWrite32 ((UINTN)&CrbReg->CrbControlRequest, PTP_CRB_CONTROL_AREA_REQUEST_GO_IDLE);
|
||||
|
||||
//
|
||||
// Only enforce Idle state transition if execution fails when CRBIdleBypass==1
|
||||
// Leave regular Idle delay at the beginning of next command execution
|
||||
//
|
||||
if (GetCachedIdleByPass () == 1){
|
||||
if (GetCachedIdleByPass () == 1) {
|
||||
Status = PtpCrbWaitRegisterBits (
|
||||
&CrbReg->CrbControlStatus,
|
||||
PTP_CRB_CONTROL_AREA_STATUS_TPM_IDLE,
|
||||
@@ -382,11 +394,11 @@ GoIdle_Exit:
|
||||
**/
|
||||
EFI_STATUS
|
||||
Tpm2TisTpmCommand (
|
||||
IN TIS_PC_REGISTERS_PTR TisReg,
|
||||
IN UINT8 *BufferIn,
|
||||
IN UINT32 SizeIn,
|
||||
IN OUT UINT8 *BufferOut,
|
||||
IN OUT UINT32 *SizeOut
|
||||
IN TIS_PC_REGISTERS_PTR TisReg,
|
||||
IN UINT8 *BufferIn,
|
||||
IN UINT32 SizeIn,
|
||||
IN OUT UINT8 *BufferOut,
|
||||
IN OUT UINT32 *SizeOut
|
||||
);
|
||||
|
||||
/**
|
||||
@@ -402,7 +414,7 @@ Tpm2TisTpmCommand (
|
||||
**/
|
||||
EFI_STATUS
|
||||
TisPcRequestUseTpm (
|
||||
IN TIS_PC_REGISTERS_PTR TisReg
|
||||
IN TIS_PC_REGISTERS_PTR TisReg
|
||||
);
|
||||
|
||||
/**
|
||||
@@ -414,32 +426,37 @@ TisPcRequestUseTpm (
|
||||
**/
|
||||
TPM2_PTP_INTERFACE_TYPE
|
||||
Tpm2GetPtpInterface (
|
||||
IN VOID *Register
|
||||
IN VOID *Register
|
||||
)
|
||||
{
|
||||
PTP_CRB_INTERFACE_IDENTIFIER InterfaceId;
|
||||
PTP_FIFO_INTERFACE_CAPABILITY InterfaceCapability;
|
||||
PTP_CRB_INTERFACE_IDENTIFIER InterfaceId;
|
||||
PTP_FIFO_INTERFACE_CAPABILITY InterfaceCapability;
|
||||
|
||||
if (!Tpm2IsPtpPresence (Register)) {
|
||||
return Tpm2PtpInterfaceMax;
|
||||
}
|
||||
|
||||
//
|
||||
// Check interface id
|
||||
//
|
||||
InterfaceId.Uint32 = MmioRead32 ((UINTN)&((PTP_CRB_REGISTERS *)Register)->InterfaceId);
|
||||
InterfaceId.Uint32 = MmioRead32 ((UINTN)&((PTP_CRB_REGISTERS *)Register)->InterfaceId);
|
||||
InterfaceCapability.Uint32 = MmioRead32 ((UINTN)&((PTP_FIFO_REGISTERS *)Register)->InterfaceCapability);
|
||||
|
||||
if ((InterfaceId.Bits.InterfaceType == PTP_INTERFACE_IDENTIFIER_INTERFACE_TYPE_CRB) &&
|
||||
(InterfaceId.Bits.InterfaceVersion == PTP_INTERFACE_IDENTIFIER_INTERFACE_VERSION_CRB) &&
|
||||
(InterfaceId.Bits.CapCRB != 0)) {
|
||||
(InterfaceId.Bits.CapCRB != 0))
|
||||
{
|
||||
return Tpm2PtpInterfaceCrb;
|
||||
}
|
||||
|
||||
if ((InterfaceId.Bits.InterfaceType == PTP_INTERFACE_IDENTIFIER_INTERFACE_TYPE_FIFO) &&
|
||||
(InterfaceId.Bits.InterfaceVersion == PTP_INTERFACE_IDENTIFIER_INTERFACE_VERSION_FIFO) &&
|
||||
(InterfaceId.Bits.CapFIFO != 0) &&
|
||||
(InterfaceCapability.Bits.InterfaceVersion == INTERFACE_CAPABILITY_INTERFACE_VERSION_PTP)) {
|
||||
(InterfaceCapability.Bits.InterfaceVersion == INTERFACE_CAPABILITY_INTERFACE_VERSION_PTP))
|
||||
{
|
||||
return Tpm2PtpInterfaceFifo;
|
||||
}
|
||||
|
||||
return Tpm2PtpInterfaceTis;
|
||||
}
|
||||
|
||||
@@ -452,7 +469,7 @@ Tpm2GetPtpInterface (
|
||||
**/
|
||||
UINT8
|
||||
Tpm2GetIdleByPass (
|
||||
IN VOID *Register
|
||||
IN VOID *Register
|
||||
)
|
||||
{
|
||||
PTP_CRB_INTERFACE_IDENTIFIER InterfaceId;
|
||||
@@ -472,24 +489,24 @@ Tpm2GetIdleByPass (
|
||||
**/
|
||||
VOID
|
||||
DumpPtpInfo (
|
||||
IN VOID *Register
|
||||
IN VOID *Register
|
||||
)
|
||||
{
|
||||
PTP_CRB_INTERFACE_IDENTIFIER InterfaceId;
|
||||
PTP_FIFO_INTERFACE_CAPABILITY InterfaceCapability;
|
||||
UINT8 StatusEx;
|
||||
UINT16 Vid;
|
||||
UINT16 Did;
|
||||
UINT8 Rid;
|
||||
TPM2_PTP_INTERFACE_TYPE PtpInterface;
|
||||
PTP_CRB_INTERFACE_IDENTIFIER InterfaceId;
|
||||
PTP_FIFO_INTERFACE_CAPABILITY InterfaceCapability;
|
||||
UINT8 StatusEx;
|
||||
UINT16 Vid;
|
||||
UINT16 Did;
|
||||
UINT8 Rid;
|
||||
TPM2_PTP_INTERFACE_TYPE PtpInterface;
|
||||
|
||||
if (!Tpm2IsPtpPresence (Register)) {
|
||||
return ;
|
||||
return;
|
||||
}
|
||||
|
||||
InterfaceId.Uint32 = MmioRead32 ((UINTN)&((PTP_CRB_REGISTERS *)Register)->InterfaceId);
|
||||
InterfaceId.Uint32 = MmioRead32 ((UINTN)&((PTP_CRB_REGISTERS *)Register)->InterfaceId);
|
||||
InterfaceCapability.Uint32 = MmioRead32 ((UINTN)&((PTP_FIFO_REGISTERS *)Register)->InterfaceCapability);
|
||||
StatusEx = MmioRead8 ((UINTN)&((PTP_FIFO_REGISTERS *)Register)->StatusEx);
|
||||
StatusEx = MmioRead8 ((UINTN)&((PTP_FIFO_REGISTERS *)Register)->StatusEx);
|
||||
|
||||
//
|
||||
// Dump InterfaceId Register for PTP
|
||||
@@ -507,7 +524,8 @@ DumpPtpInfo (
|
||||
//
|
||||
DEBUG ((DEBUG_INFO, "InterfaceCapability - 0x%08x\n", InterfaceCapability.Uint32));
|
||||
if ((InterfaceId.Bits.InterfaceType == PTP_INTERFACE_IDENTIFIER_INTERFACE_TYPE_TIS) ||
|
||||
(InterfaceId.Bits.InterfaceType == PTP_INTERFACE_IDENTIFIER_INTERFACE_TYPE_FIFO)) {
|
||||
(InterfaceId.Bits.InterfaceType == PTP_INTERFACE_IDENTIFIER_INTERFACE_TYPE_FIFO))
|
||||
{
|
||||
DEBUG ((DEBUG_INFO, " InterfaceVersion - 0x%x\n", InterfaceCapability.Bits.InterfaceVersion));
|
||||
}
|
||||
|
||||
@@ -519,26 +537,27 @@ DumpPtpInfo (
|
||||
DEBUG ((DEBUG_INFO, " TpmFamily - 0x%x\n", (StatusEx & PTP_FIFO_STS_EX_TPM_FAMILY) >> PTP_FIFO_STS_EX_TPM_FAMILY_OFFSET));
|
||||
}
|
||||
|
||||
Vid = 0xFFFF;
|
||||
Did = 0xFFFF;
|
||||
Rid = 0xFF;
|
||||
Vid = 0xFFFF;
|
||||
Did = 0xFFFF;
|
||||
Rid = 0xFF;
|
||||
PtpInterface = GetCachedPtpInterface ();
|
||||
DEBUG ((DEBUG_INFO, "PtpInterface - %x\n", PtpInterface));
|
||||
switch (PtpInterface) {
|
||||
case Tpm2PtpInterfaceCrb:
|
||||
Vid = MmioRead16 ((UINTN)&((PTP_CRB_REGISTERS *)Register)->Vid);
|
||||
Did = MmioRead16 ((UINTN)&((PTP_CRB_REGISTERS *)Register)->Did);
|
||||
Rid = (UINT8)InterfaceId.Bits.Rid;
|
||||
break;
|
||||
case Tpm2PtpInterfaceFifo:
|
||||
case Tpm2PtpInterfaceTis:
|
||||
Vid = MmioRead16 ((UINTN)&((PTP_FIFO_REGISTERS *)Register)->Vid);
|
||||
Did = MmioRead16 ((UINTN)&((PTP_FIFO_REGISTERS *)Register)->Did);
|
||||
Rid = MmioRead8 ((UINTN)&((PTP_FIFO_REGISTERS *)Register)->Rid);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
case Tpm2PtpInterfaceCrb:
|
||||
Vid = MmioRead16 ((UINTN)&((PTP_CRB_REGISTERS *)Register)->Vid);
|
||||
Did = MmioRead16 ((UINTN)&((PTP_CRB_REGISTERS *)Register)->Did);
|
||||
Rid = (UINT8)InterfaceId.Bits.Rid;
|
||||
break;
|
||||
case Tpm2PtpInterfaceFifo:
|
||||
case Tpm2PtpInterfaceTis:
|
||||
Vid = MmioRead16 ((UINTN)&((PTP_FIFO_REGISTERS *)Register)->Vid);
|
||||
Did = MmioRead16 ((UINTN)&((PTP_FIFO_REGISTERS *)Register)->Did);
|
||||
Rid = MmioRead8 ((UINTN)&((PTP_FIFO_REGISTERS *)Register)->Rid);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
DEBUG ((DEBUG_INFO, "VID - 0x%04x\n", Vid));
|
||||
DEBUG ((DEBUG_INFO, "DID - 0x%04x\n", Did));
|
||||
DEBUG ((DEBUG_INFO, "RID - 0x%02x\n", Rid));
|
||||
@@ -559,35 +578,35 @@ DumpPtpInfo (
|
||||
EFI_STATUS
|
||||
EFIAPI
|
||||
DTpm2SubmitCommand (
|
||||
IN UINT32 InputParameterBlockSize,
|
||||
IN UINT8 *InputParameterBlock,
|
||||
IN OUT UINT32 *OutputParameterBlockSize,
|
||||
IN UINT8 *OutputParameterBlock
|
||||
IN UINT32 InputParameterBlockSize,
|
||||
IN UINT8 *InputParameterBlock,
|
||||
IN OUT UINT32 *OutputParameterBlockSize,
|
||||
IN UINT8 *OutputParameterBlock
|
||||
)
|
||||
{
|
||||
TPM2_PTP_INTERFACE_TYPE PtpInterface;
|
||||
|
||||
PtpInterface = GetCachedPtpInterface ();
|
||||
switch (PtpInterface) {
|
||||
case Tpm2PtpInterfaceCrb:
|
||||
return PtpCrbTpmCommand (
|
||||
(PTP_CRB_REGISTERS_PTR) (UINTN) PcdGet64 (PcdTpmBaseAddress),
|
||||
InputParameterBlock,
|
||||
InputParameterBlockSize,
|
||||
OutputParameterBlock,
|
||||
OutputParameterBlockSize
|
||||
);
|
||||
case Tpm2PtpInterfaceFifo:
|
||||
case Tpm2PtpInterfaceTis:
|
||||
return Tpm2TisTpmCommand (
|
||||
(TIS_PC_REGISTERS_PTR) (UINTN) PcdGet64 (PcdTpmBaseAddress),
|
||||
InputParameterBlock,
|
||||
InputParameterBlockSize,
|
||||
OutputParameterBlock,
|
||||
OutputParameterBlockSize
|
||||
);
|
||||
default:
|
||||
return EFI_NOT_FOUND;
|
||||
case Tpm2PtpInterfaceCrb:
|
||||
return PtpCrbTpmCommand (
|
||||
(PTP_CRB_REGISTERS_PTR)(UINTN)PcdGet64 (PcdTpmBaseAddress),
|
||||
InputParameterBlock,
|
||||
InputParameterBlockSize,
|
||||
OutputParameterBlock,
|
||||
OutputParameterBlockSize
|
||||
);
|
||||
case Tpm2PtpInterfaceFifo:
|
||||
case Tpm2PtpInterfaceTis:
|
||||
return Tpm2TisTpmCommand (
|
||||
(TIS_PC_REGISTERS_PTR)(UINTN)PcdGet64 (PcdTpmBaseAddress),
|
||||
InputParameterBlock,
|
||||
InputParameterBlockSize,
|
||||
OutputParameterBlock,
|
||||
OutputParameterBlockSize
|
||||
);
|
||||
default:
|
||||
return EFI_NOT_FOUND;
|
||||
}
|
||||
}
|
||||
|
||||
@@ -608,12 +627,12 @@ DTpm2RequestUseTpm (
|
||||
|
||||
PtpInterface = GetCachedPtpInterface ();
|
||||
switch (PtpInterface) {
|
||||
case Tpm2PtpInterfaceCrb:
|
||||
return PtpCrbRequestUseTpm ((PTP_CRB_REGISTERS_PTR) (UINTN) PcdGet64 (PcdTpmBaseAddress));
|
||||
case Tpm2PtpInterfaceFifo:
|
||||
case Tpm2PtpInterfaceTis:
|
||||
return TisPcRequestUseTpm ((TIS_PC_REGISTERS_PTR) (UINTN) PcdGet64 (PcdTpmBaseAddress));
|
||||
default:
|
||||
return EFI_NOT_FOUND;
|
||||
case Tpm2PtpInterfaceCrb:
|
||||
return PtpCrbRequestUseTpm ((PTP_CRB_REGISTERS_PTR)(UINTN)PcdGet64 (PcdTpmBaseAddress));
|
||||
case Tpm2PtpInterfaceFifo:
|
||||
case Tpm2PtpInterfaceTis:
|
||||
return TisPcRequestUseTpm ((TIS_PC_REGISTERS_PTR)(UINTN)PcdGet64 (PcdTpmBaseAddress));
|
||||
default:
|
||||
return EFI_NOT_FOUND;
|
||||
}
|
||||
}
|
||||
|
@@ -19,12 +19,12 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
|
||||
|
||||
#include <IndustryStandard/TpmTis.h>
|
||||
|
||||
#define TIS_TIMEOUT_MAX (90000 * 1000) // 90s
|
||||
#define TIS_TIMEOUT_MAX (90000 * 1000) // 90s
|
||||
|
||||
//
|
||||
// Max TPM command/response length
|
||||
//
|
||||
#define TPMCMDBUFLENGTH 0x500
|
||||
#define TPMCMDBUFLENGTH 0x500
|
||||
|
||||
/**
|
||||
Check whether TPM chip exist.
|
||||
@@ -36,10 +36,10 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
|
||||
**/
|
||||
BOOLEAN
|
||||
TisPcPresenceCheck (
|
||||
IN TIS_PC_REGISTERS_PTR TisReg
|
||||
IN TIS_PC_REGISTERS_PTR TisReg
|
||||
)
|
||||
{
|
||||
UINT8 RegRead;
|
||||
UINT8 RegRead;
|
||||
|
||||
RegRead = MmioRead8 ((UINTN)&TisReg->Access);
|
||||
return (BOOLEAN)(RegRead != (UINT8)-1);
|
||||
@@ -58,21 +58,24 @@ TisPcPresenceCheck (
|
||||
**/
|
||||
EFI_STATUS
|
||||
TisPcWaitRegisterBits (
|
||||
IN UINT8 *Register,
|
||||
IN UINT8 BitSet,
|
||||
IN UINT8 BitClear,
|
||||
IN UINT32 TimeOut
|
||||
IN UINT8 *Register,
|
||||
IN UINT8 BitSet,
|
||||
IN UINT8 BitClear,
|
||||
IN UINT32 TimeOut
|
||||
)
|
||||
{
|
||||
UINT8 RegRead;
|
||||
UINT32 WaitTime;
|
||||
UINT8 RegRead;
|
||||
UINT32 WaitTime;
|
||||
|
||||
for (WaitTime = 0; WaitTime < TimeOut; WaitTime += 30){
|
||||
for (WaitTime = 0; WaitTime < TimeOut; WaitTime += 30) {
|
||||
RegRead = MmioRead8 ((UINTN)Register);
|
||||
if ((RegRead & BitSet) == BitSet && (RegRead & BitClear) == 0)
|
||||
if (((RegRead & BitSet) == BitSet) && ((RegRead & BitClear) == 0)) {
|
||||
return EFI_SUCCESS;
|
||||
}
|
||||
|
||||
MicroSecondDelay (30);
|
||||
}
|
||||
|
||||
return EFI_TIMEOUT;
|
||||
}
|
||||
|
||||
@@ -89,15 +92,15 @@ TisPcWaitRegisterBits (
|
||||
**/
|
||||
EFI_STATUS
|
||||
TisPcReadBurstCount (
|
||||
IN TIS_PC_REGISTERS_PTR TisReg,
|
||||
OUT UINT16 *BurstCount
|
||||
IN TIS_PC_REGISTERS_PTR TisReg,
|
||||
OUT UINT16 *BurstCount
|
||||
)
|
||||
{
|
||||
UINT32 WaitTime;
|
||||
UINT8 DataByte0;
|
||||
UINT8 DataByte1;
|
||||
UINT32 WaitTime;
|
||||
UINT8 DataByte0;
|
||||
UINT8 DataByte1;
|
||||
|
||||
if (BurstCount == NULL || TisReg == NULL) {
|
||||
if ((BurstCount == NULL) || (TisReg == NULL)) {
|
||||
return EFI_INVALID_PARAMETER;
|
||||
}
|
||||
|
||||
@@ -113,6 +116,7 @@ TisPcReadBurstCount (
|
||||
if (*BurstCount != 0) {
|
||||
return EFI_SUCCESS;
|
||||
}
|
||||
|
||||
MicroSecondDelay (30);
|
||||
WaitTime += 30;
|
||||
} while (WaitTime < TIS_TIMEOUT_D);
|
||||
@@ -132,16 +136,16 @@ TisPcReadBurstCount (
|
||||
**/
|
||||
EFI_STATUS
|
||||
TisPcPrepareCommand (
|
||||
IN TIS_PC_REGISTERS_PTR TisReg
|
||||
IN TIS_PC_REGISTERS_PTR TisReg
|
||||
)
|
||||
{
|
||||
EFI_STATUS Status;
|
||||
EFI_STATUS Status;
|
||||
|
||||
if (TisReg == NULL) {
|
||||
return EFI_INVALID_PARAMETER;
|
||||
}
|
||||
|
||||
MmioWrite8((UINTN)&TisReg->Status, TIS_PC_STS_READY);
|
||||
MmioWrite8 ((UINTN)&TisReg->Status, TIS_PC_STS_READY);
|
||||
Status = TisPcWaitRegisterBits (
|
||||
&TisReg->Status,
|
||||
TIS_PC_STS_READY,
|
||||
@@ -164,10 +168,10 @@ TisPcPrepareCommand (
|
||||
**/
|
||||
EFI_STATUS
|
||||
TisPcRequestUseTpm (
|
||||
IN TIS_PC_REGISTERS_PTR TisReg
|
||||
IN TIS_PC_REGISTERS_PTR TisReg
|
||||
)
|
||||
{
|
||||
EFI_STATUS Status;
|
||||
EFI_STATUS Status;
|
||||
|
||||
if (TisReg == NULL) {
|
||||
return EFI_INVALID_PARAMETER;
|
||||
@@ -177,7 +181,7 @@ TisPcRequestUseTpm (
|
||||
return EFI_NOT_FOUND;
|
||||
}
|
||||
|
||||
MmioWrite8((UINTN)&TisReg->Access, TIS_PC_ACC_RQUUSE);
|
||||
MmioWrite8 ((UINTN)&TisReg->Access, TIS_PC_ACC_RQUUSE);
|
||||
Status = TisPcWaitRegisterBits (
|
||||
&TisReg->Access,
|
||||
(UINT8)(TIS_PC_ACC_ACTIVE |TIS_PC_VALID),
|
||||
@@ -204,47 +208,51 @@ TisPcRequestUseTpm (
|
||||
**/
|
||||
EFI_STATUS
|
||||
Tpm2TisTpmCommand (
|
||||
IN TIS_PC_REGISTERS_PTR TisReg,
|
||||
IN UINT8 *BufferIn,
|
||||
IN UINT32 SizeIn,
|
||||
IN OUT UINT8 *BufferOut,
|
||||
IN OUT UINT32 *SizeOut
|
||||
IN TIS_PC_REGISTERS_PTR TisReg,
|
||||
IN UINT8 *BufferIn,
|
||||
IN UINT32 SizeIn,
|
||||
IN OUT UINT8 *BufferOut,
|
||||
IN OUT UINT32 *SizeOut
|
||||
)
|
||||
{
|
||||
EFI_STATUS Status;
|
||||
UINT16 BurstCount;
|
||||
UINT32 Index;
|
||||
UINT32 TpmOutSize;
|
||||
UINT16 Data16;
|
||||
UINT32 Data32;
|
||||
EFI_STATUS Status;
|
||||
UINT16 BurstCount;
|
||||
UINT32 Index;
|
||||
UINT32 TpmOutSize;
|
||||
UINT16 Data16;
|
||||
UINT32 Data32;
|
||||
|
||||
DEBUG_CODE_BEGIN ();
|
||||
UINTN DebugSize;
|
||||
UINTN DebugSize;
|
||||
|
||||
DEBUG ((DEBUG_VERBOSE, "Tpm2TisTpmCommand Send - "));
|
||||
if (SizeIn > 0x100) {
|
||||
DebugSize = 0x40;
|
||||
} else {
|
||||
DebugSize = SizeIn;
|
||||
}
|
||||
for (Index = 0; Index < DebugSize; Index++) {
|
||||
DEBUG ((DEBUG_VERBOSE, "Tpm2TisTpmCommand Send - "));
|
||||
if (SizeIn > 0x100) {
|
||||
DebugSize = 0x40;
|
||||
} else {
|
||||
DebugSize = SizeIn;
|
||||
}
|
||||
|
||||
for (Index = 0; Index < DebugSize; Index++) {
|
||||
DEBUG ((DEBUG_VERBOSE, "%02x ", BufferIn[Index]));
|
||||
}
|
||||
|
||||
if (DebugSize != SizeIn) {
|
||||
DEBUG ((DEBUG_VERBOSE, "...... "));
|
||||
for (Index = SizeIn - 0x20; Index < SizeIn; Index++) {
|
||||
DEBUG ((DEBUG_VERBOSE, "%02x ", BufferIn[Index]));
|
||||
}
|
||||
if (DebugSize != SizeIn) {
|
||||
DEBUG ((DEBUG_VERBOSE, "...... "));
|
||||
for (Index = SizeIn - 0x20; Index < SizeIn; Index++) {
|
||||
DEBUG ((DEBUG_VERBOSE, "%02x ", BufferIn[Index]));
|
||||
}
|
||||
}
|
||||
DEBUG ((DEBUG_VERBOSE, "\n"));
|
||||
}
|
||||
|
||||
DEBUG ((DEBUG_VERBOSE, "\n"));
|
||||
DEBUG_CODE_END ();
|
||||
TpmOutSize = 0;
|
||||
|
||||
Status = TisPcPrepareCommand (TisReg);
|
||||
if (EFI_ERROR (Status)){
|
||||
if (EFI_ERROR (Status)) {
|
||||
DEBUG ((DEBUG_ERROR, "Tpm2 is not ready for command!\n"));
|
||||
return EFI_DEVICE_ERROR;
|
||||
}
|
||||
|
||||
//
|
||||
// Send the command data to Tpm
|
||||
//
|
||||
@@ -255,17 +263,19 @@ Tpm2TisTpmCommand (
|
||||
Status = EFI_DEVICE_ERROR;
|
||||
goto Exit;
|
||||
}
|
||||
for (; BurstCount > 0 && Index < SizeIn; BurstCount--) {
|
||||
MmioWrite8((UINTN)&TisReg->DataFifo, *(BufferIn + Index));
|
||||
|
||||
for ( ; BurstCount > 0 && Index < SizeIn; BurstCount--) {
|
||||
MmioWrite8 ((UINTN)&TisReg->DataFifo, *(BufferIn + Index));
|
||||
Index++;
|
||||
}
|
||||
}
|
||||
|
||||
//
|
||||
// Check the Tpm status STS_EXPECT change from 1 to 0
|
||||
//
|
||||
Status = TisPcWaitRegisterBits (
|
||||
&TisReg->Status,
|
||||
(UINT8) TIS_PC_VALID,
|
||||
(UINT8)TIS_PC_VALID,
|
||||
TIS_PC_STS_EXPECT,
|
||||
TIS_TIMEOUT_C
|
||||
);
|
||||
@@ -274,17 +284,18 @@ Tpm2TisTpmCommand (
|
||||
Status = EFI_BUFFER_TOO_SMALL;
|
||||
goto Exit;
|
||||
}
|
||||
|
||||
//
|
||||
// Executed the TPM command and waiting for the response data ready
|
||||
//
|
||||
MmioWrite8((UINTN)&TisReg->Status, TIS_PC_STS_GO);
|
||||
MmioWrite8 ((UINTN)&TisReg->Status, TIS_PC_STS_GO);
|
||||
|
||||
//
|
||||
// NOTE: That may take many seconds to minutes for certain commands, such as key generation.
|
||||
//
|
||||
Status = TisPcWaitRegisterBits (
|
||||
&TisReg->Status,
|
||||
(UINT8) (TIS_PC_VALID | TIS_PC_STS_DATA),
|
||||
(UINT8)(TIS_PC_VALID | TIS_PC_STS_DATA),
|
||||
0,
|
||||
TIS_TIMEOUT_MAX
|
||||
);
|
||||
@@ -295,10 +306,10 @@ Tpm2TisTpmCommand (
|
||||
//
|
||||
DEBUG ((DEBUG_ERROR, "Wait for Tpm2 response data time out. Trying to cancel the command!!\n"));
|
||||
|
||||
MmioWrite32((UINTN)&TisReg->Status, TIS_PC_STS_CANCEL);
|
||||
MmioWrite32 ((UINTN)&TisReg->Status, TIS_PC_STS_CANCEL);
|
||||
Status = TisPcWaitRegisterBits (
|
||||
&TisReg->Status,
|
||||
(UINT8) (TIS_PC_VALID | TIS_PC_STS_DATA),
|
||||
(UINT8)(TIS_PC_VALID | TIS_PC_STS_DATA),
|
||||
0,
|
||||
TIS_TIMEOUT_B
|
||||
);
|
||||
@@ -318,7 +329,7 @@ Tpm2TisTpmCommand (
|
||||
//
|
||||
// Get response data header
|
||||
//
|
||||
Index = 0;
|
||||
Index = 0;
|
||||
BurstCount = 0;
|
||||
while (Index < sizeof (TPM2_RESPONSE_HEADER)) {
|
||||
Status = TisPcReadBurstCount (TisReg, &BurstCount);
|
||||
@@ -326,18 +337,23 @@ Tpm2TisTpmCommand (
|
||||
Status = EFI_DEVICE_ERROR;
|
||||
goto Exit;
|
||||
}
|
||||
for (; BurstCount > 0; BurstCount--) {
|
||||
|
||||
for ( ; BurstCount > 0; BurstCount--) {
|
||||
*(BufferOut + Index) = MmioRead8 ((UINTN)&TisReg->DataFifo);
|
||||
Index++;
|
||||
if (Index == sizeof (TPM2_RESPONSE_HEADER)) break;
|
||||
if (Index == sizeof (TPM2_RESPONSE_HEADER)) {
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
DEBUG_CODE_BEGIN ();
|
||||
DEBUG ((DEBUG_VERBOSE, "Tpm2TisTpmCommand ReceiveHeader - "));
|
||||
for (Index = 0; Index < sizeof (TPM2_RESPONSE_HEADER); Index++) {
|
||||
DEBUG ((DEBUG_VERBOSE, "%02x ", BufferOut[Index]));
|
||||
}
|
||||
DEBUG ((DEBUG_VERBOSE, "\n"));
|
||||
DEBUG ((DEBUG_VERBOSE, "Tpm2TisTpmCommand ReceiveHeader - "));
|
||||
for (Index = 0; Index < sizeof (TPM2_RESPONSE_HEADER); Index++) {
|
||||
DEBUG ((DEBUG_VERBOSE, "%02x ", BufferOut[Index]));
|
||||
}
|
||||
|
||||
DEBUG ((DEBUG_VERBOSE, "\n"));
|
||||
DEBUG_CODE_END ();
|
||||
//
|
||||
// Check the response data header (tag,parasize and returncode )
|
||||
@@ -351,17 +367,18 @@ Tpm2TisTpmCommand (
|
||||
}
|
||||
|
||||
CopyMem (&Data32, (BufferOut + 2), sizeof (UINT32));
|
||||
TpmOutSize = SwapBytes32 (Data32);
|
||||
TpmOutSize = SwapBytes32 (Data32);
|
||||
if (*SizeOut < TpmOutSize) {
|
||||
Status = EFI_BUFFER_TOO_SMALL;
|
||||
goto Exit;
|
||||
}
|
||||
|
||||
*SizeOut = TpmOutSize;
|
||||
//
|
||||
// Continue reading the remaining data
|
||||
//
|
||||
while ( Index < TpmOutSize ) {
|
||||
for (; BurstCount > 0; BurstCount--) {
|
||||
for ( ; BurstCount > 0; BurstCount--) {
|
||||
*(BufferOut + Index) = MmioRead8 ((UINTN)&TisReg->DataFifo);
|
||||
Index++;
|
||||
if (Index == TpmOutSize) {
|
||||
@@ -369,21 +386,24 @@ Tpm2TisTpmCommand (
|
||||
goto Exit;
|
||||
}
|
||||
}
|
||||
|
||||
Status = TisPcReadBurstCount (TisReg, &BurstCount);
|
||||
if (EFI_ERROR (Status)) {
|
||||
Status = EFI_DEVICE_ERROR;
|
||||
goto Exit;
|
||||
}
|
||||
}
|
||||
|
||||
Exit:
|
||||
DEBUG_CODE_BEGIN ();
|
||||
DEBUG ((DEBUG_VERBOSE, "Tpm2TisTpmCommand Receive - "));
|
||||
for (Index = 0; Index < TpmOutSize; Index++) {
|
||||
DEBUG ((DEBUG_VERBOSE, "%02x ", BufferOut[Index]));
|
||||
}
|
||||
DEBUG ((DEBUG_VERBOSE, "\n"));
|
||||
DEBUG ((DEBUG_VERBOSE, "Tpm2TisTpmCommand Receive - "));
|
||||
for (Index = 0; Index < TpmOutSize; Index++) {
|
||||
DEBUG ((DEBUG_VERBOSE, "%02x ", BufferOut[Index]));
|
||||
}
|
||||
|
||||
DEBUG ((DEBUG_VERBOSE, "\n"));
|
||||
DEBUG_CODE_END ();
|
||||
MmioWrite8((UINTN)&TisReg->Status, TIS_PC_STS_READY);
|
||||
MmioWrite8 ((UINTN)&TisReg->Status, TIS_PC_STS_READY);
|
||||
return Status;
|
||||
}
|
||||
|
||||
@@ -402,14 +422,14 @@ Exit:
|
||||
EFI_STATUS
|
||||
EFIAPI
|
||||
DTpm2TisSubmitCommand (
|
||||
IN UINT32 InputParameterBlockSize,
|
||||
IN UINT8 *InputParameterBlock,
|
||||
IN OUT UINT32 *OutputParameterBlockSize,
|
||||
IN UINT8 *OutputParameterBlock
|
||||
IN UINT32 InputParameterBlockSize,
|
||||
IN UINT8 *InputParameterBlock,
|
||||
IN OUT UINT32 *OutputParameterBlockSize,
|
||||
IN UINT8 *OutputParameterBlock
|
||||
)
|
||||
{
|
||||
return Tpm2TisTpmCommand (
|
||||
(TIS_PC_REGISTERS_PTR) (UINTN) PcdGet64 (PcdTpmBaseAddress),
|
||||
(TIS_PC_REGISTERS_PTR)(UINTN)PcdGet64 (PcdTpmBaseAddress),
|
||||
InputParameterBlock,
|
||||
InputParameterBlockSize,
|
||||
OutputParameterBlock,
|
||||
@@ -430,5 +450,5 @@ DTpm2TisRequestUseTpm (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
return TisPcRequestUseTpm ((TIS_PC_REGISTERS_PTR) (UINTN) PcdGet64 (PcdTpmBaseAddress));
|
||||
return TisPcRequestUseTpm ((TIS_PC_REGISTERS_PTR)(UINTN)PcdGet64 (PcdTpmBaseAddress));
|
||||
}
|
||||
|
Reference in New Issue
Block a user