ArmPlatformPkg/PL35xSmc: Clean SMC driver to replace hardcoded Chip Select into the driver itself by passing SMC configuration to the driver
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@11959 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
oliviermartin
@@ -18,136 +18,35 @@
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INCLUDE AsmMacroIoLib.inc
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EXPORT SMCInitializeNOR
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EXPORT SMCInitializeSRAM
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EXPORT SMCInitializePeripherals
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EXPORT SMCInitializeVRAM
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EXPORT PL35xSmcInitialize
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PRESERVE8
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AREA ModuleInitializeSMC, CODE, READONLY
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// CS0 CS0-Interf0 NOR1 flash on the motherboard
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// CS1 CS1-Interf0 Reserved for the motherboard
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// CS2 CS2-Interf0 SRAM on the motherboard
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// CS3 CS3-Interf0 memory-mapped Ethernet and USB controllers on the motherboard
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// CS4 CS0-Interf1 NOR2 flash on the motherboard
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// CS5 CS1-Interf1 memory-mapped peripherals
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// CS6 CS2-Interf1 memory-mapped peripherals
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// CS7 CS3-Interf1 system memory-mapped peripherals on the motherboard.
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// IN r1 SmcBase
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// IN r2 ChipSelect
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// IN r1 Smc Base Address
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// IN r2 Smc Configuration Start Address
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// IN r3 Smc Configuration End Address
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// NOTE: This code is been called before any stack has been setup. It means some registers
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// could be overwritten (case of 'r0')
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SMCInitializeNOR
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PL35xSmcInitialize
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// While (SmcConfigurationStart < SmcConfigurationEnd)
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cmp r2, r3
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blxge lr
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// Write to set_cycle register(holding register for NOR 1 cycle register or NAND cycle register)
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// - Read cycle timeout = 0xA (0:3)
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// - Write cycle timeout = 0x3(7:4)
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// - OE Assertion Delay = 0x9(11:8)
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// - WE Assertion delay = 0x3(15:12)
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// - Page cycle timeout = 0x2(19:16)
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ldr r0, = 0x0002393A
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str r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]
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ldr r0, [r2, #0x4]
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str r0, [r1, #PL350_SMC_SET_CYCLES_OFFSET]
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// Write to set_opmode register(holding register for NOR 1 opomode register or NAND opmode register)
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ldr r0, = (PL354_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL354_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_CONT :OR: PL354_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_CONT :OR: PL354_SMC_SET_OPMODE_SET_ADV)
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str r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]
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ldr r0, [r2, #0x8]
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str r0, [r1, #PL350_SMC_SET_OPMODE_OFFSET]
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// Write to direct_cmd register so that the NOR 1 registers(set-cycles and opmode) are updated with holding registers
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ldr r0, =PL354_SMC_DIRECT_CMD_ADDR_CMD_UPDATE
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orr r0, r0, r2
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str r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]
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bx lr
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ldr r0, =PL350_SMC_DIRECT_CMD_ADDR_CMD_UPDATE
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ldr r4, [r2, #0x0]
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orr r0, r0, r4
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str r0, [r1, #PL350_SMC_DIRECT_CMD_OFFSET]
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add r2, #0xC
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b PL35xSmcInitialize
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//
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// Setup SRAM (CS2-Interface0)
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//
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SMCInitializeSRAM
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ldr r0, = 0x00027158
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str r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]
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ldr r0, =(PL354_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL354_SMC_SET_OPMODE_SET_ADV)
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str r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]
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ldr r0, =(PL354_SMC_DIRECT_CMD_ADDR_CMD_UPDATE :OR: PL354_SMC_DIRECT_CMD_ADDR_CS(0,2))
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str r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]
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bx lr
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SMCInitializePeripherals
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//
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// USB/Eth/VRAM (CS3-Interface0)
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//
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ldr r0, = 0x000CD2AA
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str r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]
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ldr r0, =(PL354_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL354_SMC_SET_OPMODE_SET_RD_SYNC :OR: PL354_SMC_SET_OPMODE_SET_WR_SYNC)
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str r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]
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ldr r0, =(PL354_SMC_DIRECT_CMD_ADDR_CMD_UPDATE :OR: PL354_SMC_DIRECT_CMD_ADDR_CS(0,3))
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str r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]
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//
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// Setup Peripherals (CS3-Interface1)
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//
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ldr r0, = 0x00025156
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str r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]
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ldr r0, =(PL354_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL354_SMC_SET_OPMODE_SET_RD_SYNC :OR: PL354_SMC_SET_OPMODE_SET_WR_SYNC)
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str r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]
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ldr r0, =(PL354_SMC_DIRECT_CMD_ADDR_CMD_UPDATE :OR: PL354_SMC_DIRECT_CMD_ADDR_CS(1,3))
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str r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]
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bx lr
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// IN r1 SmcBase
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// IN r2 VideoSRamBase
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// NOTE: This code is been called before any stack has been setup. It means some registers
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// could be overwritten (case of 'r0')
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SMCInitializeVRAM
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//
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// Setup VRAM (CS1-Interface0)
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//
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ldr r0, = 0x00049249
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str r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]
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ldr r0, = (PL354_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL354_SMC_SET_OPMODE_SET_RD_SYNC :OR: PL354_SMC_SET_OPMODE_SET_WR_SYNC)
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str r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]
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ldr r0, = (PL354_SMC_DIRECT_CMD_ADDR_CMD_UPDATE :OR: PL354_SMC_DIRECT_CMD_ADDR_CS(0,1))
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str r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]
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//
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// Page mode setup for VRAM
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//
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// Read current state
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ldr r0, [r2, #0]
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ldr r0, [r2, #0]
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ldr r0, = 0x00000000
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str r0, [r2, #0]
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ldr r0, [r2, #0]
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// Enable page mode
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ldr r0, [r2, #0]
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ldr r0, [r2, #0]
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ldr r0, = 0x00000000
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str r0, [r2, #0]
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ldr r0, = 0x00900090
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str r0, [r2, #0]
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// Confirm page mode enabled
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ldr r0, [r2, #0]
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ldr r0, [r2, #0]
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ldr r0, = 0x00000000
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str r0, [r2, #0]
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ldr r0, [r2, #0]
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bx lr
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END
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