Use CPU_HOB to detect max address support from platform, and added 1G page table support.
Sign-off-by: jyao1 Reviewed-by: li-elvin git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12332 6f19259b-4bc3-4df7-8a09-765794883524
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@@ -2,7 +2,7 @@
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This is an implementation of the ACPI S3 Save protocol. This is defined in
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S3 boot path specification 0.9.
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Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
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Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions
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@@ -18,7 +18,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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#ifndef _ACPI_S3_SAVE_H_
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#define _ACPI_S3_SAVE_H_
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#pragma pack(push, 1)
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#pragma pack(1)
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typedef union {
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struct {
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@@ -92,6 +92,30 @@ typedef union {
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UINT64 Uint64;
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} PAGE_TABLE_ENTRY;
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//
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// Page Table Entry 1GB
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//
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typedef union {
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struct {
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UINT64 Present:1; // 0 = Not present in memory, 1 = Present in memory
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UINT64 ReadWrite:1; // 0 = Read-Only, 1= Read/Write
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UINT64 UserSupervisor:1; // 0 = Supervisor, 1=User
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UINT64 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching
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UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached
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UINT64 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU)
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UINT64 Dirty:1; // 0 = Not Dirty, 1 = written by processor on access to page
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UINT64 MustBe1:1; // Must be 1
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UINT64 Global:1; // 0 = Not global page, 1 = global page TLB not cleared on CR3 write
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UINT64 Available:3; // Available for use by system software
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UINT64 PAT:1; //
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UINT64 MustBeZero:17; // Must be zero;
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UINT64 PageTableBaseAddress:22; // Page Table Base Address
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UINT64 AvabilableHigh:11; // Available for use by system software
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UINT64 Nx:1; // 0 = Execute Code, 1 = No Code Execution
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} Bits;
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UINT64 Uint64;
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} PAGE_TABLE_1G_ENTRY;
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#pragma pack()
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/**
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