Use CPU_HOB to detect max address support from platform, and added 1G page table support.
Sign-off-by: jyao1 Reviewed-by: li-elvin git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12332 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
@@ -15,7 +15,7 @@
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2) IA-32 Intel(R) Architecture Software Developer's Manual Volume 2:Instruction Set Reference, Intel
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3) IA-32 Intel(R) Architecture Software Developer's Manual Volume 3:System Programmer's Guide, Intel
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Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
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Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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@@ -46,6 +46,8 @@ CreateIdentityMappingPageTables (
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VOID
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)
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{
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UINT32 RegEax;
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UINT32 RegEdx;
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UINT8 PhysicalAddressBits;
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EFI_PHYSICAL_ADDRESS PageAddress;
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UINTN IndexOfPml4Entries;
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@@ -60,15 +62,32 @@ CreateIdentityMappingPageTables (
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UINTN TotalPagesNum;
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UINTN BigPageAddress;
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VOID *Hob;
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BOOLEAN Page1GSupport;
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PAGE_TABLE_1G_ENTRY *PageDirectory1GEntry;
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Page1GSupport = FALSE;
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AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);
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if (RegEax >= 0x80000001) {
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AsmCpuid (0x80000001, NULL, NULL, NULL, &RegEdx);
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if ((RegEdx & BIT26) != 0) {
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Page1GSupport = TRUE;
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}
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}
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//
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// Get physical address bits supported from CPU HOB.
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// Get physical address bits supported.
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//
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PhysicalAddressBits = 36;
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Hob = GetFirstHob (EFI_HOB_TYPE_CPU);
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if (Hob != NULL) {
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PhysicalAddressBits = ((EFI_HOB_CPU *) Hob)->SizeOfMemorySpace;
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} else {
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AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);
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if (RegEax >= 0x80000008) {
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AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL);
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PhysicalAddressBits = (UINT8) RegEax;
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} else {
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PhysicalAddressBits = 36;
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}
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}
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//
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@@ -84,16 +103,20 @@ CreateIdentityMappingPageTables (
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//
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if (PhysicalAddressBits <= 39 ) {
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NumberOfPml4EntriesNeeded = 1;
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NumberOfPdpEntriesNeeded = 1 << (PhysicalAddressBits - 30);
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NumberOfPdpEntriesNeeded = (UINT32)LShiftU64 (1, (PhysicalAddressBits - 30));
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} else {
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NumberOfPml4EntriesNeeded = 1 << (PhysicalAddressBits - 39);
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NumberOfPml4EntriesNeeded = (UINT32)LShiftU64 (1, (PhysicalAddressBits - 39));
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NumberOfPdpEntriesNeeded = 512;
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}
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//
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// Pre-allocate big pages to avoid later allocations.
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//
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TotalPagesNum = (NumberOfPdpEntriesNeeded + 1) * NumberOfPml4EntriesNeeded + 1;
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if (!Page1GSupport) {
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TotalPagesNum = (NumberOfPdpEntriesNeeded + 1) * NumberOfPml4EntriesNeeded + 1;
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} else {
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TotalPagesNum = NumberOfPml4EntriesNeeded + 1;
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}
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BigPageAddress = (UINTN) AllocatePages (TotalPagesNum);
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ASSERT (BigPageAddress != 0);
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@@ -101,7 +124,7 @@ CreateIdentityMappingPageTables (
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// By architecture only one PageMapLevel4 exists - so lets allocate storage for it.
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//
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PageMap = (VOID *) BigPageAddress;
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BigPageAddress += EFI_PAGE_SIZE;
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BigPageAddress += SIZE_4KB;
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PageMapLevel4Entry = PageMap;
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PageAddress = 0;
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@@ -111,7 +134,7 @@ CreateIdentityMappingPageTables (
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// So lets allocate space for them and fill them in in the IndexOfPdpEntries loop.
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//
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PageDirectoryPointerEntry = (VOID *) BigPageAddress;
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BigPageAddress += EFI_PAGE_SIZE;
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BigPageAddress += SIZE_4KB;
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//
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// Make a PML4 Entry
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@@ -120,44 +143,63 @@ CreateIdentityMappingPageTables (
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PageMapLevel4Entry->Bits.ReadWrite = 1;
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PageMapLevel4Entry->Bits.Present = 1;
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for (IndexOfPdpEntries = 0; IndexOfPdpEntries < NumberOfPdpEntriesNeeded; IndexOfPdpEntries++, PageDirectoryPointerEntry++) {
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//
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// Each Directory Pointer entries points to a page of Page Directory entires.
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// So allocate space for them and fill them in in the IndexOfPageDirectoryEntries loop.
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//
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PageDirectoryEntry = (VOID *) BigPageAddress;
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BigPageAddress += EFI_PAGE_SIZE;
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//
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// Fill in a Page Directory Pointer Entries
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//
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PageDirectoryPointerEntry->Uint64 = (UINT64)(UINTN)PageDirectoryEntry;
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PageDirectoryPointerEntry->Bits.ReadWrite = 1;
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PageDirectoryPointerEntry->Bits.Present = 1;
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for (IndexOfPageDirectoryEntries = 0; IndexOfPageDirectoryEntries < 512; IndexOfPageDirectoryEntries++, PageDirectoryEntry++, PageAddress += 0x200000) {
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if (Page1GSupport) {
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PageDirectory1GEntry = (VOID *) BigPageAddress;
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BigPageAddress += SIZE_4KB;
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for (IndexOfPageDirectoryEntries = 0; IndexOfPageDirectoryEntries < 512; IndexOfPageDirectoryEntries++, PageDirectory1GEntry++, PageAddress += SIZE_1GB) {
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//
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// Fill in the Page Directory entries
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//
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PageDirectoryEntry->Uint64 = (UINT64)PageAddress;
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PageDirectoryEntry->Bits.ReadWrite = 1;
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PageDirectoryEntry->Bits.Present = 1;
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PageDirectoryEntry->Bits.MustBe1 = 1;
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PageDirectory1GEntry->Uint64 = (UINT64)PageAddress;
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PageDirectory1GEntry->Bits.ReadWrite = 1;
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PageDirectory1GEntry->Bits.Present = 1;
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PageDirectory1GEntry->Bits.MustBe1 = 1;
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}
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} else {
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for (IndexOfPdpEntries = 0; IndexOfPdpEntries < NumberOfPdpEntriesNeeded; IndexOfPdpEntries++, PageDirectoryPointerEntry++) {
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//
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// Each Directory Pointer entries points to a page of Page Directory entires.
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// So allocate space for them and fill them in in the IndexOfPageDirectoryEntries loop.
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//
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PageDirectoryEntry = (VOID *) BigPageAddress;
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BigPageAddress += SIZE_4KB;
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//
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// Fill in a Page Directory Pointer Entries
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//
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PageDirectoryPointerEntry->Uint64 = (UINT64)(UINTN)PageDirectoryEntry;
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PageDirectoryPointerEntry->Bits.ReadWrite = 1;
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PageDirectoryPointerEntry->Bits.Present = 1;
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for (IndexOfPageDirectoryEntries = 0; IndexOfPageDirectoryEntries < 512; IndexOfPageDirectoryEntries++, PageDirectoryEntry++, PageAddress += SIZE_2MB) {
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//
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// Fill in the Page Directory entries
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//
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PageDirectoryEntry->Uint64 = (UINT64)PageAddress;
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PageDirectoryEntry->Bits.ReadWrite = 1;
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PageDirectoryEntry->Bits.Present = 1;
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PageDirectoryEntry->Bits.MustBe1 = 1;
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}
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}
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for (; IndexOfPdpEntries < 512; IndexOfPdpEntries++, PageDirectoryPointerEntry++) {
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ZeroMem (
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PageDirectoryPointerEntry,
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sizeof(PAGE_MAP_AND_DIRECTORY_POINTER)
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);
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}
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}
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}
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//
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// For the PML4 entries we are not using fill in a null entry.
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// For now we just copy the first entry.
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//
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for (; IndexOfPml4Entries < 512; IndexOfPml4Entries++, PageMapLevel4Entry++) {
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CopyMem (
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PageMapLevel4Entry,
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PageMap,
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sizeof (PAGE_MAP_AND_DIRECTORY_POINTER)
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);
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ZeroMem (
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PageMapLevel4Entry,
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sizeof (PAGE_MAP_AND_DIRECTORY_POINTER)
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);
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}
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return (UINTN)PageMap;
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@@ -7,7 +7,7 @@
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3) IA-32 Intel(R) Architecture Software Developer's Manual Volume 3:System Programmer's Guide, Intel
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4) AMD64 Architecture Programmer's Manual Volume 2: System Programming
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Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
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Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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@@ -97,6 +97,30 @@ typedef union {
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UINT64 Uint64;
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} PAGE_TABLE_ENTRY;
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//
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// Page Table Entry 1GB
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//
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typedef union {
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struct {
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UINT64 Present:1; // 0 = Not present in memory, 1 = Present in memory
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UINT64 ReadWrite:1; // 0 = Read-Only, 1= Read/Write
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UINT64 UserSupervisor:1; // 0 = Supervisor, 1=User
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UINT64 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching
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UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached
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UINT64 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU)
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UINT64 Dirty:1; // 0 = Not Dirty, 1 = written by processor on access to page
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UINT64 MustBe1:1; // Must be 1
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UINT64 Global:1; // 0 = Not global page, 1 = global page TLB not cleared on CR3 write
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UINT64 Available:3; // Available for use by system software
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UINT64 PAT:1; //
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UINT64 MustBeZero:17; // Must be zero;
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UINT64 PageTableBaseAddress:22; // Page Table Base Address
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UINT64 AvabilableHigh:11; // Available for use by system software
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UINT64 Nx:1; // 0 = Execute Code, 1 = No Code Execution
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} Bits;
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UINT64 Uint64;
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} PAGE_TABLE_1G_ENTRY;
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#pragma pack()
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@@ -89,6 +89,30 @@ typedef union {
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UINT64 Uint64;
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} PAGE_TABLE_ENTRY;
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//
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// Page Table Entry 1GB
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//
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typedef union {
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struct {
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UINT64 Present:1; // 0 = Not present in memory, 1 = Present in memory
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UINT64 ReadWrite:1; // 0 = Read-Only, 1= Read/Write
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UINT64 UserSupervisor:1; // 0 = Supervisor, 1=User
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UINT64 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching
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UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached
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UINT64 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU)
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UINT64 Dirty:1; // 0 = Not Dirty, 1 = written by processor on access to page
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UINT64 MustBe1:1; // Must be 1
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UINT64 Global:1; // 0 = Not global page, 1 = global page TLB not cleared on CR3 write
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UINT64 Available:3; // Available for use by system software
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UINT64 PAT:1; //
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UINT64 MustBeZero:17; // Must be zero;
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UINT64 PageTableBaseAddress:22; // Page Table Base Address
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UINT64 AvabilableHigh:11; // Available for use by system software
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UINT64 Nx:1; // 0 = Execute Code, 1 = No Code Execution
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} Bits;
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UINT64 Uint64;
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} PAGE_TABLE_1G_ENTRY;
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#pragma pack()
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typedef
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@@ -53,20 +53,38 @@ CalculatePageTableSize (
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VOID
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)
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{
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UINT32 RegEax;
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UINT32 RegEdx;
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UINTN TotalPagesNum;
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UINT8 PhysicalAddressBits;
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VOID *Hob;
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UINT32 NumberOfPml4EntriesNeeded;
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UINT32 NumberOfPdpEntriesNeeded;
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BOOLEAN Page1GSupport;
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Page1GSupport = FALSE;
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AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);
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if (RegEax >= 0x80000001) {
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AsmCpuid (0x80000001, NULL, NULL, NULL, &RegEdx);
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if ((RegEdx & BIT26) != 0) {
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Page1GSupport = TRUE;
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}
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}
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//
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// Get physical address bits supported from CPU HOB.
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// Get physical address bits supported.
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//
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PhysicalAddressBits = 36;
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Hob = GetFirstHob (EFI_HOB_TYPE_CPU);
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if (Hob != NULL) {
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PhysicalAddressBits = ((EFI_HOB_CPU *) Hob)->SizeOfMemorySpace;
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} else {
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AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);
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if (RegEax >= 0x80000008) {
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AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL);
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PhysicalAddressBits = (UINT8) RegEax;
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} else {
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PhysicalAddressBits = 36;
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}
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}
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//
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@@ -82,13 +100,17 @@ CalculatePageTableSize (
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//
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if (PhysicalAddressBits <= 39 ) {
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NumberOfPml4EntriesNeeded = 1;
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NumberOfPdpEntriesNeeded = 1 << (PhysicalAddressBits - 30);
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NumberOfPdpEntriesNeeded = (UINT32)LShiftU64 (1, (PhysicalAddressBits - 30));
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} else {
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NumberOfPml4EntriesNeeded = 1 << (PhysicalAddressBits - 39);
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NumberOfPml4EntriesNeeded = (UINT32)LShiftU64 (1, (PhysicalAddressBits - 39));
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NumberOfPdpEntriesNeeded = 512;
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}
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TotalPagesNum = (NumberOfPdpEntriesNeeded + 1) * NumberOfPml4EntriesNeeded + 1;
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if (!Page1GSupport) {
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TotalPagesNum = (NumberOfPdpEntriesNeeded + 1) * NumberOfPml4EntriesNeeded + 1;
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} else {
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TotalPagesNum = NumberOfPml4EntriesNeeded + 1;
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}
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return EFI_PAGES_TO_SIZE (TotalPagesNum);
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}
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@@ -118,15 +140,32 @@ CreateIdentityMappingPageTables (
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PAGE_TABLE_ENTRY *PageDirectoryEntry;
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UINTN BigPageAddress;
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VOID *Hob;
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BOOLEAN Page1GSupport;
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PAGE_TABLE_1G_ENTRY *PageDirectory1GEntry;
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Page1GSupport = FALSE;
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AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);
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if (RegEax >= 0x80000001) {
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AsmCpuid (0x80000001, NULL, NULL, NULL, &RegEdx);
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if ((RegEdx & BIT26) != 0) {
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Page1GSupport = TRUE;
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}
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}
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//
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// Get physical address bits supported from CPU HOB.
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// Get physical address bits supported.
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//
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PhysicalAddressBits = 36;
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Hob = GetFirstHob (EFI_HOB_TYPE_CPU);
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if (Hob != NULL) {
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PhysicalAddressBits = ((EFI_HOB_CPU *) Hob)->SizeOfMemorySpace;
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} else {
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AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);
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if (RegEax >= 0x80000008) {
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AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL);
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PhysicalAddressBits = (UINT8) RegEax;
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} else {
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PhysicalAddressBits = 36;
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}
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}
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//
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@@ -142,9 +181,9 @@ CreateIdentityMappingPageTables (
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//
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if (PhysicalAddressBits <= 39 ) {
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NumberOfPml4EntriesNeeded = 1;
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NumberOfPdpEntriesNeeded = 1 << (PhysicalAddressBits - 30);
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NumberOfPdpEntriesNeeded = (UINT32)LShiftU64 (1, (PhysicalAddressBits - 30));
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} else {
|
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NumberOfPml4EntriesNeeded = 1 << (PhysicalAddressBits - 39);
|
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NumberOfPml4EntriesNeeded = (UINT32)LShiftU64 (1, (PhysicalAddressBits - 39));
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NumberOfPdpEntriesNeeded = 512;
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}
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@@ -157,7 +196,7 @@ CreateIdentityMappingPageTables (
|
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// By architecture only one PageMapLevel4 exists - so lets allocate storage for it.
|
||||
//
|
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PageMap = (VOID *) BigPageAddress;
|
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BigPageAddress += EFI_PAGE_SIZE;
|
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BigPageAddress += SIZE_4KB;
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PageMapLevel4Entry = PageMap;
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PageAddress = 0;
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@@ -167,7 +206,7 @@ CreateIdentityMappingPageTables (
|
||||
// So lets allocate space for them and fill them in in the IndexOfPdpEntries loop.
|
||||
//
|
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PageDirectoryPointerEntry = (VOID *) BigPageAddress;
|
||||
BigPageAddress += EFI_PAGE_SIZE;
|
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BigPageAddress += SIZE_4KB;
|
||||
|
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//
|
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// Make a PML4 Entry
|
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@@ -176,44 +215,63 @@ CreateIdentityMappingPageTables (
|
||||
PageMapLevel4Entry->Bits.ReadWrite = 1;
|
||||
PageMapLevel4Entry->Bits.Present = 1;
|
||||
|
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for (IndexOfPdpEntries = 0; IndexOfPdpEntries < NumberOfPdpEntriesNeeded; IndexOfPdpEntries++, PageDirectoryPointerEntry++) {
|
||||
//
|
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// Each Directory Pointer entries points to a page of Page Directory entires.
|
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// So allocate space for them and fill them in in the IndexOfPageDirectoryEntries loop.
|
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//
|
||||
PageDirectoryEntry = (VOID *) BigPageAddress;
|
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BigPageAddress += EFI_PAGE_SIZE;
|
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|
||||
//
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// Fill in a Page Directory Pointer Entries
|
||||
//
|
||||
PageDirectoryPointerEntry->Uint64 = (UINT64)(UINTN)PageDirectoryEntry;
|
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PageDirectoryPointerEntry->Bits.ReadWrite = 1;
|
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PageDirectoryPointerEntry->Bits.Present = 1;
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|
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for (IndexOfPageDirectoryEntries = 0; IndexOfPageDirectoryEntries < 512; IndexOfPageDirectoryEntries++, PageDirectoryEntry++, PageAddress += 0x200000) {
|
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if (Page1GSupport) {
|
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PageDirectory1GEntry = (VOID *) BigPageAddress;
|
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BigPageAddress += SIZE_4KB;
|
||||
|
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for (IndexOfPageDirectoryEntries = 0; IndexOfPageDirectoryEntries < 512; IndexOfPageDirectoryEntries++, PageDirectory1GEntry++, PageAddress += SIZE_1GB) {
|
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//
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// Fill in the Page Directory entries
|
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//
|
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PageDirectoryEntry->Uint64 = (UINT64)PageAddress;
|
||||
PageDirectoryEntry->Bits.ReadWrite = 1;
|
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PageDirectoryEntry->Bits.Present = 1;
|
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PageDirectoryEntry->Bits.MustBe1 = 1;
|
||||
PageDirectory1GEntry->Uint64 = (UINT64)PageAddress;
|
||||
PageDirectory1GEntry->Bits.ReadWrite = 1;
|
||||
PageDirectory1GEntry->Bits.Present = 1;
|
||||
PageDirectory1GEntry->Bits.MustBe1 = 1;
|
||||
}
|
||||
} else {
|
||||
for (IndexOfPdpEntries = 0; IndexOfPdpEntries < NumberOfPdpEntriesNeeded; IndexOfPdpEntries++, PageDirectoryPointerEntry++) {
|
||||
//
|
||||
// Each Directory Pointer entries points to a page of Page Directory entires.
|
||||
// So allocate space for them and fill them in in the IndexOfPageDirectoryEntries loop.
|
||||
//
|
||||
PageDirectoryEntry = (VOID *) BigPageAddress;
|
||||
BigPageAddress += SIZE_4KB;
|
||||
|
||||
//
|
||||
// Fill in a Page Directory Pointer Entries
|
||||
//
|
||||
PageDirectoryPointerEntry->Uint64 = (UINT64)(UINTN)PageDirectoryEntry;
|
||||
PageDirectoryPointerEntry->Bits.ReadWrite = 1;
|
||||
PageDirectoryPointerEntry->Bits.Present = 1;
|
||||
|
||||
for (IndexOfPageDirectoryEntries = 0; IndexOfPageDirectoryEntries < 512; IndexOfPageDirectoryEntries++, PageDirectoryEntry++, PageAddress += SIZE_2MB) {
|
||||
//
|
||||
// Fill in the Page Directory entries
|
||||
//
|
||||
PageDirectoryEntry->Uint64 = (UINT64)PageAddress;
|
||||
PageDirectoryEntry->Bits.ReadWrite = 1;
|
||||
PageDirectoryEntry->Bits.Present = 1;
|
||||
PageDirectoryEntry->Bits.MustBe1 = 1;
|
||||
}
|
||||
}
|
||||
|
||||
for (; IndexOfPdpEntries < 512; IndexOfPdpEntries++, PageDirectoryPointerEntry++) {
|
||||
ZeroMem (
|
||||
PageDirectoryPointerEntry,
|
||||
sizeof(PAGE_MAP_AND_DIRECTORY_POINTER)
|
||||
);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
//
|
||||
// For the PML4 entries we are not using fill in a null entry.
|
||||
// For now we just copy the first entry.
|
||||
//
|
||||
for (; IndexOfPml4Entries < 512; IndexOfPml4Entries++, PageMapLevel4Entry++) {
|
||||
CopyMem (
|
||||
PageMapLevel4Entry,
|
||||
PageMap,
|
||||
sizeof (PAGE_MAP_AND_DIRECTORY_POINTER)
|
||||
);
|
||||
ZeroMem (
|
||||
PageMapLevel4Entry,
|
||||
sizeof (PAGE_MAP_AND_DIRECTORY_POINTER)
|
||||
);
|
||||
}
|
||||
}
|
||||
|
||||
|
Reference in New Issue
Block a user