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BaseTools/GenFw: Add support for LOONGARCH64 relax relocation

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Correct relax id from 99 to 100 and added relocation support up to 109

fix gcc14 adds new relocation, and the generated relocation
causes the build and compilation to fail.
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4559

Cc: Rebecca Cran <rebecca@bsdio.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Bob Feng <bob.c.feng@intel.com>
Cc: Yuwei Chen <yuwei.chen@intel.com>
Cc: Chao Li <lichao@loongson.cn>
Signed-off-by: Dongyan Qian <qiandongyan@loongson.cn>
Reviewed-by: Chao Li <lichao@loongson.cn>
This commit is contained in:
Dongyan Qian
2023-09-22 15:12:02 +08:00
committed by mergify[bot]
parent d11f0ea045
commit c70d914428
2 changed files with 32 additions and 1 deletions
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20
BaseTools/Source/C/GenFw/Elf64Convert.c
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@@ -1778,7 +1778,17 @@ WriteSections64 (
case R_LARCH_TLS_LD64_HI20:
case R_LARCH_TLS_GD_PC_HI20:
case R_LARCH_TLS_GD64_HI20:
case R_LARCH_32_PCREL:
case R_LARCH_RELAX:
case R_LARCH_DELETE:
case R_LARCH_ALIGN:
case R_LARCH_PCREL20_S2:
case R_LARCH_CFA:
case R_LARCH_ADD6:
case R_LARCH_SUB6:
case R_LARCH_ADD_ULEB128:
case R_LARCH_SUB_ULEB128:
case R_LARCH_64_PCREL:
//
// These types are not used or do not require fixup.
//
@@ -2185,7 +2195,17 @@ WriteRelocations64 (
case R_LARCH_TLS_LD64_HI20:
case R_LARCH_TLS_GD_PC_HI20:
case R_LARCH_TLS_GD64_HI20:
case R_LARCH_32_PCREL:
case R_LARCH_RELAX:
case R_LARCH_DELETE:
case R_LARCH_ALIGN:
case R_LARCH_PCREL20_S2:
case R_LARCH_CFA:
case R_LARCH_ADD6:
case R_LARCH_SUB6:
case R_LARCH_ADD_ULEB128:
case R_LARCH_SUB_ULEB128:
case R_LARCH_64_PCREL:
//
// These types are not used or do not require fixup in PE format files.
//