ArmPkg/ArmLib: move cache maintenance sync barriers out of loop

There is no need to issue a full data synchronization barrier and an
instruction synchronization barrier after each and every set/way or
MVA cache maintenance operation. For the set/way case, we can simply
remove them, since the set/way outer loop already issues the required
barriers after completing its traversal over all the cache levels.

For the MVA case, move the data synchronization barrier out of the
loop, and add the instruction synchronization barrier to the I-cache
invalidation by MVA routine.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18755 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
Ard Biesheuvel
2015-11-09 13:27:15 +00:00
committed by abiesheuvel
parent fbf658ebc8
commit c722289324
4 changed files with 1 additions and 36 deletions

View File

@@ -35,6 +35,7 @@ CacheRangeOperation (
LineOperation(AlignedAddress);
AlignedAddress += ArmCacheLineLength;
}
ArmDataSynchronizationBarrier ();
}
VOID