MdePkg/PCI: Add missing PCI/PCIE definitions

The definitions are required by certain platform initialization
code.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Reviewed-by: Amy Chan <amy.chan@intel.com>
This commit is contained in:
Ruiyu Ni
2016-05-27 21:43:45 +08:00
parent dd85dd0731
commit cbedba8698
4 changed files with 503 additions and 21 deletions

View File

@@ -1,7 +1,7 @@
/** @file
Support for the latest PCI standard.
Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
(C) Copyright 2016 Hewlett Packard Enterprise Development LP<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
@@ -16,6 +16,337 @@
#ifndef _PCIEXPRESS21_H_
#define _PCIEXPRESS21_H_
#include <IndustryStandard/Pci30.h>
#pragma pack(1)
///
/// PCI Express Capability Structure
///
typedef union {
struct {
UINT16 Version : 4;
UINT16 DevicePortType : 4;
UINT16 SlotImplemented : 1;
UINT16 InterruptMessageNumber : 5;
UINT16 Undefined : 1;
UINT16 Reserved : 1;
} Bits;
UINT16 Uint16;
} PCI_REG_PCIE_CAPABILITY;
#define PCIE_DEVICE_PORT_TYPE_PCIE_ENDPOINT 0
#define PCIE_DEVICE_PORT_TYPE_LEGACY_PCIE_ENDPOINT 1
#define PCIE_DEVICE_PORT_TYPE_ROOT_PORT 4
#define PCIE_DEVICE_PORT_TYPE_UPSTREAM_PORT 5
#define PCIE_DEVICE_PORT_TYPE_DOWNSTREAM_PORT 6
#define PCIE_DEVICE_PORT_TYPE_PCIE_TO_PCI_BRIDGE 7
#define PCIE_DEVICE_PORT_TYPE_PCI_TO_PCIE_BRIDGE 8
#define PCIE_DEVICE_PORT_TYPE_ROOT_COMPLEX_INTEGRATED_ENDPOINT 9
#define PCIE_DEVICE_PORT_TYPE_ROOT_COMPLEX_EVENT_COLLECTOR 10
typedef union {
struct {
UINT32 MaxPayloadSize : 3;
UINT32 PhantomFunctions : 2;
UINT32 ExtendedTagField : 1;
UINT32 EndpointL0sAcceptableLatency : 3;
UINT32 EndpointL1AcceptableLatency : 3;
UINT32 Undefined : 3;
UINT32 RoleBasedErrorReporting : 1;
UINT32 Reserved : 2;
UINT32 CapturedSlotPowerLimitValue : 8;
UINT32 CapturedSlotPowerLimitScale : 2;
UINT32 FunctionLevelReset : 1;
UINT32 Reserved2 : 3;
} Bits;
UINT32 Uint32;
} PCI_REG_PCIE_DEVICE_CAPABILITY;
typedef union {
struct {
UINT16 CorrectableError : 1;
UINT16 NonFatalError : 1;
UINT16 FatalError : 1;
UINT16 UnsupportedRequest : 1;
UINT16 RelaxedOrdering : 1;
UINT16 MaxPayloadSize : 3;
UINT16 ExtendedTagField : 1;
UINT16 PhantomFunctions : 1;
UINT16 AuxPower : 1;
UINT16 NoSnoop : 1;
UINT16 MaxReadRequestSize : 3;
UINT16 BridgeConfigurationRetryOrFunctionLevelReset : 1;
} Bits;
UINT16 Uint16;
} PCI_REG_PCIE_DEVICE_CONTROL;
typedef union {
struct {
UINT16 CorrectableError : 1;
UINT16 NonFatalError : 1;
UINT16 FatalError : 1;
UINT16 UnsupportedRequest : 1;
UINT16 AuxPower : 1;
UINT16 TransactionsPending : 1;
UINT16 Reserved : 10;
} Bits;
UINT16 Uint16;
} PCI_REG_PCIE_DEVICE_STATUS;
typedef union {
struct {
UINT32 MaxLinkSpeed : 4;
UINT32 MaxLinkWidth : 6;
UINT32 Aspm : 2;
UINT32 L0sExitLatency : 3;
UINT32 L1ExitLatency : 3;
UINT32 ClockPowerManagement : 1;
UINT32 SurpriseDownError : 1;
UINT32 DataLinkLayerLinkActive : 1;
UINT32 LinkBandwidthNotification : 1;
UINT32 AspmOptionalityCompliance : 1;
UINT32 Reserved : 1;
UINT32 PortNumber : 8;
} Bits;
UINT32 Uint32;
} PCI_REG_PCIE_LINK_CAPABILITY;
#define PCIE_LINK_ASPM_L0S BIT0
#define PCIE_LINK_ASPM_L1 BIT1
typedef union {
struct {
UINT16 AspmControl : 2;
UINT16 Reserved : 1;
UINT16 ReadCompletionBoundary : 1;
UINT16 LinkDisable : 1;
UINT16 RetrainLink : 1;
UINT16 CommonClockConfiguration : 1;
UINT16 ExtendedSynch : 1;
UINT16 ClockPowerManagement : 1;
UINT16 HardwareAutonomousWidthDisable : 1;
UINT16 LinkBandwidthManagementInterrupt : 1;
UINT16 LinkAutonomousBandwidthInterrupt : 1;
} Bits;
UINT16 Uint16;
} PCI_REG_PCIE_LINK_CONTROL;
typedef union {
struct {
UINT16 CurrentLinkSpeed : 4;
UINT16 NegotiatedLinkWidth : 6;
UINT16 Undefined : 1;
UINT16 LinkTraining : 1;
UINT16 SlotClockConfiguration : 1;
UINT16 DataLinkLayerLinkActive : 1;
UINT16 LinkBandwidthManagement : 1;
UINT16 LinkAutonomousBandwidth : 1;
} Bits;
UINT16 Uint16;
} PCI_REG_PCIE_LINK_STATUS;
typedef union {
struct {
UINT32 AttentionButton : 1;
UINT32 PowerController : 1;
UINT32 MrlSensor : 1;
UINT32 AttentionIndicator : 1;
UINT32 PowerIndicator : 1;
UINT32 HotPlugSurprise : 1;
UINT32 HotPlugCapable : 1;
UINT32 SlotPowerLimitValue : 8;
UINT32 SlotPowerLimitScale : 2;
UINT32 ElectromechanicalInterlock : 1;
UINT32 NoCommandCompleted : 1;
UINT32 PhysicalSlotNumber : 13;
} Bits;
UINT32 Uint32;
} PCI_REG_PCIE_SLOT_CAPABILITY;
typedef union {
struct {
UINT32 AttentionButtonPressed : 1;
UINT32 PowerFaultDetected : 1;
UINT32 MrlSensorChanged : 1;
UINT32 PresenceDetectChanged : 1;
UINT32 CommandCompletedInterrupt : 1;
UINT32 HotPlugInterrupt : 1;
UINT32 AttentionIndicator : 2;
UINT32 PowerIndicator : 2;
UINT32 PowerController : 1;
UINT32 ElectromechanicalInterlock : 1;
UINT32 DataLinkLayerStateChanged : 1;
UINT32 Reserved : 3;
} Bits;
UINT16 Uint16;
} PCI_REG_PCIE_SLOT_CONTROL;
typedef union {
struct {
UINT16 AttentionButtonPressed : 1;
UINT16 PowerFaultDetected : 1;
UINT16 MrlSensorChanged : 1;
UINT16 PresenceDetectChanged : 1;
UINT16 CommandCompleted : 1;
UINT16 MrlSensor : 1;
UINT16 PresenceDetect : 1;
UINT16 ElectromechanicalInterlock : 1;
UINT16 DataLinkLayerStateChanged : 1;
UINT16 Reserved : 7;
} Bits;
UINT16 Uint16;
} PCI_REG_PCIE_SLOT_STATUS;
typedef union {
struct {
UINT16 SystemErrorOnCorrectableError : 1;
UINT16 SystemErrorOnNonFatalError : 1;
UINT16 SystemErrorOnFatalError : 1;
UINT16 PmeInterrupt : 1;
UINT16 CrsSoftwareVisibility : 1;
UINT16 Reserved : 11;
} Bits;
UINT16 Uint16;
} PCI_REG_PCIE_ROOT_CONTROL;
typedef union {
struct {
UINT16 CrsSoftwareVisibility : 1;
UINT16 Reserved : 15;
} Bits;
UINT16 Uint16;
} PCI_REG_PCIE_ROOT_CAPABILITY;
typedef union {
struct {
UINT32 PmeRequesterId : 16;
UINT32 PmeStatus : 1;
UINT32 PmePending : 1;
UINT32 Reserved : 14;
} Bits;
UINT32 Uint32;
} PCI_REG_PCIE_ROOT_STATUS;
typedef union {
struct {
UINT32 CompletionTimeoutRanges : 4;
UINT32 CompletionTimeoutDisable : 1;
UINT32 AriForwarding : 1;
UINT32 AtomicOpRouting : 1;
UINT32 AtomicOp32Completer : 1;
UINT32 AtomicOp64Completer : 1;
UINT32 Cas128Completer : 1;
UINT32 NoRoEnabledPrPrPassing : 1;
UINT32 LtrMechanism : 1;
UINT32 TphCompleter : 2;
UINT32 Reserved : 4;
UINT32 Obff : 2;
UINT32 ExtendedFmtField : 1;
UINT32 EndEndTlpPrefix : 1;
UINT32 MaxEndEndTlpPrefixes : 2;
UINT32 Reserved2 : 8;
} Bits;
UINT32 Uint32;
} PCI_REG_PCIE_DEVICE_CAPABILITY2;
#define PCIE_DEVICE_CAPABILITY_OBFF_MESSAGE BIT0
#define PCIE_DEVICE_CAPABILITY_OBFF_WAKE BIT1
typedef union {
struct {
UINT16 CompletionTimeoutValue : 4;
UINT16 CompletionTimeoutDisable : 1;
UINT16 AriForwarding : 1;
UINT16 AtomicOpRequester : 1;
UINT16 AtomicOpEgressBlocking : 1;
UINT16 IdoRequest : 1;
UINT16 IdoCompletion : 1;
UINT16 LtrMechanism : 2;
UINT16 Reserved : 2;
UINT16 Obff : 2;
UINT16 EndEndTlpPrefixBlocking : 1;
} Bits;
UINT16 Uint16;
} PCI_REG_PCIE_DEVICE_CONTROL2;
#define PCIE_COMPLETION_TIMEOUT_50US_50MS 0
#define PCIE_COMPLETION_TIMEOUT_50US_100US 1
#define PCIE_COMPLETION_TIMEOUT_1MS_10MS 2
#define PCIE_COMPLETION_TIMEOUT_16MS_55MS 5
#define PCIE_COMPLETION_TIMEOUT_65MS_210MS 6
#define PCIE_COMPLETION_TIMEOUT_260MS_900MS 9
#define PCIE_COMPLETION_TIMEOUT_1S_3_5S 10
#define PCIE_COMPLETION_TIMEOUT_4S_13S 13
#define PCIE_COMPLETION_TIMEOUT_17S_64S 14
#define PCIE_DEVICE_CONTROL_OBFF_DISABLED 0
#define PCIE_DEVICE_CONTROL_OBFF_MESSAGE_A 1
#define PCIE_DEVICE_CONTROL_OBFF_MESSAGE_B 2
#define PCIE_DEVICE_CONTROL_OBFF_WAKE 3
typedef union {
struct {
UINT32 Reserved : 1;
UINT32 LinkSpeedsVector : 7;
UINT32 Crosslink : 1;
UINT32 Reserved2 : 23;
} Bits;
UINT32 Uint32;
} PCI_REG_PCIE_LINK_CAPABILITY2;
typedef union {
struct {
UINT16 TargetLinkSpeed : 4;
UINT16 EnterCompliance : 1;
UINT16 HardwareAutonomousSpeedDisable : 1;
UINT16 SelectableDeemphasis : 1;
UINT16 TransmitMargin : 3;
UINT16 EnterModifiedCompliance : 1;
UINT16 ComplianceSos : 1;
UINT16 CompliancePresetDeemphasis : 4;
} Bits;
UINT16 Uint16;
} PCI_REG_PCIE_LINK_CONTROL2;
typedef union {
struct {
UINT16 CurrentDeemphasisLevel : 1;
UINT16 EqualizationComplete : 1;
UINT16 EqualizationPhase1Successful : 1;
UINT16 EqualizationPhase2Successful : 1;
UINT16 EqualizationPhase3Successful : 1;
UINT16 LinkEqualizationRequest : 1;
UINT16 Reserved : 10;
} Bits;
UINT16 Uint16;
} PCI_REG_PCIE_LINK_STATUS2;
typedef struct {
EFI_PCI_CAPABILITY_HDR Hdr;
PCI_REG_PCIE_CAPABILITY Capability;
PCI_REG_PCIE_DEVICE_CAPABILITY DeviceCapability;
PCI_REG_PCIE_DEVICE_CONTROL DeviceControl;
PCI_REG_PCIE_DEVICE_STATUS DeviceStatus;
PCI_REG_PCIE_LINK_CAPABILITY LinkCapability;
PCI_REG_PCIE_LINK_CONTROL LinkControl;
PCI_REG_PCIE_LINK_STATUS LinkStatus;
PCI_REG_PCIE_SLOT_CAPABILITY SlotCapability;
PCI_REG_PCIE_SLOT_CONTROL SlotControl;
PCI_REG_PCIE_SLOT_STATUS SlotStatus;
PCI_REG_PCIE_ROOT_CONTROL RootControl;
PCI_REG_PCIE_ROOT_CAPABILITY RootCapability;
PCI_REG_PCIE_ROOT_STATUS RootStatus;
PCI_REG_PCIE_DEVICE_CAPABILITY2 DeviceCapability2;
PCI_REG_PCIE_DEVICE_CONTROL2 DeviceControl2;
UINT16 DeviceStatus2;
PCI_REG_PCIE_LINK_CAPABILITY2 LinkCapability2;
PCI_REG_PCIE_LINK_CONTROL2 LinkControl2;
PCI_REG_PCIE_LINK_STATUS2 LinkStatus2;
UINT32 SlotCapability2;
UINT16 SlotControl2;
UINT16 SlotStatus2;
} PCI_CAPABILITY_PCIEXP;
#define EFI_PCIE_CAPABILITY_BASE_OFFSET 0x100
#define EFI_PCIE_CAPABILITY_ID_SRIOV_CONTROL_ARI_HIERARCHY 0x10
#define EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_OFFSET 0x24
@@ -83,11 +414,37 @@ typedef struct {
#define PCI_EXPRESS_EXTENDED_CAPABILITY_ADVANCED_ERROR_REPORTING_VER1 0x1
#define PCI_EXPRESS_EXTENDED_CAPABILITY_ADVANCED_ERROR_REPORTING_VER2 0x2
typedef union {
struct {
UINT32 Undefined : 1;
UINT32 Reserved : 3;
UINT32 DataLinkProtocolError : 1;
UINT32 SurpriseDownError : 1;
UINT32 Reserved2 : 6;
UINT32 PoisonedTlp : 1;
UINT32 FlowControlProtocolError : 1;
UINT32 CompletionTimeout : 1;
UINT32 CompleterAbort : 1;
UINT32 UnexpectedCompletion : 1;
UINT32 ReceiverOverflow : 1;
UINT32 MalformedTlp : 1;
UINT32 EcrcError : 1;
UINT32 UnsupportedRequestError : 1;
UINT32 AcsVoilation : 1;
UINT32 UncorrectableInternalError : 1;
UINT32 McBlockedTlp : 1;
UINT32 AtomicOpEgressBlocked : 1;
UINT32 TlpPrefixBlockedError : 1;
UINT32 Reserved3 : 6;
} Bits;
UINT32 Uint32;
} PCI_EXPRESS_REG_UNCORRECTABLE_ERROR;
typedef struct {
PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
UINT32 UncorrectableErrorStatus;
UINT32 UncorrectableErrorMask;
UINT32 UncorrectableErrorSeverity;
PCI_EXPRESS_REG_UNCORRECTABLE_ERROR UncorrectableErrorStatus;
PCI_EXPRESS_REG_UNCORRECTABLE_ERROR UncorrectableErrorMask;
PCI_EXPRESS_REG_UNCORRECTABLE_ERROR UncorrectableErrorSeverity;
UINT32 CorrectableErrorStatus;
UINT32 CorrectableErrorMask;
UINT32 AdvancedErrorCapabilitiesAndControl;
@@ -289,4 +646,6 @@ typedef struct {
#define GET_TPH_TABLE_SIZE(x) ((x->TphRequesterCapability & 0x7FF0000)>>16) * sizeof(UINT16)
#pragma pack()
#endif