sravan/system76-edk2
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

MdePkg/PCI: Add missing PCI/PCIE definitions

Browse Source 
The definitions are required by certain platform initialization
code.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Reviewed-by: Amy Chan <amy.chan@intel.com>
This commit is contained in:
Ruiyu Ni
2016-05-27 21:43:45 +08:00
parent dd85dd0731
commit cbedba8698
4 changed files with 503 additions and 21 deletions
Download Patch File Download Diff File Expand all files Collapse all files

33
MdePkg/Include/IndustryStandard/PciExpress30.h
View File

@@ -3,7 +3,7 @@
This header file may not define all structures. Please extend as required.
Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -17,16 +17,41 @@
#ifndef _PCIEXPRESS30_H_
#define _PCIEXPRESS30_H_
#include "PciExpress21.h"
#include <IndustryStandard/PciExpress21.h>
#pragma pack(1)
#define PCI_EXPRESS_EXTENDED_CAPABILITY_SECONDARY_PCIE_ID 0x0019
#define PCI_EXPRESS_EXTENDED_CAPABILITY_SECONDARY_PCIE_VER1 0x1
typedef union {
struct {
UINT32 PerformEqualization : 1;
UINT32 LinkEqualizationRequestInterruptEnable : 1;
UINT32 Reserved : 30;
} Bits;
UINT32 Uint32;
} PCI_EXPRESS_REG_LINK_CONTROL3;
typedef union {
struct {
UINT16 DownstreamPortTransmitterPreset : 4;
UINT16 DownstreamPortReceiverPresetHint : 3;
UINT16 Reserved : 1;
UINT16 UpstreamPortTransmitterPreset : 4;
UINT16 UpstreamPortReceiverPresetHint : 3;
UINT16 Reserved2 : 1;
} Bits;
UINT16 Uint16;
} PCI_EXPRESS_REG_LANE_EQUALIZATION_CONTROL;
typedef struct {
PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
UINT32 LinkControl3;
PCI_EXPRESS_REG_LINK_CONTROL3 LinkControl3;
UINT32 LaneErrorStatus;
UINT16 EqualizationControl[2];
PCI_EXPRESS_REG_LANE_EQUALIZATION_CONTROL EqualizationControl[2];
} PCI_EXPRESS_EXTENDED_CAPABILITIES_SECONDARY_PCIE;
#pragma pack()
#endif