MdeModulePkg/AtaAtapiPassThru: Check IS to check for command completion

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3024

AHCI driver used to poll D2H register type to determine whether the FIS
has been received. This caused a problem of long timeouts when the link
got a CRC error and the FIS never arrives. To fix this this change
switches AHCI driver to poll the IS register which will signal both the
reception of FIS and the occurrence of error.

Signed-off-by: Mateusz Albecki <mateusz.albecki@intel.com>
Reviewed-by: Hao A Wu <hao.a.wu@intel.com>

Cc: Ray Ni <ray.ni@intel.com>
Cc: Hao A Wu <hao.a.wu@intel.com>
This commit is contained in:
Albecki, Mateusz
2020-11-05 20:48:44 +08:00
committed by mergify[bot]
parent 36c50bd5d5
commit cc28ab7a1d
2 changed files with 132 additions and 171 deletions

View File

@ -1,7 +1,7 @@
/** @file
Header file for AHCI mode of ATA host controller.
Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2010 - 2020, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@ -96,7 +96,7 @@ typedef union {
#define EFI_AHCI_PORT_IS 0x0010
#define EFI_AHCI_PORT_IS_DHRS BIT0
#define EFI_AHCI_PORT_IS_PSS BIT1
#define EFI_AHCI_PORT_IS_SSS BIT2
#define EFI_AHCI_PORT_IS_DSS BIT2
#define EFI_AHCI_PORT_IS_SDBS BIT3
#define EFI_AHCI_PORT_IS_UFS BIT4
#define EFI_AHCI_PORT_IS_DPS BIT5
@ -113,6 +113,7 @@ typedef union {
#define EFI_AHCI_PORT_IS_CPDS BIT31
#define EFI_AHCI_PORT_IS_CLEAR 0xFFFFFFFF
#define EFI_AHCI_PORT_IS_FIS_CLEAR 0x0000000F
#define EFI_AHCI_PORT_IS_ERROR_MASK (EFI_AHCI_PORT_IS_INFS | EFI_AHCI_PORT_IS_IFS | EFI_AHCI_PORT_IS_HBDS | EFI_AHCI_PORT_IS_HBFS | EFI_AHCI_PORT_IS_TFES)
#define EFI_AHCI_PORT_IE 0x0014
#define EFI_AHCI_PORT_CMD 0x0018
@ -240,6 +241,12 @@ typedef struct {
UINT8 AhciCFisRsvd5[44];
} EFI_AHCI_COMMAND_FIS;
typedef enum {
SataFisD2H = 0,
SataFisPioSetup,
SataFisDmaSetup
} SATA_FIS_TYPE;
//
// ACMD: ATAPI command (12 or 16 bytes)
//