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ArmPlatformPkg/Sec: Remove SCR and CPTR initialization from SetupExceptionLevel3

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This is already taken care by Sec when PcdTrustzoneSupport = TRUE.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14580 6f19259b-4bc3-4df7-8a09-765794883524
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Olivier Martin
2013-08-21 12:05:44 +00:00
committed by oliviermartin
parent a639401d2f
commit cc93554486
2 changed files with 40 additions and 32 deletions
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14
ArmPlatformPkg/Sec/AArch64/Helper.S
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@@ -26,20 +26,6 @@ ASM_GLOBAL ASM_PFX(copy_cpsr_into_spsr)
ASM_GLOBAL ASM_PFX(set_non_secure_mode)
ASM_PFX(SetupExceptionLevel3):
mrs x0, scr_el3 // Read EL3 Secure Configuration Register
orr x0, x0, #1 // EL0 an EL1 cannot access secure memory
// Send all interrupts to their respective Exception levels for EL3
bic x0, x0, #(1 << 1) // IRQ
bic x0, x0, #(1 << 2) // FIQ
bic x0, x0, #(1 << 3) // Serror and Abort
orr x0, x0, #(1 << 8) // Enable HVC
orr x0, x0, #(1 << 10) // Make next level down 64Bit. This is EL2 in the case of the Model.
// We need a nice way to detect this.
msr scr_el3, x0 // Write back our settings
msr cptr_el3, xzr // Disable copro traps to EL3
// Check for the primary CPU to avoid a race on the distributor registers.
mrs x0, mpidr_el1
tst x0, #15