Fix doxygen comment for structure and macro
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@6096 6f19259b-4bc3-4df7-8a09-765794883524
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@@ -48,27 +48,27 @@ typedef enum {
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//
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// Complete PCI address generater
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//
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#define EFI_PCI_IO_PASS_THROUGH_BAR 0xff // Special BAR that passes a memory or I/O cycle through unchanged
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#define EFI_PCI_IO_ATTRIBUTE_MASK 0x077f // All the following I/O and Memory cycles
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#define EFI_PCI_IO_ATTRIBUTE_ISA_MOTHERBOARD_IO 0x0001 // I/O cycles 0x0000-0x00FF (10 bit decode)
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#define EFI_PCI_IO_ATTRIBUTE_ISA_IO 0x0002 // I/O cycles 0x0100-0x03FF or greater (10 bit decode)
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#define EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO 0x0004 // I/O cycles 0x3C6, 0x3C8, 0x3C9 (10 bit decode)
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#define EFI_PCI_IO_ATTRIBUTE_VGA_MEMORY 0x0008 // MEM cycles 0xA0000-0xBFFFF (24 bit decode)
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#define EFI_PCI_IO_ATTRIBUTE_VGA_IO 0x0010 // I/O cycles 0x3B0-0x3BB and 0x3C0-0x3DF (10 bit decode)
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#define EFI_PCI_IO_ATTRIBUTE_IDE_PRIMARY_IO 0x0020 // I/O cycles 0x1F0-0x1F7, 0x3F6, 0x3F7 (10 bit decode)
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#define EFI_PCI_IO_ATTRIBUTE_IDE_SECONDARY_IO 0x0040 // I/O cycles 0x170-0x177, 0x376, 0x377 (10 bit decode)
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#define EFI_PCI_IO_ATTRIBUTE_MEMORY_WRITE_COMBINE 0x0080 // Map a memory range so write are combined
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#define EFI_PCI_IO_ATTRIBUTE_IO 0x0100 // Enable the I/O decode bit in the PCI Config Header
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#define EFI_PCI_IO_ATTRIBUTE_MEMORY 0x0200 // Enable the Memory decode bit in the PCI Config Header
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#define EFI_PCI_IO_ATTRIBUTE_BUS_MASTER 0x0400 // Enable the DMA bit in the PCI Config Header
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#define EFI_PCI_IO_ATTRIBUTE_MEMORY_CACHED 0x0800 // Map a memory range so all r/w accesses are cached
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#define EFI_PCI_IO_ATTRIBUTE_MEMORY_DISABLE 0x1000 // Disable a memory range
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#define EFI_PCI_IO_ATTRIBUTE_EMBEDDED_DEVICE 0x2000 // Clear for an add-in PCI Device
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#define EFI_PCI_IO_ATTRIBUTE_EMBEDDED_ROM 0x4000 // Clear for a physical PCI Option ROM accessed through ROM BAR
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#define EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE 0x8000 // Clear for PCI controllers that can not genrate a DAC
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#define EFI_PCI_IO_ATTRIBUTE_ISA_IO_16 0x10000 // I/O cycles 0x0100-0x03FF or greater (16 bit decode)
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#define EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO_16 0x20000 // I/O cycles 0x3C6, 0x3C8, 0x3C9 (16 bit decode)
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#define EFI_PCI_IO_ATTRIBUTE_VGA_IO_16 0x30000 // I/O cycles 0x3B0-0x3BB and 0x3C0-0x3DF (16 bit decode)
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#define EFI_PCI_IO_PASS_THROUGH_BAR 0xff ///< Special BAR that passes a memory or I/O cycle through unchanged
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#define EFI_PCI_IO_ATTRIBUTE_MASK 0x077f ///< All the following I/O and Memory cycles
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#define EFI_PCI_IO_ATTRIBUTE_ISA_MOTHERBOARD_IO 0x0001 ///< I/O cycles 0x0000-0x00FF (10 bit decode)
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#define EFI_PCI_IO_ATTRIBUTE_ISA_IO 0x0002 ///< I/O cycles 0x0100-0x03FF or greater (10 bit decode)
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#define EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO 0x0004 ///< I/O cycles 0x3C6, 0x3C8, 0x3C9 (10 bit decode)
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#define EFI_PCI_IO_ATTRIBUTE_VGA_MEMORY 0x0008 ///< MEM cycles 0xA0000-0xBFFFF (24 bit decode)
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#define EFI_PCI_IO_ATTRIBUTE_VGA_IO 0x0010 ///< I/O cycles 0x3B0-0x3BB and 0x3C0-0x3DF (10 bit decode)
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#define EFI_PCI_IO_ATTRIBUTE_IDE_PRIMARY_IO 0x0020 ///< I/O cycles 0x1F0-0x1F7, 0x3F6, 0x3F7 (10 bit decode)
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#define EFI_PCI_IO_ATTRIBUTE_IDE_SECONDARY_IO 0x0040 ///< I/O cycles 0x170-0x177, 0x376, 0x377 (10 bit decode)
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#define EFI_PCI_IO_ATTRIBUTE_MEMORY_WRITE_COMBINE 0x0080 ///< Map a memory range so write are combined
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#define EFI_PCI_IO_ATTRIBUTE_IO 0x0100 ///< Enable the I/O decode bit in the PCI Config Header
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#define EFI_PCI_IO_ATTRIBUTE_MEMORY 0x0200 ///< Enable the Memory decode bit in the PCI Config Header
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#define EFI_PCI_IO_ATTRIBUTE_BUS_MASTER 0x0400 ///< Enable the DMA bit in the PCI Config Header
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#define EFI_PCI_IO_ATTRIBUTE_MEMORY_CACHED 0x0800 ///< Map a memory range so all r/w accesses are cached
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#define EFI_PCI_IO_ATTRIBUTE_MEMORY_DISABLE 0x1000 ///< Disable a memory range
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#define EFI_PCI_IO_ATTRIBUTE_EMBEDDED_DEVICE 0x2000 ///< Clear for an add-in PCI Device
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#define EFI_PCI_IO_ATTRIBUTE_EMBEDDED_ROM 0x4000 ///< Clear for a physical PCI Option ROM accessed through ROM BAR
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#define EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE 0x8000 ///< Clear for PCI controllers that can not genrate a DAC
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#define EFI_PCI_IO_ATTRIBUTE_ISA_IO_16 0x10000 ///< I/O cycles 0x0100-0x03FF or greater (16 bit decode)
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#define EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO_16 0x20000 ///< I/O cycles 0x3C6, 0x3C8, 0x3C9 (16 bit decode)
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#define EFI_PCI_IO_ATTRIBUTE_VGA_IO_16 0x30000 ///< I/O cycles 0x3B0-0x3BB and 0x3C0-0x3DF (16 bit decode)
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#define EFI_PCI_DEVICE_ENABLE (EFI_PCI_IO_ATTRIBUTE_IO | EFI_PCI_IO_ATTRIBUTE_MEMORY | EFI_PCI_IO_ATTRIBUTE_BUS_MASTER)
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#define EFI_VGA_DEVICE_ENABLE (EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO | EFI_PCI_IO_ATTRIBUTE_VGA_MEMORY | EFI_PCI_IO_ATTRIBUTE_VGA_IO | EFI_PCI_IO_ATTRIBUTE_IO)
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@@ -481,76 +481,6 @@ EFI_STATUS
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There is one EFI_PCI_IO_PROTOCOL instance for each PCI controller on a PCI bus.
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A device driver that wishes to manage a PCI controller in a system will have to
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retrieve the EFI_PCI_IO_PROTOCOL instance that is associated with the PCI controller.
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@param PollMem
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Polls an address in PCI memory space until an exit condition is met, or a timeout occurs.
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@param PollIo
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Polls an address in PCI I/O space until an exit condition is met, or a timeout occurs.
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@param Mem.Read
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Allows BAR relative reads to PCI memory space.
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@param Mem.Write
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Allows BAR relative writes to PCI memory space.
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@param Io.Read
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Allows BAR relative reads to PCI I/O space.
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@param Io.Write
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Allows BAR relative writes to PCI I/O space.
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@param Pci.Read
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Allows PCI controller relative reads to PCI configuration space.
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@param Pci.Write
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Allows PCI controller relative writes to PCI configuration space.
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@param CopyMem
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Allows one region of PCI memory space to be copied to another region of PCI memory space.
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@param Map
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Provides the PCI controller's specific address needed to access system memory for DMA.
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@param Unmap
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Releases any resources allocated by Map().
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@param AllocateBuffer
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Allocates pages that are suitable for a common buffer mapping.
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@param FreeBuffer
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Frees pages that were allocated with AllocateBuffer().
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@param Flush
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Flushes all PCI posted write transactions to system memory.
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@param GetLocation
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Retrieves this PCI controller's current PCI bus number, device number, and function number.
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@param Attributes
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Performs an operation on the attributes that this PCI controller supports.
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The operations include getting the set of supported attributes, retrieving
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the current attributes, setting the current
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attributes, enabling attributes, and disabling attributes.
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@param GetBarAttributes
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Gets the attributes that this PCI controller supports setting on a BAR using
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SetBarAttributes(), and retrieves the list of resource descriptors for a BAR.
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@param SetBarAttributes
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Sets the attributes for a range of a BAR on a PCI controller.
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@param RomSize
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The size, in bytes, of the ROM image.
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@param RomImage
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A pointer to the in memory copy of the ROM image. The PCI Bus Driver is responsible
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for allocating memory for the ROM image, and copying the contents of the ROM to memory.
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The contents of this buffer are either from the PCI option ROM that can be accessed
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through the ROM BAR of the PCI controller, or it is from a platform-specific location.
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The Attributes() function can be used to determine from which of these two sources
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the RomImage buffer was initialized.
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**/
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struct _EFI_PCI_IO_PROTOCOL {
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EFI_PCI_IO_PROTOCOL_POLL_IO_MEM PollMem;
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@@ -568,7 +498,20 @@ struct _EFI_PCI_IO_PROTOCOL {
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EFI_PCI_IO_PROTOCOL_ATTRIBUTES Attributes;
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EFI_PCI_IO_PROTOCOL_GET_BAR_ATTRIBUTES GetBarAttributes;
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EFI_PCI_IO_PROTOCOL_SET_BAR_ATTRIBUTES SetBarAttributes;
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///
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/// The size, in bytes, of the ROM image.
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///
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UINT64 RomSize;
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///
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/// A pointer to the in memory copy of the ROM image. The PCI Bus Driver is responsible
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/// for allocating memory for the ROM image, and copying the contents of the ROM to memory.
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/// The contents of this buffer are either from the PCI option ROM that can be accessed
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/// through the ROM BAR of the PCI controller, or it is from a platform-specific location.
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/// The Attributes() function can be used to determine from which of these two sources
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/// the RomImage buffer was initialized.
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///
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VOID *RomImage;
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};
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