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Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Liming Gao <liming.gao@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
This commit is contained in:
Liming Gao
2018-06-27 21:08:52 +08:00
parent ca79bab7af
commit d1102dba72
1010 changed files with 13588 additions and 13588 deletions
Download Patch File Download Diff File Expand all files Collapse all files

126
MdeModulePkg/Bus/Pci/EhciPei/EhcPeim.c
View File

@@ -2,8 +2,8 @@
PEIM to produce gPeiUsb2HostControllerPpiGuid based on gPeiUsbControllerPpiGuid
which is used to enable recovery function from USB Drivers.
Copyright (c) 2010 - 2017, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions
of the BSD License which accompanies this distribution. The
@@ -39,7 +39,7 @@ USB_PORT_STATE_MAP mUsbPortChangeMap[] = {
/**
Read Ehc Operation register.
@param Ehc The EHCI device.
@param Offset The operation register offset.
@@ -53,17 +53,17 @@ EhcReadOpReg (
)
{
UINT32 Data;
ASSERT (Ehc->CapLen != 0);
Data = MmioRead32 (Ehc->UsbHostControllerBaseAddress + Ehc->CapLen + Offset);
return Data;
}
/**
Write the data to the EHCI operation register.
@param Ehc The EHCI device.
@param Offset EHCI operation register offset.
@param Data The data to write.
@@ -85,7 +85,7 @@ EhcWriteOpReg (
/**
Set one bit of the operational register while keeping other bits.
@param Ehc The EHCI device.
@param Offset The offset of the operational register.
@param Bit The bit mask of the register to set.
@@ -107,7 +107,7 @@ EhcSetOpRegBit (
/**
Clear one bit of the operational register while keeping other bits.
@param Ehc The EHCI device.
@param Offset The offset of the operational register.
@param Bit The bit mask of the register to clear.
@@ -128,9 +128,9 @@ EhcClearOpRegBit (
}
/**
Wait the operation register's bit as specified by Bit
Wait the operation register's bit as specified by Bit
to become set (or clear).
@param Ehc The EHCI device.
@param Offset The offset of the operational register.
@param Bit The bit mask of the register to wait for.
@@ -165,7 +165,7 @@ EhcWaitOpRegBit (
/**
Read EHCI capability register.
@param Ehc The EHCI device.
@param Offset Capability register address.
@@ -179,16 +179,16 @@ EhcReadCapRegister (
)
{
UINT32 Data;
Data = MmioRead32(Ehc->UsbHostControllerBaseAddress + Offset);
return Data;
}
/**
Set door bell and wait it to be ACKed by host controller.
This function is used to synchronize with the hardware.
@param Ehc The EHCI device.
@param Timeout The time to wait before abort (in millisecond, ms).
@@ -223,9 +223,9 @@ EhcSetAndWaitDoorBell (
}
/**
Clear all the interrutp status bits, these bits
Clear all the interrutp status bits, these bits
are Write-Clean.
@param Ehc The EHCI device.
**/
@@ -238,9 +238,9 @@ EhcAckAllInterrupt (
}
/**
Enable the periodic schedule then wait EHC to
Enable the periodic schedule then wait EHC to
actually enable it.
@param Ehc The EHCI device.
@param Timeout The time to wait before abort (in millisecond, ms).
@@ -264,7 +264,7 @@ EhcEnablePeriodSchd (
/**
Enable asynchrounous schedule.
@param Ehc The EHCI device.
@param Timeout Time to wait before abort.
@@ -288,7 +288,7 @@ EhcEnableAsyncSchd (
/**
Check whether Ehc is halted.
@param Ehc The EHCI device.
@retval TRUE The controller is halted.
@@ -305,7 +305,7 @@ EhcIsHalt (
/**
Check whether system error occurred.
@param Ehc The EHCI device.
@retval TRUE System error happened.
@@ -322,7 +322,7 @@ EhcIsSysError (
/**
Reset the host controller.
@param Ehc The EHCI device.
@param Timeout Time to wait before abort (in millisecond, ms).
@@ -356,7 +356,7 @@ EhcResetHC (
/**
Halt the host controller.
@param Ehc The EHCI device.
@param Timeout Time to wait before abort.
@@ -379,7 +379,7 @@ EhcHaltHC (
/**
Set the EHCI to run.
@param Ehc The EHCI device.
@param Timeout Time to wait before abort.
@@ -402,7 +402,7 @@ EhcRunHC (
/**
Power On All EHCI Ports.
@param Ehc The EHCI device.
**/
@@ -414,7 +414,7 @@ EhcPowerOnAllPorts (
UINT8 PortNumber;
UINT8 Index;
UINT32 RegVal;
PortNumber = (UINT8)(Ehc->HcStructParams & HCSP_NPORTS);
for (Index = 0; Index < PortNumber; Index++) {
//
@@ -429,14 +429,14 @@ EhcPowerOnAllPorts (
}
/**
Initialize the HC hardware.
Initialize the HC hardware.
EHCI spec lists the five things to do to initialize the hardware.
1. Program CTRLDSSEGMENT.
2. Set USBINTR to enable interrupts.
3. Set periodic list base.
4. Set USBCMD, interrupt threshold, frame list size etc.
5. Write 1 to CONFIGFLAG to route all ports to EHCI.
@param Ehc The EHCI device.
@retval EFI_SUCCESS The EHCI has come out of halt state.
@@ -451,7 +451,7 @@ EhcInitHC (
EFI_STATUS Status;
EFI_PHYSICAL_ADDRESS TempPtr;
UINTN PageNumber;
ASSERT (EhcIsHalt (Ehc));
//
@@ -472,9 +472,9 @@ EhcInitHC (
return Status;
}
EhcPowerOnAllPorts (Ehc);
EhcPowerOnAllPorts (Ehc);
MicroSecondDelay (EHC_ROOT_PORT_RECOVERY_STALL);
Status = EhcInitSched (Ehc);
if (EFI_ERROR (Status)) {
@@ -523,26 +523,26 @@ EhcInitHC (
/**
Submits bulk transfer to a bulk endpoint of a USB device.
@param PeiServices The pointer of EFI_PEI_SERVICES.
@param This The pointer of PEI_USB2_HOST_CONTROLLER_PPI.
@param DeviceAddress Target device address.
@param EndPointAddress Endpoint number and its direction in bit 7.
@param DeviceSpeed Device speed, Low speed device doesn't support
@param DeviceSpeed Device speed, Low speed device doesn't support
bulk transfer.
@param MaximumPacketLength Maximum packet size the endpoint is capable of
@param MaximumPacketLength Maximum packet size the endpoint is capable of
sending or receiving.
@param Data Array of pointers to the buffers of data to transmit
@param Data Array of pointers to the buffers of data to transmit
from or receive into.
@param DataLength The lenght of the data buffer.
@param DataToggle On input, the initial data toggle for the transfer;
On output, it is updated to to next data toggle to use of
On output, it is updated to to next data toggle to use of
the subsequent bulk transfer.
@param TimeOut Indicates the maximum time, in millisecond, which the
transfer is allowed to complete.
If Timeout is 0, then the caller must wait for the function
to be completed until EFI_SUCCESS or EFI_DEVICE_ERROR is returned.
@param Translator A pointr to the transaction translator data.
@param Translator A pointr to the transaction translator data.
@param TransferResult A pointer to the detailed result information of the
bulk transfer.
@@ -577,7 +577,7 @@ EhcBulkTransfer (
//
// Validate the parameters
//
if ((DataLength == NULL) || (*DataLength == 0) ||
if ((DataLength == NULL) || (*DataLength == 0) ||
(Data == NULL) || (Data[0] == NULL) || (TransferResult == NULL)) {
return EFI_INVALID_PARAMETER;
}
@@ -652,10 +652,10 @@ ON_EXIT:
Retrieves the number of root hub ports.
@param[in] PeiServices The pointer to the PEI Services Table.
@param[in] This The pointer to this instance of the
@param[in] This The pointer to this instance of the
PEI_USB2_HOST_CONTROLLER_PPI.
@param[out] PortNumber The pointer to the number of the root hub ports.
@param[out] PortNumber The pointer to the number of the root hub ports.
@retval EFI_SUCCESS The port number was retrieved successfully.
@retval EFI_INVALID_PARAMETER PortNumber is NULL.
@@ -671,19 +671,19 @@ EhcGetRootHubPortNumber (
PEI_USB2_HC_DEV *EhcDev;
EhcDev = PEI_RECOVERY_USB_EHC_DEV_FROM_EHCI_THIS (This);
if (PortNumber == NULL) {
return EFI_INVALID_PARAMETER;
}
}
*PortNumber = (UINT8)(EhcDev->HcStructParams & HCSP_NPORTS);
return EFI_SUCCESS;
}
/**
Clears a feature for the specified root hub port.
@param PeiServices The pointer of EFI_PEI_SERVICES.
@param This The pointer of PEI_USB2_HOST_CONTROLLER_PPI.
@param PortNumber Specifies the root hub port whose feature
@@ -691,7 +691,7 @@ EhcGetRootHubPortNumber (
@param PortFeature Indicates the feature selector associated with the
feature clear request.
@retval EFI_SUCCESS The feature specified by PortFeature was cleared
@retval EFI_SUCCESS The feature specified by PortFeature was cleared
for the USB root hub port specified by PortNumber.
@retval EFI_INVALID_PARAMETER PortNumber is invalid or PortFeature is invalid.
@@ -805,7 +805,7 @@ ON_EXIT:
/**
Sets a feature for the specified root hub port.
@param PeiServices The pointer of EFI_PEI_SERVICES
@param This The pointer of PEI_USB2_HOST_CONTROLLER_PPI
@param PortNumber Root hub port to set.
@@ -876,7 +876,7 @@ EhcSetRootHubPortFeature (
break;
}
}
//
// Set one to PortReset bit must also set zero to PortEnable bit
//
@@ -907,10 +907,10 @@ ON_EXIT:
/**
Retrieves the current status of a USB root hub port.
@param PeiServices The pointer of EFI_PEI_SERVICES.
@param This The pointer of PEI_USB2_HOST_CONTROLLER_PPI.
@param PortNumber The root hub port to retrieve the state from.
@param PortNumber The root hub port to retrieve the state from.
@param PortStatus Variable to receive the port state.
@retval EFI_SUCCESS The status of the USB root hub port specified.
@@ -957,9 +957,9 @@ EhcGetRootHubPortStatus (
//
// Identify device speed. If in K state, it is low speed.
// If the port is enabled after reset, the device is of
// If the port is enabled after reset, the device is of
// high speed. The USB bus driver should retrieve the actual
// port speed after reset.
// port speed after reset.
//
if (EHC_BIT_IS_SET (State, PORTSC_LINESTATE_K)) {
PortStatus->PortStatus |= USB_PORT_STAT_LOW_SPEED;
@@ -967,7 +967,7 @@ EhcGetRootHubPortStatus (
} else if (EHC_BIT_IS_SET (State, PORTSC_ENABLED)) {
PortStatus->PortStatus |= USB_PORT_STAT_HIGH_SPEED;
}
//
// Convert the EHCI port/port change state to UEFI status
//
@@ -993,12 +993,12 @@ ON_EXIT:
/**
Submits control transfer to a target USB device.
@param PeiServices The pointer of EFI_PEI_SERVICES.
@param This The pointer of PEI_USB2_HOST_CONTROLLER_PPI.
@param DeviceAddress The target device address.
@param DeviceSpeed Target device speed.
@param MaximumPacketLength Maximum packet size the default control transfer
@param MaximumPacketLength Maximum packet size the default control transfer
endpoint is capable of sending or receiving.
@param Request USB device request to send.
@param TransferDirection Specifies the data direction for the data stage.
@@ -1052,12 +1052,12 @@ EhcControlTransfer (
return EFI_INVALID_PARAMETER;
}
if ((TransferDirection == EfiUsbNoData) &&
if ((TransferDirection == EfiUsbNoData) &&
((Data != NULL) || (*DataLength != 0))) {
return EFI_INVALID_PARAMETER;
}
if ((TransferDirection != EfiUsbNoData) &&
if ((TransferDirection != EfiUsbNoData) &&
((Data == NULL) || (*DataLength == 0))) {
return EFI_INVALID_PARAMETER;
}
@@ -1225,7 +1225,7 @@ EhcPeimEntry (
if (EFI_ERROR (Status)) {
break;
}
//
// This PEIM is for UHC type controller.
//
@@ -1303,19 +1303,19 @@ EhcPeimEntry (
**/
EFI_STATUS
InitializeUsbHC (
IN PEI_USB2_HC_DEV *EhcDev
IN PEI_USB2_HC_DEV *EhcDev
)
{
EFI_STATUS Status;
EhcResetHC (EhcDev, EHC_RESET_TIMEOUT);
Status = EhcInitHC (EhcDev);
if (EFI_ERROR (Status)) {
return EFI_ABORTED;
return EFI_ABORTED;
}
return EFI_SUCCESS;
}

26
MdeModulePkg/Bus/Pci/EhciPei/EhcPeim.h
View File

@@ -1,8 +1,8 @@
/** @file
Private Header file for Usb Host Controller PEIM
Copyright (c) 2010 - 2017, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions
of the BSD License which accompanies this distribution. The
@@ -118,20 +118,20 @@ struct _PEI_USB2_HC_DEV {
//
PEI_EHC_QTD *ShortReadStop;
EFI_EVENT PollTimer;
//
// Asynchronous(bulk and control) transfer schedule data:
// Asynchronous(bulk and control) transfer schedule data:
// ReclaimHead is used as the head of the asynchronous transfer
// list. It acts as the reclamation header.
// list. It acts as the reclamation header.
//
PEI_EHC_QH *ReclaimHead;
//
// Periodic (interrupt) transfer schedule data:
//
VOID *PeriodFrame; // Mapped as common buffer
VOID *PeriodFrame; // Mapped as common buffer
VOID *PeriodFrameMap;
PEI_EHC_QH *PeriodOne;
EFI_LIST_ENTRY AsyncIntTransfers;
@@ -156,14 +156,14 @@ struct _PEI_USB2_HC_DEV {
**/
EFI_STATUS
InitializeUsbHC (
IN PEI_USB2_HC_DEV *EhcDev
IN PEI_USB2_HC_DEV *EhcDev
);
/**
Initialize the memory management pool for the host controller.
@param Ehc The EHCI device.
@param Check4G Whether the host controller requires allocated memory
@param Check4G Whether the host controller requires allocated memory
from one 4G address space.
@param Which4G The 4G memory area each memory allocated should be from.
@@ -178,7 +178,7 @@ UsbHcInitMemPool (
IN UINT32 Which4G
)
;
/**
Release the memory management pool.
@@ -199,7 +199,7 @@ UsbHcFreeMemPool (
/**
Allocate some memory from the host controller's memory pool
which can be used to communicate with host controller.
@param Ehc The EHCI device.
@param Pool The host controller's memory pool.
@param Size Size of the memory to allocate.

4
MdeModulePkg/Bus/Pci/EhciPei/EhciPei.inf
View File

@@ -4,14 +4,14 @@
# It produces gPeiUsb2HostControllerPpiGuid based on gPeiUsbControllerPpiGuid
# which is used to enable recovery function from USB Drivers.
#
# Copyright (c) 2010 - 2017, Intel Corporation. All rights reserved.<BR>
# Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.<BR>
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions
# of the BSD License which accompanies this distribution. The
# full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#

4
MdeModulePkg/Bus/Pci/EhciPei/EhciPei.uni
View File

@@ -4,14 +4,14 @@
// It produces gPeiUsb2HostControllerPpiGuid based on gPeiUsbControllerPpiGuid
// which is used to enable recovery function from USB Drivers.
//
// Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved.<BR>
// Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.<BR>
//
// This program and the accompanying materials
// are licensed and made available under the terms and conditions
// of the BSD License which accompanies this distribution. The
// full text of the license may be found at
// http://opensource.org/licenses/bsd-license.php
//
//
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
//

6
MdeModulePkg/Bus/Pci/EhciPei/EhciPeiExtra.uni
View File

@@ -1,7 +1,7 @@
// /** @file
// EhciPei Localized Strings and Content
//
// Copyright (c) 2013 - 2014, Intel Corporation. All rights reserved.<BR>
// Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.<BR>
//
// This program and the accompanying materials
// are licensed and made available under the terms and conditions
@@ -14,8 +14,8 @@
//
// **/
#string STR_PROPERTIES_MODULE_NAME
#language en-US
#string STR_PROPERTIES_MODULE_NAME
#language en-US
"EHCI PEI Module for Recovery"

36
MdeModulePkg/Bus/Pci/EhciPei/EhciReg.h
View File

@@ -1,8 +1,8 @@
/** @file
Private Header file for Usb Host Controller PEIM
Copyright (c) 2010, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions
of the BSD License which accompanies this distribution. The
@@ -94,8 +94,8 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#define EHCI_IS_DATAIN(EndpointAddr) EHC_BIT_IS_SET((EndpointAddr), 0x80)
//
// Structure to map the hardware port states to the
// UEFI's port states.
// Structure to map the hardware port states to the
// UEFI's port states.
//
typedef struct {
UINT16 HwState;
@@ -116,7 +116,7 @@ typedef struct {
/**
Read EHCI capability register.
@param Ehc The EHCI device.
@param Offset Capability register address.
@@ -132,7 +132,7 @@ EhcReadCapRegister (
/**
Read Ehc Operation register.
@param Ehc The EHCI device.
@param Offset The operation register offset.
@@ -148,7 +148,7 @@ EhcReadOpReg (
/**
Write the data to the EHCI operation register.
@param Ehc The EHCI device.
@param Offset EHCI operation register offset.
@param Data The data to write.
@@ -164,7 +164,7 @@ EhcWriteOpReg (
/**
Stop the legacy USB SMI support.
@param Ehc The EHCI device.
**/
@@ -177,7 +177,7 @@ EhcClearLegacySupport (
/**
Set door bell and wait it to be ACKed by host controller.
This function is used to synchronize with the hardware.
@param Ehc The EHCI device.
@param Timeout The time to wait before abort (in millisecond, ms).
@@ -193,9 +193,9 @@ EhcSetAndWaitDoorBell (
;
/**
Clear all the interrutp status bits, these bits
Clear all the interrutp status bits, these bits
are Write-Clean.
@param Ehc The EHCI device.
**/
@@ -207,7 +207,7 @@ EhcAckAllInterrupt (
/**
Check whether Ehc is halted.
@param Ehc The EHCI device.
@retval TRUE The controller is halted.
@@ -222,7 +222,7 @@ EhcIsHalt (
/**
Check whether system error occurred.
@param Ehc The EHCI device.
@retval TRUE System error happened.
@@ -237,7 +237,7 @@ EhcIsSysError (
/**
Reset the host controller.
@param Ehc The EHCI device.
@param Timeout Time to wait before abort (in millisecond, ms).
@@ -254,7 +254,7 @@ EhcResetHC (
/**
Halt the host controller.
@param Ehc The EHCI device.
@param Timeout Time to wait before abort.
@@ -271,7 +271,7 @@ EhcHaltHC (
/**
Set the EHCI to run
@param Ehc The EHCI device.
@param Timeout Time to wait before abort.
@@ -287,14 +287,14 @@ EhcRunHC (
;
/**
Initialize the HC hardware.
Initialize the HC hardware.
EHCI spec lists the five things to do to initialize the hardware.
1. Program CTRLDSSEGMENT.
2. Set USBINTR to enable interrupts.
3. Set periodic list base.
4. Set USBCMD, interrupt threshold, frame list size etc.
5. Write 1 to CONFIGFLAG to route all ports to EHCI.
@param Ehc The EHCI device.
@retval EFI_SUCCESS The EHCI has come out of halt state.

30
MdeModulePkg/Bus/Pci/EhciPei/EhciSched.c
View File

@@ -2,8 +2,8 @@
PEIM to produce gPeiUsb2HostControllerPpiGuid based on gPeiUsbControllerPpiGuid
which is used to enable recovery function from USB Drivers.
Copyright (c) 2010 - 2017, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions
of the BSD License which accompanies this distribution. The
@@ -19,7 +19,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
/**
Create helper QTD/QH for the EHCI device.
@param Ehc The EHCI device.
@retval EFI_OUT_OF_RESOURCES Failed to allocate resource for helper QTD/QH.
@@ -95,7 +95,7 @@ EhcCreateHelpQ (
/**
Initialize the schedule data structure such as frame list.
@param Ehc The EHCI device to init schedule data for.
@retval EFI_OUT_OF_RESOURCES Failed to allocate resource to init schedule data.
@@ -162,7 +162,7 @@ EhcInitSched (
if (EFI_ERROR (Status)) {
return Status;
}
//
// Initialize the frame list entries then set the registers
//
@@ -186,8 +186,8 @@ EhcInitSched (
/**
Free the schedule data. It may be partially initialized.
@param Ehc The EHCI device.
@param Ehc The EHCI device.
**/
VOID
@@ -230,7 +230,7 @@ EhcFreeSched (
due to its interfaces. This simplifies the AsynList
management: A reclamation header is always linked to
the AsyncListAddr, the only active QH is appended to it.
@param Ehc The EHCI device.
@param Qh The queue head to link.
@@ -260,7 +260,7 @@ EhcLinkQhToAsync (
/**
Unlink a queue head from the asynchronous schedule list.
Need to synchronize with hardware.
@param Ehc The EHCI device.
@param Qh The queue head to unlink.
@@ -291,13 +291,13 @@ EhcUnlinkQhFromAsync (
// Set and wait the door bell to synchronize with the hardware
//
EhcSetAndWaitDoorBell (Ehc, EHC_GENERIC_TIMEOUT);
return;
}
/**
Check the URB's execution result and update the URB's
result accordingly.
result accordingly.
@param Ehc The EHCI device.
@param Urb The URB to check result.
@@ -358,13 +358,13 @@ EhcCheckUrbResult (
Finished = TRUE;
goto ON_EXIT;
} else if (EHC_BIT_IS_SET (State, QTD_STAT_ACTIVE)) {
//
// The QTD is still active, no need to check furthur.
//
Urb->Result |= EFI_USB_ERR_NOTEXECUTE;
Finished = FALSE;
goto ON_EXIT;
@@ -387,7 +387,7 @@ EhcCheckUrbResult (
// Status Stage of the setup transfer to get the finial result
//
if (QtdHw->AltNext == QTD_LINK (Ehc->ShortReadStop, FALSE)) {
Finished = TRUE;
goto ON_EXIT;
}
@@ -412,7 +412,7 @@ ON_EXIT:
/**
Execute the transfer by polling the URB. This is a synchronous operation.
@param Ehc The EHCI device.
@param Urb The URB to execute.
@param TimeOut The time to wait before abort, in millisecond.

14
MdeModulePkg/Bus/Pci/EhciPei/EhciSched.h
View File

@@ -1,8 +1,8 @@
/** @file
Private Header file for Usb Host Controller PEIM
Copyright (c) 2010 - 2011, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions
of the BSD License which accompanies this distribution. The
@@ -19,7 +19,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
/**
Initialize the schedule data structure such as frame list.
@param Ehc The EHCI device to init schedule data for.
@retval EFI_OUT_OF_RESOURCES Failed to allocate resource to init schedule data.
@@ -34,7 +34,7 @@ EhcInitSched (
/**
Free the schedule data. It may be partially initialized.
@param Ehc The EHCI device.
**/
@@ -50,7 +50,7 @@ EhcFreeSched (
due to its interfaces. This simplifies the AsynList
management: A reclamation header is always linked to
the AsyncListAddr, the only active QH is appended to it.
@param Ehc The EHCI device.
@param Qh The queue head to link.
@@ -65,7 +65,7 @@ EhcLinkQhToAsync (
/**
Unlink a queue head from the asynchronous schedule list.
Need to synchronize with hardware.
@param Ehc The EHCI device.
@param Qh The queue head to unlink.
@@ -79,7 +79,7 @@ EhcUnlinkQhFromAsync (
/**
Execute the transfer by polling the URB. This is a synchronous operation.
@param Ehc The EHCI device.
@param Urb The URB to execute.
@param TimeOut The time to wait before abort, in millisecond.

36
MdeModulePkg/Bus/Pci/EhciPei/EhciUrb.c
View File

@@ -2,8 +2,8 @@
PEIM to produce gPeiUsb2HostControllerPpiGuid based on gPeiUsbControllerPpiGuid
which is used to enable recovery function from USB Drivers.
Copyright (c) 2010 - 2017, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions
of the BSD License which accompanies this distribution. The
@@ -20,7 +20,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
/**
Delete a single asynchronous interrupt transfer for
the device and endpoint.
@param Ehc The EHCI device.
@param Data Current data not associated with a QTD.
@param DataLen The length of the data.
@@ -96,7 +96,7 @@ EhcCreateQtd (
Len += ThisBufLen;
Data += ThisBufLen;
}
//
// Need to fix the last pointer if the Qtd can't hold all the
// user's data to make sure that the length is in the unit of
@@ -120,7 +120,7 @@ EhcCreateQtd (
1. SplitXState in the Status field.
2. Microframe S-mask.
3. Microframe C-mask.
@param Ep The queue head's related endpoint.
@param QhHw The queue head to initialize.
@@ -142,7 +142,7 @@ EhcInitIntQh (
QhHw->SMask = QH_MICROFRAME_0;
return ;
}
//
// For low/full speed device, the transfer must go through
// the split transaction. Need to update three fields
@@ -160,7 +160,7 @@ EhcInitIntQh (
/**
Allocate and initialize a EHCI queue head.
@param Ehci The EHCI device.
@param Ep The endpoint to create queue head for.
@@ -185,7 +185,7 @@ EhcCreateQh (
Qh->Signature = EHC_QH_SIG;
Qh->NextQh = NULL;
Qh->Interval = Ep->PollRate;
InitializeListHead (&Qh->Qtds);
QhHw = &Qh->QhHw;
@@ -250,7 +250,7 @@ EhcCreateQh (
can't support high speed endpoint with a interval less
than 8 microframe because interval is specified in
the unit of ms (millisecond).
@param Interval The interval to convert.
@retval The converted interval.
@@ -266,7 +266,7 @@ EhcConvertPollRate (
if (Interval == 0) {
return 1;
}
//
// Find the index (1 based) of the highest non-zero bit
//
@@ -282,7 +282,7 @@ EhcConvertPollRate (
/**
Free a list of QTDs.
@param Ehc The EHCI device.
@param Qtds The list head of the QTD.
@@ -307,7 +307,7 @@ EhcFreeQtds (
/**
Free an allocated URB. It is possible for it to be partially inited.
@param Ehc The EHCI device.
@param Urb The URB to free.
@@ -338,7 +338,7 @@ EhcFreeUrb (
/**
Create a list of QTDs for the URB.
@param Ehc The EHCI device.
@param Urb The URB to create QTDs for.
@@ -380,7 +380,7 @@ EhcCreateQtds (
if (Ep->Direction == EfiUsbDataIn) {
AlterNext = QTD_LINK (Ehc->ShortReadStop, FALSE);
}
//
// Build the Setup and status packets for control transfer
//
@@ -457,7 +457,7 @@ EhcCreateQtds (
Len += Qtd->DataLen;
}
//
// Insert the status packet for control transfer
//
@@ -496,7 +496,7 @@ ON_ERROR:
/**
Create a new URB and its associated QTD.
@param Ehc The EHCI device.
@param DevAddr The device address.
@param EpAddr Endpoint addrress & its direction.
@@ -519,7 +519,7 @@ PEI_URB *
EhcCreateUrb (
IN PEI_USB2_HC_DEV *Ehc,
IN UINT8 DevAddr,
IN UINT8 EpAddr,
IN UINT8 EpAddr,
IN UINT8 DevSpeed,
IN UINT8 Toggle,
IN UINTN MaxPacket,
@@ -540,7 +540,7 @@ EhcCreateUrb (
UINTN Len;
PEI_URB *Urb;
VOID *Map;
Urb = Ehc->Urb;
Urb->Signature = EHC_URB_SIG;
InitializeListHead (&Urb->UrbList);

54
MdeModulePkg/Bus/Pci/EhciPei/EhciUrb.h
View File

@@ -1,8 +1,8 @@
/** @file
Private Header file for Usb Host Controller PEIM
Copyright (c) 2010, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions
of the BSD License which accompanies this distribution. The
@@ -73,7 +73,7 @@ typedef struct _PEI_URB PEI_URB;
#define USB_ERR_SHORT_PACKET 0x200
//
// Fill in the hardware link point: pass in a EHC_QH/QH_HW
// Fill in the hardware link point: pass in a EHC_QH/QH_HW
// pointer to QH_LINK; A EHC_QTD/QTD_HW pointer to QTD_LINK
//
#define QH_LINK(Addr, Type, Term) \
@@ -82,16 +82,16 @@ typedef struct _PEI_URB PEI_URB;
#define QTD_LINK(Addr, Term) QH_LINK((Addr), 0, (Term))
//
// The defination of EHCI hardware used data structure for
// little endian architecture. The QTD and QH structures
// are required to be 32 bytes aligned. Don't add members
// The defination of EHCI hardware used data structure for
// little endian architecture. The QTD and QH structures
// are required to be 32 bytes aligned. Don't add members
// to the head of the associated software strucuture.
//
#pragma pack(1)
typedef struct {
UINT32 NextQtd;
UINT32 AltNext;
UINT32 Status : 8;
UINT32 Pid : 2;
UINT32 ErrCnt : 2;
@@ -105,7 +105,7 @@ typedef struct {
} QTD_HW;
typedef struct {
UINT32 HorizonLink;
UINT32 HorizonLink;
//
// Endpoint capabilities/Characteristics DWord 1 and DWord 2
//
@@ -131,7 +131,7 @@ typedef struct {
UINT32 CurQtd;
UINT32 NextQtd;
UINT32 AltQtd;
UINT32 Status : 8;
UINT32 Pid : 2;
UINT32 ErrCnt : 2;
@@ -163,7 +163,7 @@ typedef struct _USB_ENDPOINT {
} USB_ENDPOINT;
//
// Software QTD strcture, this is used to manage all the
// Software QTD strcture, this is used to manage all the
// QTD generated from a URB. Don't add fields before QtdHw.
//
struct _PEI_EHC_QTD {
@@ -177,17 +177,17 @@ struct _PEI_EHC_QTD {
//
// Software QH structure. All three different transaction types
// supported by UEFI USB, that is the control/bulk/interrupt
// transfers use the queue head and queue token strcuture.
// Software QH structure. All three different transaction types
// supported by UEFI USB, that is the control/bulk/interrupt
// transfers use the queue head and queue token strcuture.
//
// Interrupt QHs are linked to periodic frame list in the reversed
// 2^N tree. Each interrupt QH is linked to the list starting at
// 2^N tree. Each interrupt QH is linked to the list starting at
// frame 0. There is a dummy interrupt QH linked to each frame as
// a sentinental whose polling interval is 1. Synchronous interrupt
// transfer is linked after this dummy QH.
//
// For control/bulk transfer, only synchronous (in the sense of UEFI)
// transfer is linked after this dummy QH.
//
// For control/bulk transfer, only synchronous (in the sense of UEFI)
// transfer is supported. A dummy QH is linked to EHCI AsyncListAddr
// as the reclamation header. New transfer is inserted after this QH.
//
@@ -196,17 +196,17 @@ struct _PEI_EHC_QH {
UINT32 Signature;
PEI_EHC_QH *NextQh; // The queue head pointed to by horizontal link
EFI_LIST_ENTRY Qtds; // The list of QTDs to this queue head
UINTN Interval;
UINTN Interval;
};
//
// URB (Usb Request Block) contains information for all kinds of
// URB (Usb Request Block) contains information for all kinds of
// usb requests.
//
struct _PEI_URB {
UINT32 Signature;
EFI_LIST_ENTRY UrbList;
//
// Transaction information
//
@@ -218,14 +218,14 @@ struct _PEI_URB {
UINTN DataLen;
VOID *DataPhy; // Address of the mapped user data
VOID *DataMap;
EFI_ASYNC_USB_TRANSFER_CALLBACK Callback;
EFI_ASYNC_USB_TRANSFER_CALLBACK Callback;
VOID *Context;
//
// Schedule data
//
PEI_EHC_QH *Qh;
//
// Transaction result
//
@@ -237,7 +237,7 @@ struct _PEI_URB {
/**
Delete a single asynchronous interrupt transfer for
the device and endpoint.
@param Ehc The EHCI device.
@param Data Current data not associated with a QTD.
@param DataLen The length of the data.
@@ -261,7 +261,7 @@ EhcCreateQtd (
/**
Allocate and initialize a EHCI queue head.
@param Ehci The EHCI device.
@param Ep The endpoint to create queue head for.
@@ -277,7 +277,7 @@ EhcCreateQh (
/**
Free an allocated URB. It is possible for it to be partially inited.
@param Ehc The EHCI device.
@param Urb The URB to free.
@@ -291,7 +291,7 @@ EhcFreeUrb (
/**
Create a new URB and its associated QTD.
@param Ehc The EHCI device.
@param DevAddr The device address.
@param EpAddr Endpoint addrress & its direction.
@@ -314,7 +314,7 @@ PEI_URB *
EhcCreateUrb (
IN PEI_USB2_HC_DEV *Ehc,
IN UINT8 DevAddr,
IN UINT8 EpAddr,
IN UINT8 EpAddr,
IN UINT8 DevSpeed,
IN UINT8 Toggle,
IN UINTN MaxPacket,

30
MdeModulePkg/Bus/Pci/EhciPei/UsbHcMem.c
View File

@@ -2,8 +2,8 @@
PEIM to produce gPeiUsb2HostControllerPpiGuid based on gPeiUsbControllerPpiGuid
which is used to enable recovery function from USB Drivers.
Copyright (c) 2010 - 2017, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions
of the BSD License which accompanies this distribution. The
@@ -54,28 +54,28 @@ UsbHcAllocMemBlock (
return NULL;
}
ZeroMem ((VOID *)(UINTN)TempPtr, PageNumber*EFI_PAGE_SIZE);
//
// each bit in the bit array represents USBHC_MEM_UNIT
// bytes of memory in the memory block.
//
ASSERT (USBHC_MEM_UNIT * 8 <= EFI_PAGE_SIZE);
Block = (USBHC_MEM_BLOCK*)(UINTN)TempPtr;
Block->BufLen = EFI_PAGES_TO_SIZE (Pages);
Block->BitsLen = Block->BufLen / (USBHC_MEM_UNIT * 8);
PageNumber = (Block->BitsLen)/PAGESIZE +1;
Status = PeiServicesAllocatePages (
EfiBootServicesCode,
PageNumber,
&TempPtr
);
if (EFI_ERROR (Status)) {
return NULL;
}
ZeroMem ((VOID *)(UINTN)TempPtr, PageNumber*EFI_PAGE_SIZE);
ZeroMem ((VOID *)(UINTN)TempPtr, PageNumber*EFI_PAGE_SIZE);
Block->Bits = (UINT8 *)(UINTN)TempPtr;
@@ -184,7 +184,7 @@ UsbHcAllocMemFromBlock (
if (Available < Units) {
return NULL;
}
//
// Mark the memory as allocated
//
@@ -283,7 +283,7 @@ UsbHcIsMemBlockEmpty (
{
UINTN Index;
for (Index = 0; Index < Block->BitsLen; Index++) {
if (Block->Bits[Index] != 0) {
return FALSE;
@@ -321,7 +321,7 @@ UsbHcUnlinkMemBlock (
/**
Initialize the memory management pool for the host controller.
@param Ehc The EHCI device.
@param Check4G Whether the host controller requires allocated memory.
from one 4G address space.
@@ -342,7 +342,7 @@ UsbHcInitMemPool (
UINTN PageNumber;
EFI_STATUS Status;
EFI_PHYSICAL_ADDRESS TempPtr;
PageNumber = sizeof(USBHC_MEM_POOL)/PAGESIZE +1;
Status = PeiServicesAllocatePages (
EfiBootServicesCode,
@@ -353,9 +353,9 @@ UsbHcInitMemPool (
if (EFI_ERROR (Status)) {
return NULL;
}
ZeroMem ((VOID *)(UINTN)TempPtr, PageNumber*EFI_PAGE_SIZE);
ZeroMem ((VOID *)(UINTN)TempPtr, PageNumber*EFI_PAGE_SIZE);
Pool = (USBHC_MEM_POOL *) ((UINTN) TempPtr);
Pool = (USBHC_MEM_POOL *) ((UINTN) TempPtr);
Pool->Check4G = Check4G;
Pool->Which4G = Which4G;
@@ -405,7 +405,7 @@ UsbHcFreeMemPool (
/**
Allocate some memory from the host controller's memory pool
which can be used to communicate with host controller.
@param Ehc The EHCI device.
@param Pool The host controller's memory pool.
@param Size Size of the memory to allocate.
@@ -464,7 +464,7 @@ UsbHcAllocateMem (
if (NewBlock == NULL) {
return NULL;
}
//
// Add the new memory block to the pool, then allocate memory from it
//

18
MdeModulePkg/Bus/Pci/EhciPei/UsbHcMem.h
View File

@@ -1,8 +1,8 @@
/** @file
Private Header file for Usb Host Controller PEIM
Copyright (c) 2010 - 2017, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions
of the BSD License which accompanies this distribution. The
@@ -32,22 +32,22 @@ typedef struct _USBHC_MEM_BLOCK USBHC_MEM_BLOCK;
struct _USBHC_MEM_BLOCK {
UINT8 *Bits; // Bit array to record which unit is allocated
UINTN BitsLen;
UINTN BitsLen;
UINT8 *Buf;
UINT8 *BufHost;
UINTN BufLen; // Memory size in bytes
VOID *Mapping;
VOID *Mapping;
USBHC_MEM_BLOCK *Next;
};
//
// USBHC_MEM_POOL is used to manage the memory used by USB
// USBHC_MEM_POOL is used to manage the memory used by USB
// host controller. EHCI requires the control memory and transfer
// data to be on the same 4G memory.
// data to be on the same 4G memory.
//
typedef struct _USBHC_MEM_POOL {
BOOLEAN Check4G;
UINT32 Which4G;
BOOLEAN Check4G;
UINT32 Which4G;
USBHC_MEM_BLOCK *Head;
} USBHC_MEM_POOL;
@@ -71,7 +71,7 @@ typedef struct _USBHC_MEM_POOL {
(Byte)++; \
(Bit) = 0; \
} \
} while (0)
} while (0)
/**