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MdeModulePkg: Clean up source files

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Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Liming Gao <liming.gao@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
This commit is contained in:
Liming Gao
2018-06-27 21:08:52 +08:00
parent ca79bab7af
commit d1102dba72
1010 changed files with 13588 additions and 13588 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.c
View File

@@ -140,7 +140,7 @@ PciBusDriverBindingSupported (
//
if (RemainingDevicePath != NULL) {
//
// Check if RemainingDevicePath is the End of Device Path Node,
// Check if RemainingDevicePath is the End of Device Path Node,
// if yes, go on checking other conditions
//
if (!IsDevicePathEnd (RemainingDevicePath)) {
@@ -254,7 +254,7 @@ PciBusDriverBindingStart (
//
if (RemainingDevicePath != NULL) {
//
// Check if RemainingDevicePath is the End of Device Path Node,
// Check if RemainingDevicePath is the End of Device Path Node,
// if yes, return EFI_SUCCESS
//
if (IsDevicePathEnd (RemainingDevicePath)) {
@@ -282,14 +282,14 @@ PciBusDriverBindingStart (
//
// If PCI Platform protocol doesn't exist, try to Pci Override Protocol.
//
if (gPciPlatformProtocol == NULL) {
if (gPciPlatformProtocol == NULL) {
gPciOverrideProtocol = NULL;
gBS->LocateProtocol (
&gEfiPciOverrideProtocolGuid,
NULL,
(VOID **) &gPciOverrideProtocol
);
}
}
if (mIoMmuProtocol == NULL) {
gBS->LocateProtocol (
@@ -315,7 +315,7 @@ PciBusDriverBindingStart (
This->DriverBindingHandle,
Controller,
EFI_OPEN_PROTOCOL_GET_PROTOCOL
);
);
ASSERT_EFI_ERROR (Status);
//

6
MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
View File

@@ -2,7 +2,7 @@
# The PCI bus driver will probe all PCI devices and allocate MMIO and IO space for these devices.
# Please use PCD feature flag PcdPciBusHotplugDeviceSupport to enable hot plug supporting.
#
# Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>
# Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
@@ -90,8 +90,8 @@
gEfiPciHotPlugInitProtocolGuid ## SOMETIMES_CONSUMES
gEfiPciHostBridgeResourceAllocationProtocolGuid ## TO_START
gEfiPciPlatformProtocolGuid ## SOMETIMES_CONSUMES
gEfiPciOverrideProtocolGuid ## SOMETIMES_CONSUMES
gEfiPciEnumerationCompleteProtocolGuid ## PRODUCES
gEfiPciOverrideProtocolGuid ## SOMETIMES_CONSUMES
gEfiPciEnumerationCompleteProtocolGuid ## PRODUCES
gEfiPciRootBridgeIoProtocolGuid ## TO_START
gEfiIncompatiblePciDeviceSupportProtocolGuid ## SOMETIMES_CONSUMES
gEfiLoadFile2ProtocolGuid ## SOMETIMES_PRODUCES

6
MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxeExtra.uni
View File

@@ -1,7 +1,7 @@
// /** @file
// PciBusDxe Localized Strings and Content
//
// Copyright (c) 2013 - 2014, Intel Corporation. All rights reserved.<BR>
// Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.<BR>
//
// This program and the accompanying materials
// are licensed and made available under the terms and conditions of the BSD License
@@ -12,8 +12,8 @@
//
// **/
#string STR_PROPERTIES_MODULE_NAME
#language en-US
#string STR_PROPERTIES_MODULE_NAME
#language en-US
"PCI Bus DXE Driver"

4
MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c
View File

@@ -236,7 +236,7 @@ RegisterPciDevice (
PciIo = &(PciIoDevice->PciIo);
Data8 = PCI_INT_LINE_UNKNOWN;
PciIo->Pci.Write (PciIo, EfiPciIoWidthUint8, 0x3C, 1, &Data8);
//
// Process OpRom
//
@@ -296,7 +296,7 @@ RegisterPciDevice (
PciIoDevice->PciIo.RomImage,
PciIoDevice->PciIo.RomSize
);
}
}
}
}

12
MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumerator.c
View File

@@ -187,7 +187,7 @@ PciRootBridgeEnumerator (
AddrRangeMin = Configuration1->AddrRangeMin;
Configuration1->AddrRangeMin = Configuration2->AddrRangeMin;
Configuration2->AddrRangeMin = AddrRangeMin;
AddrLen = Configuration1->AddrLen;
Configuration1->AddrLen = Configuration2->AddrLen;
Configuration2->AddrLen = AddrLen;
@@ -234,7 +234,7 @@ PciRootBridgeEnumerator (
Status = PciAllocateBusNumber (RootBridgeDev, SubBusNumber, PaddedBusRange, &SubBusNumber);
if (EFI_ERROR (Status)) {
return Status;
}
}
//
// Find the bus range which contains the higest bus number, then returns the number of buses
@@ -252,7 +252,7 @@ PciRootBridgeEnumerator (
Configuration++;
Desc = Configuration->Desc;
Configuration->Desc = ACPI_END_TAG_DESCRIPTOR;
//
// Set bus number
//
@@ -267,7 +267,7 @@ PciRootBridgeEnumerator (
//
Configuration->Desc = Desc;
(Configuration - 1)->AddrLen = AddrLen;
return Status;
}
@@ -1812,7 +1812,7 @@ NotifyPhase (
Phase,
ChipsetEntry
);
}
}
Status = PciResAlloc->NotifyPhase (
PciResAlloc,
@@ -2043,7 +2043,7 @@ PciHotPlugRequestNotify (
return EFI_INVALID_PARAMETER;
}
}
Status = gBS->OpenProtocol (
Controller,
&gEfiPciIoProtocolGuid,

6
MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c
View File

@@ -1736,7 +1736,7 @@ PciIovParseVfBar (
break;
}
}
//
// Check the length again so as to keep compatible with some special bars
//
@@ -1745,7 +1745,7 @@ PciIovParseVfBar (
PciIoDevice->VfPciBar[BarIndex].BaseAddress = 0;
PciIoDevice->VfPciBar[BarIndex].Alignment = 0;
}
//
// Increment number of bar
//
@@ -2185,7 +2185,7 @@ CreatePciIoDevice (
//
ParentPciIo = &Bridge->PciIo;
ParentPciIo->Pci.Read (
ParentPciIo,
ParentPciIo,
EfiPciIoWidthUint32,
Bridge->PciExpressCapabilityOffset + EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_OFFSET,
1,

44
MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c
View File

@@ -1,7 +1,7 @@
/** @file
EFI PCI IO protocol functions implementation for PCI Bus module.
Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -232,7 +232,7 @@ PciIoPollMem (
//
// If request is not aligned, then convert request to EfiPciIoWithXXXUint8
//
//
if (FeaturePcdGet (PcdUnalignedPciIoEnable)) {
if ((Offset & ((1 << (Width & 0x03)) - 1)) != 0) {
Status = PciIoMemRead (This, Width, BarIndex, Offset, 1, Result);
@@ -262,7 +262,7 @@ PciIoPollMem (
} while (TRUE);
}
}
Status = PciIoDevice->PciRootBridgeIo->PollMem (
PciIoDevice->PciRootBridgeIo,
(EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,
@@ -335,7 +335,7 @@ PciIoPollIo (
//
// If request is not aligned, then convert request to EfiPciIoWithXXXUint8
//
//
if (FeaturePcdGet (PcdUnalignedPciIoEnable)) {
if ((Offset & ((1 << (Width & 0x03)) - 1)) != 0) {
Status = PciIoIoRead (This, Width, BarIndex, Offset, 1, Result);
@@ -365,7 +365,7 @@ PciIoPollIo (
} while (TRUE);
}
}
Status = PciIoDevice->PciRootBridgeIo->PollIo (
PciIoDevice->PciRootBridgeIo,
(EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,
@@ -438,14 +438,14 @@ PciIoMemRead (
//
// If request is not aligned, then convert request to EfiPciIoWithXXXUint8
//
//
if (FeaturePcdGet (PcdUnalignedPciIoEnable)) {
if ((Offset & ((1 << (Width & 0x03)) - 1)) != 0) {
Count *= (UINTN)(1 << (Width & 0x03));
Width = (EFI_PCI_IO_PROTOCOL_WIDTH) (Width & (~0x03));
}
}
}
Status = PciIoDevice->PciRootBridgeIo->Mem.Read (
PciIoDevice->PciRootBridgeIo,
@@ -517,7 +517,7 @@ PciIoMemWrite (
//
// If request is not aligned, then convert request to EfiPciIoWithXXXUint8
//
//
if (FeaturePcdGet (PcdUnalignedPciIoEnable)) {
if ((Offset & ((1 << (Width & 0x03)) - 1)) != 0) {
Count *= (UINTN)(1 << (Width & 0x03));
@@ -595,13 +595,13 @@ PciIoIoRead (
//
// If request is not aligned, then convert request to EfiPciIoWithXXXUint8
//
//
if (FeaturePcdGet (PcdUnalignedPciIoEnable)) {
if ((Offset & ((1 << (Width & 0x03)) - 1)) != 0) {
Count *= (UINTN)(1 << (Width & 0x03));
Width = (EFI_PCI_IO_PROTOCOL_WIDTH) (Width & (~0x03));
}
}
}
Status = PciIoDevice->PciRootBridgeIo->Io.Read (
PciIoDevice->PciRootBridgeIo,
@@ -673,13 +673,13 @@ PciIoIoWrite (
//
// If request is not aligned, then convert request to EfiPciIoWithXXXUint8
//
//
if (FeaturePcdGet (PcdUnalignedPciIoEnable)) {
if ((Offset & ((1 << (Width & 0x03)) - 1)) != 0) {
Count *= (UINTN)(1 << (Width & 0x03));
Width = (EFI_PCI_IO_PROTOCOL_WIDTH) (Width & (~0x03));
}
}
}
Status = PciIoDevice->PciRootBridgeIo->Io.Write (
PciIoDevice->PciRootBridgeIo,
@@ -739,16 +739,16 @@ PciIoConfigRead (
if (EFI_ERROR (Status)) {
return Status;
}
//
// If request is not aligned, then convert request to EfiPciIoWithXXXUint8
//
//
if (FeaturePcdGet (PcdUnalignedPciIoEnable)) {
if ((Offset & ((1 << (Width & 0x03)) - 1)) != 0) {
Count *= (UINTN)(1 << (Width & 0x03));
Width = (EFI_PCI_IO_PROTOCOL_WIDTH) (Width & (~0x03));
}
}
}
Status = PciIoDevice->PciRootBridgeIo->Pci.Read (
PciIoDevice->PciRootBridgeIo,
@@ -811,14 +811,14 @@ PciIoConfigWrite (
//
// If request is not aligned, then convert request to EfiPciIoWithXXXUint8
//
//
if (FeaturePcdGet (PcdUnalignedPciIoEnable)) {
if ((Offset & ((1 << (Width & 0x03)) - 1)) != 0) {
Count *= (UINTN)(1 << (Width & 0x03));
Width = (EFI_PCI_IO_PROTOCOL_WIDTH) (Width & (~0x03));
}
}
}
Status = PciIoDevice->PciRootBridgeIo->Pci.Write (
PciIoDevice->PciRootBridgeIo,
(EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,
@@ -910,13 +910,13 @@ PciIoCopyMem (
//
// If request is not aligned, then convert request to EfiPciIoWithXXXUint8
//
//
if (FeaturePcdGet (PcdUnalignedPciIoEnable)) {
if ((SrcOffset & ((1 << (Width & 0x03)) - 1)) != 0 || (DestOffset & ((1 << (Width & 0x03)) - 1)) != 0) {
Count *= (UINTN)(1 << (Width & 0x03));
Width = (EFI_PCI_IO_PROTOCOL_WIDTH) (Width & (~0x03));
}
}
}
Status = PciIoDevice->PciRootBridgeIo->CopyMem (
PciIoDevice->PciRootBridgeIo,
@@ -1790,7 +1790,7 @@ PciIoAttributes (
@param AddrRangeMin The base address of the MMIO.
@param AddrLen The length of the MMIO.
@retval The AddrTranslationOffset from RootBridgeIo for the
@retval The AddrTranslationOffset from RootBridgeIo for the
specified range, or (UINT64) -1 if the range is not
found in RootBridgeIo.
**/

6
MdeModulePkg/Bus/Pci/PciBusDxe/PciLib.c
View File

@@ -269,11 +269,11 @@ DumpBridgeResource (
/**
Find the corresponding resource node for the Device in child list of BridgeResource.
@param[in] Device Pointer to PCI_IO_DEVICE.
@param[in] BridgeResource Pointer to PCI_RESOURCE_NODE.
@param[out] DeviceResources Pointer to a buffer to receive resources for the Device.
@return Count of the resource descriptors returned.
**/
UINTN
@@ -306,7 +306,7 @@ FindResourceNode (
/**
Dump the resource map of all the devices under Bridge.
@param[in] Bridge Bridge device instance.
@param[in] Resources Resource descriptors for the bridge device.
@param[in] ResourceCount Count of resource descriptors.

8
MdeModulePkg/Bus/Pci/PciBusDxe/PciOptionRomSupport.c
View File

@@ -1,7 +1,7 @@
/** @file
PCI Rom supporting funtions implementation for PCI Bus module.
Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -342,7 +342,7 @@ ContainEfiImage (
}
//
// The PCI Data Structure must be DWORD aligned.
// The PCI Data Structure must be DWORD aligned.
//
if (RomHeader->PcirOffset == 0 ||
(RomHeader->PcirOffset & 3) != 0 ||
@@ -471,8 +471,8 @@ LoadOpRomImage (
FirstCheck = FALSE;
OffsetPcir = RomHeader->PcirOffset;
//
// If the pointer to the PCI Data Structure is invalid, no further images can be located.
// The PCI Data Structure must be DWORD aligned.
// If the pointer to the PCI Data Structure is invalid, no further images can be located.
// The PCI Data Structure must be DWORD aligned.
//
if (OffsetPcir == 0 ||
(OffsetPcir & 3) != 0 ||

4
MdeModulePkg/Bus/Pci/PciBusDxe/PciResourceSupport.c
View File

@@ -1,7 +1,7 @@
/** @file
PCI resouces support functions implemntation for PCI Bus module.
Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -1116,7 +1116,7 @@ DegradeResource (
PMem64Node,
TRUE
);
}
}
//
// if both PMEM64 and PMEM32 requests from child devices, which can not be satisfied