sravan/system76-edk2
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

MdeModulePkg: Clean up source files

Browse Source 
1. Do not use tab characters
2. No trailing white space in one line
3. All files must end with CRLF

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Liming Gao <liming.gao@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
This commit is contained in:
Liming Gao
2018-06-27 21:08:52 +08:00
parent ca79bab7af
commit d1102dba72
1010 changed files with 13588 additions and 13588 deletions
Download Patch File Download Diff File Expand all files Collapse all files

28
MdeModulePkg/Bus/Pci/XhciDxe/UsbHcMem.c
View File

@@ -2,7 +2,7 @@
Routine procedures for memory allocate/free.
Copyright (c) 2013 - 2016, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -598,23 +598,23 @@ UsbHcFreeMem (
return ;
}
/**
/**
Allocates pages at a specified alignment that are suitable for an EfiPciIoOperationBusMasterCommonBuffer mapping.
If Alignment is not a power of two and Alignment is not zero, then ASSERT().
@param PciIo The PciIo that can be used to access the host controller.
@param Pages The number of pages to allocate.
@param Alignment The requested alignment of the allocation. Must be a power of two.
@param HostAddress The system memory address to map to the PCI controller.
@param DeviceAddress The resulting map address for the bus master PCI controller to
@param DeviceAddress The resulting map address for the bus master PCI controller to
use to access the hosts HostAddress.
@param Mapping A resulting value to pass to Unmap().
@retval EFI_SUCCESS Success to allocate aligned pages.
@retval EFI_INVALID_PARAMETER Pages or Alignment is not valid.
@retval EFI_OUT_OF_RESOURCES Do not have enough resources to allocate memory.
**/
EFI_STATUS
@@ -639,11 +639,11 @@ UsbHcAllocateAlignedPages (
// Alignment must be a power of two or zero.
//
ASSERT ((Alignment & (Alignment - 1)) == 0);
if ((Alignment & (Alignment - 1)) != 0) {
return EFI_INVALID_PARAMETER;
}
if (Pages == 0) {
return EFI_INVALID_PARAMETER;
}
@@ -657,7 +657,7 @@ UsbHcAllocateAlignedPages (
// Make sure that Pages plus EFI_SIZE_TO_PAGES (Alignment) does not overflow.
//
ASSERT (RealPages > Pages);
Status = PciIo->AllocateBuffer (
PciIo,
AllocateAnyPages,
@@ -665,7 +665,7 @@ UsbHcAllocateAlignedPages (
Pages,
&Memory,
0
);
);
if (EFI_ERROR (Status)) {
return EFI_OUT_OF_RESOURCES;
}
@@ -719,7 +719,7 @@ UsbHcAllocateAlignedPages (
Status = PciIo->FreeBuffer (PciIo, Pages, (VOID *) AlignedMemory);
return EFI_OUT_OF_RESOURCES;
}
*HostAddress = (VOID *) AlignedMemory;
return EFI_SUCCESS;
@@ -727,7 +727,7 @@ UsbHcAllocateAlignedPages (
/**
Frees memory that was allocated with UsbHcAllocateAlignedPages().
@param PciIo The PciIo that can be used to access the host controller.
@param HostAddress The system memory address to map to the PCI controller.
@param Pages The number of 4 KB pages to free.
@@ -743,9 +743,9 @@ UsbHcFreeAlignedPages (
)
{
EFI_STATUS Status;
ASSERT (Pages != 0);
Status = PciIo->Unmap (PciIo, Mapping);
ASSERT_EFI_ERROR (Status);
@@ -753,6 +753,6 @@ UsbHcFreeAlignedPages (
PciIo,
Pages,
HostAddress
);
);
ASSERT_EFI_ERROR (Status);
}

14
MdeModulePkg/Bus/Pci/XhciDxe/UsbHcMem.h
View File

@@ -2,7 +2,7 @@
This file contains the definination for host controller memory management routines.
Copyright (c) 2013, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -164,23 +164,23 @@ UsbHcGetHostAddrForPciAddr (
IN UINTN Size
);
/**
/**
Allocates pages at a specified alignment that are suitable for an EfiPciIoOperationBusMasterCommonBuffer mapping.
If Alignment is not a power of two and Alignment is not zero, then ASSERT().
@param PciIo The PciIo that can be used to access the host controller.
@param Pages The number of pages to allocate.
@param Alignment The requested alignment of the allocation. Must be a power of two.
@param HostAddress The system memory address to map to the PCI controller.
@param DeviceAddress The resulting map address for the bus master PCI controller to
@param DeviceAddress The resulting map address for the bus master PCI controller to
use to access the hosts HostAddress.
@param Mapping A resulting value to pass to Unmap().
@retval EFI_SUCCESS Success to allocate aligned pages.
@retval EFI_INVALID_PARAMETER Pages or Alignment is not valid.
@retval EFI_OUT_OF_RESOURCES Do not have enough resources to allocate memory.
**/
EFI_STATUS
@@ -192,10 +192,10 @@ UsbHcAllocateAlignedPages (
OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,
OUT VOID **Mapping
);
/**
Frees memory that was allocated with UsbHcAllocateAlignedPages().
@param PciIo The PciIo that can be used to access the host controller.
@param HostAddress The system memory address to map to the PCI controller.
@param Pages The number of pages to free.

10
MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c
View File

@@ -1,7 +1,7 @@
/** @file
The XHCI controller driver.
Copyright (c) 2011 - 2017, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2011 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -159,7 +159,7 @@ XhcReset (
EFI_TPL OldTpl;
Xhc = XHC_FROM_THIS (This);
if (Xhc->DevicePath != NULL) {
//
// Report Status Code to indicate reset happens
@@ -169,7 +169,7 @@ XhcReset (
(EFI_IO_BUS_USB | EFI_IOB_PC_RESET),
Xhc->DevicePath
);
}
}
OldTpl = gBS->RaiseTPL (XHC_TPL);
@@ -995,7 +995,7 @@ XhcControlTransfer (
// Hook Set_Config request from UsbBus as we need configure device endpoint.
//
if ((Request->Request == USB_REQ_GET_DESCRIPTOR) &&
((Request->RequestType == USB_REQUEST_TYPE (EfiUsbDataIn, USB_REQ_TYPE_STANDARD, USB_TARGET_DEVICE)) ||
((Request->RequestType == USB_REQUEST_TYPE (EfiUsbDataIn, USB_REQ_TYPE_STANDARD, USB_TARGET_DEVICE)) ||
((Request->RequestType == USB_REQUEST_TYPE (EfiUsbDataIn, USB_REQ_TYPE_CLASS, USB_TARGET_DEVICE))))) {
DescriptorType = (UINT8)(Request->Value >> 8);
if ((DescriptorType == USB_DESC_TYPE_DEVICE) && ((*DataLength == sizeof (EFI_USB_DEVICE_DESCRIPTOR)) || ((DeviceSpeed == EFI_USB_SPEED_FULL) && (*DataLength == 8)))) {
@@ -1144,7 +1144,7 @@ XhcControlTransfer (
ClearPortRequest.Length = 0;
XhcControlTransfer (
This,
This,
DeviceAddress,
DeviceSpeed,
MaximumPacketLength,

4
MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
View File

@@ -3,7 +3,7 @@
# It implements the interfaces of monitoring the status of all ports and transferring
# Control, Bulk, Interrupt and Isochronous requests to those attached usb LS/FS/HS/SS devices.
#
# Copyright (c) 2011 - 2014, Intel Corporation. All rights reserved.<BR>
# Copyright (c) 2011 - 2018, Intel Corporation. All rights reserved.<BR>
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
@@ -41,7 +41,7 @@
XhciReg.c
XhciSched.c
UsbHcMem.c
UsbHcMem.h
UsbHcMem.h
ComponentName.c
ComponentName.h
Xhci.h

4
MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.uni
View File

@@ -4,13 +4,13 @@
// It implements the interfaces of monitoring the status of all ports and transferring
// Control, Bulk, Interrupt and Isochronous requests to those attached usb LS/FS/HS/SS devices.
//
// Copyright (c) 2011 - 2014, Intel Corporation. All rights reserved.<BR>
// Copyright (c) 2011 - 2018, Intel Corporation. All rights reserved.<BR>
//
// This program and the accompanying materials
// are licensed and made available under the terms and conditions of the BSD License
// which accompanies this distribution. The full text of the license may be found at
// http://opensource.org/licenses/bsd-license.php
//
//
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
//

6
MdeModulePkg/Bus/Pci/XhciDxe/XhciDxeExtra.uni
View File

@@ -1,7 +1,7 @@
// /** @file
// XhciDxe Localized Strings and Content
//
// Copyright (c) 2013 - 2014, Intel Corporation. All rights reserved.<BR>
// Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.<BR>
//
// This program and the accompanying materials
// are licensed and made available under the terms and conditions of the BSD License
@@ -13,8 +13,8 @@
//
// **/
#string STR_PROPERTIES_MODULE_NAME
#language en-US
#string STR_PROPERTIES_MODULE_NAME
#language en-US
"XHCI DXE Driver"

40
MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c
View File

@@ -2,7 +2,7 @@
XHCI transfer scheduling routines.
Copyright (c) 2011 - 2017, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2011 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -201,7 +201,7 @@ XhcFreeUrb (
if ((Xhc == NULL) || (Urb == NULL)) {
return;
}
if (Urb->DataMap != NULL) {
Xhc->PciIo->Unmap (Xhc->PciIo, Urb->DataMap);
}
@@ -269,15 +269,15 @@ XhcCreateTransferTrb (
} else {
MapOp = EfiPciIoOperationBusMasterRead;
}
Len = Urb->DataLen;
Status = Xhc->PciIo->Map (Xhc->PciIo, MapOp, Urb->Data, &Len, &PhyAddr, &Map);
if (EFI_ERROR (Status) || (Len != Urb->DataLen)) {
DEBUG ((EFI_D_ERROR, "XhcCreateTransferTrb: Fail to map Urb->Data.\n"));
return EFI_OUT_OF_RESOURCES;
}
Urb->DataPhy = (VOID *) ((UINTN) PhyAddr);
Urb->DataMap = Map;
}
@@ -469,7 +469,7 @@ XhcInitSched (
VOID *Dcbaa;
EFI_PHYSICAL_ADDRESS DcbaaPhy;
UINT64 CmdRing;
EFI_PHYSICAL_ADDRESS CmdRingPhy;
EFI_PHYSICAL_ADDRESS CmdRingPhy;
UINTN Entries;
UINT32 MaxScratchpadBufs;
UINT64 *ScratchBuf;
@@ -520,7 +520,7 @@ XhcInitSched (
ScratchEntryMap = AllocateZeroPool (sizeof (UINTN) * MaxScratchpadBufs);
ASSERT (ScratchEntryMap != NULL);
Xhc->ScratchEntryMap = ScratchEntryMap;
//
// Allocate the buffer to record the host address for each entry
//
@@ -533,7 +533,7 @@ XhcInitSched (
Xhc->PciIo,
EFI_SIZE_TO_PAGES (MaxScratchpadBufs * sizeof (UINT64)),
Xhc->PageSize,
(VOID **) &ScratchBuf,
(VOID **) &ScratchBuf,
&ScratchPhy,
&Xhc->ScratchMap
);
@@ -659,7 +659,7 @@ XhcRecoverHaltedEndpoint (
}
Dci = XhcEndpointToDci (Urb->Ep.EpAddr, (UINT8)(Urb->Ep.Direction));
ASSERT (Dci < 32);
DEBUG ((EFI_D_INFO, "Recovery Halted Slot = %x,Dci = %x\n", SlotId, Dci));
//
@@ -721,7 +721,7 @@ XhcDequeueTrbFromEndpoint (
}
Dci = XhcEndpointToDci (Urb->Ep.EpAddr, (UINT8)(Urb->Ep.Direction));
ASSERT (Dci < 32);
DEBUG ((EFI_D_INFO, "Stop Slot = %x,Dci = %x\n", SlotId, Dci));
//
@@ -792,9 +792,9 @@ CreateEventRing (
EventRing->TrbNumber = EVENT_RING_TRB_NUMBER;
EventRing->EventRingDequeue = (TRB_TEMPLATE *) EventRing->EventRingSeg0;
EventRing->EventRingEnqueue = (TRB_TEMPLATE *) EventRing->EventRingSeg0;
DequeuePhy = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Buf, Size);
//
// Software maintains an Event Ring Consumer Cycle State (CCS) bit, initializing it to '1'
// and toggling it every time the Event Ring Dequeue Pointer wraps back to the beginning of the Event Ring.
@@ -953,7 +953,7 @@ XhcFreeSched (
{
UINT32 Index;
UINT64 *ScratchEntry;
if (Xhc->ScratchBuf != NULL) {
ScratchEntry = Xhc->ScratchEntry;
for (Index = 0; Index < Xhc->MaxScratchpadBufs; Index++) {
@@ -974,14 +974,14 @@ XhcFreeSched (
UsbHcFreeMem (Xhc->MemPool, Xhc->CmdRing.RingSeg0, sizeof (TRB_TEMPLATE) * CMD_RING_TRB_NUMBER);
Xhc->CmdRing.RingSeg0 = NULL;
}
XhcFreeEventRing (Xhc,&Xhc->EventRing);
if (Xhc->DCBAA != NULL) {
UsbHcFreeMem (Xhc->MemPool, Xhc->DCBAA, (Xhc->MaxSlotsEn + 1) * sizeof(UINT64));
Xhc->DCBAA = NULL;
}
//
// Free memory pool at last
//
@@ -1132,7 +1132,7 @@ XhcCheckUrbResult (
if ((EvtTrb->Type != TRB_TYPE_COMMAND_COMPLT_EVENT) && (EvtTrb->Type != TRB_TYPE_TRANS_EVENT)) {
continue;
}
//
// Need convert pci device address to host address
//
@@ -1149,12 +1149,12 @@ XhcCheckUrbResult (
CheckedUrb = Xhc->PendingUrb;
} else if (IsTransferRingTrb (Xhc, TRBPtr, Urb)) {
CheckedUrb = Urb;
} else if (IsAsyncIntTrb (Xhc, TRBPtr, &AsyncUrb)) {
} else if (IsAsyncIntTrb (Xhc, TRBPtr, &AsyncUrb)) {
CheckedUrb = AsyncUrb;
} else {
continue;
}
switch (EvtTrb->Completecode) {
case TRB_COMPLETION_STALL_ERROR:
CheckedUrb->Result |= EFI_USB_ERR_STALL;
@@ -1676,7 +1676,7 @@ XhcPollPortStatusChange (
Status = XhcInitializeDeviceSlot64 (Xhc, ParentRouteChart, Port, RouteChart, Speed);
}
}
}
}
return Status;
}
@@ -3144,7 +3144,7 @@ XhcSetConfigCmd64 (
if (Dci > MaxDci) {
MaxDci = Dci;
}
IfDesc = (USB_INTERFACE_DESCRIPTOR *)((UINTN)IfDesc + IfDesc->Length);
}

8
MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.h
View File

@@ -2,7 +2,7 @@
This file contains the definition for XHCI host controller schedule routines.
Copyright (c) 2011 - 2017, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2011 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -620,7 +620,7 @@ typedef struct _SLOT_CONTEXT_64 {
UINT32 RsvdZ9;
UINT32 RsvdZ10;
UINT32 RsvdZ11;
UINT32 RsvdZ12;
UINT32 RsvdZ13;
UINT32 RsvdZ14;
@@ -688,12 +688,12 @@ typedef struct _ENDPOINT_CONTEXT_64 {
UINT32 RsvdZ5;
UINT32 RsvdZ6;
UINT32 RsvdZ7;
UINT32 RsvdZ8;
UINT32 RsvdZ9;
UINT32 RsvdZ10;
UINT32 RsvdZ11;
UINT32 RsvdZ12;
UINT32 RsvdZ13;
UINT32 RsvdZ14;