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UefiCpuPkg/MpInitLib: Simplify logic in SwitchBsp

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When switch bsp, old bsp and new bsp put CR0/CR4 into stack, and put IDT
and GDT register into a structure. After they exchange their stack, they
restore these registers. This logic is now implemented by assembly code.
This patch aims to reuse (Save/Restore)VolatileRegisters function to
replace such assembly code for better code readability.

Cc: Eric Dong <eric.dong@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
This commit is contained in:
Liu, Zhiguang
2022-08-26 15:04:46 +08:00
committed by mergify[bot]
parent 76ec17526b
commit d1abb876f4
4 changed files with 56 additions and 63 deletions
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43
UefiCpuPkg/Library/MpInitLib/MpLib.h
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@@ -68,14 +68,31 @@ typedef struct {
UINTN Size;
} MICROCODE_PATCH_INFO;
//
// CPU volatile registers around INIT-SIPI-SIPI
//
typedef struct {
UINTN Cr0;
UINTN Cr3;
UINTN Cr4;
UINTN Dr0;
UINTN Dr1;
UINTN Dr2;
UINTN Dr3;
UINTN Dr6;
UINTN Dr7;
IA32_DESCRIPTOR Gdtr;
IA32_DESCRIPTOR Idtr;
UINT16 Tr;
} CPU_VOLATILE_REGISTERS;
//
// CPU exchange information for switch BSP
//
typedef struct {
UINT8 State; // offset 0
UINTN StackPointer; // offset 4 / 8
IA32_DESCRIPTOR Gdtr; // offset 8 / 16
IA32_DESCRIPTOR Idtr; // offset 14 / 26
UINT8 State; // offset 0
UINTN StackPointer; // offset 4 / 8
CPU_VOLATILE_REGISTERS VolatileRegisters; // offset 8 / 16
} CPU_EXCHANGE_ROLE_INFO;
//
@@ -112,24 +129,6 @@ typedef enum {
CpuStateDisabled
} CPU_STATE;
//
// CPU volatile registers around INIT-SIPI-SIPI
//
typedef struct {
UINTN Cr0;
UINTN Cr3;
UINTN Cr4;
UINTN Dr0;
UINTN Dr1;
UINTN Dr2;
UINTN Dr3;
UINTN Dr6;
UINTN Dr7;
IA32_DESCRIPTOR Gdtr;
IA32_DESCRIPTOR Idtr;
UINT16 Tr;
} CPU_VOLATILE_REGISTERS;
//
// AP related data
//