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MdePkg: Replace Opcode with the corresponding instructions.

Browse Source 
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3790

Replace Opcode with the corresponding instructions.
The code changes have been verified with CompareBuild.py tool, which
can be used to compare the results of two different EDK II builds to
determine if they generate the same binaries.
(tool link: https://github.com/mdkinney/edk2/tree/sandbox/CompareBuild)

Signed-off-by: Jason Lou <yun.lou@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
This commit is contained in:
Jason
2022-01-10 21:46:27 +08:00
committed by mergify[bot]
parent 84338c0d49
commit d3febfd9ad
42 changed files with 116 additions and 175 deletions
Download Patch File Download Diff File Expand all files Collapse all files

20
MdePkg/Library/BaseLib/Ia32/EnablePaging64.nasm
View File

@@ -1,6 +1,6 @@
;------------------------------------------------------------------------------
;
; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR>
; SPDX-License-Identifier: BSD-2-Clause-Patent
;
; Module Name:
@@ -44,16 +44,12 @@ ASM_PFX(InternalX86EnablePaging64):
mov cr0, eax ; enable paging
retf ; topmost 2 dwords hold the address
.0:
DB 0x67, 0x48 ; 32-bit address size, 64-bit operand size
mov ebx, [esp] ; mov rbx, [esp]
DB 0x67, 0x48
mov ecx, [esp + 8] ; mov rcx, [esp + 8]
DB 0x67, 0x48
mov edx, [esp + 0x10] ; mov rdx, [esp + 10h]
DB 0x67, 0x48
mov esp, [esp + 0x18] ; mov rsp, [esp + 18h]
DB 0x48
add esp, -0x20 ; add rsp, -20h
call ebx ; call rbx
BITS 64
mov rbx, [esp]
mov rcx, [esp + 8]
mov rdx, [esp + 0x10]
mov rsp, [esp + 0x18]
add rsp, -0x20
call rbx
hlt ; no one should get here

6
MdePkg/Library/BaseLib/Ia32/LongJump.nasm
View File

@@ -1,6 +1,6 @@
;------------------------------------------------------------------------------
;
; Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>
; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR>
; SPDX-License-Identifier: BSD-2-Clause-Patent
;
; Module Name:
@@ -39,12 +39,12 @@ ASM_PFX(InternalLongJump):
mov edx, [esp + 4] ; edx = JumpBuffer
mov edx, [edx + 24] ; edx = target SSP
READSSP_EAX
rdsspd eax
sub edx, eax ; edx = delta
mov eax, edx ; eax = delta
shr eax, 2 ; eax = delta/sizeof(UINT32)
INCSSP_EAX
incsspd eax
CetDone:

4
MdePkg/Library/BaseLib/Ia32/Monitor.nasm
View File

@@ -1,6 +1,6 @@
;------------------------------------------------------------------------------
;
; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR>
; SPDX-License-Identifier: BSD-2-Clause-Patent
;
; Module Name:
@@ -31,6 +31,6 @@ ASM_PFX(AsmMonitor):
mov eax, [esp + 4]
mov ecx, [esp + 8]
mov edx, [esp + 12]
DB 0xf, 1, 0xc8 ; monitor
monitor
ret

4
MdePkg/Library/BaseLib/Ia32/Mwait.nasm
View File

@@ -1,6 +1,6 @@
;------------------------------------------------------------------------------
;
; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR>
; SPDX-License-Identifier: BSD-2-Clause-Patent
;
; Module Name:
@@ -29,6 +29,6 @@ global ASM_PFX(AsmMwait)
ASM_PFX(AsmMwait):
mov eax, [esp + 4]
mov ecx, [esp + 8]
DB 0xf, 1, 0xc9 ; mwait
mwait
ret

13
MdePkg/Library/BaseLib/Ia32/RdRand.nasm
View File

@@ -1,6 +1,6 @@
;------------------------------------------------------------------------------
;
; Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>
; Copyright (c) 2015 - 2022, Intel Corporation. All rights reserved.<BR>
; SPDX-License-Identifier: BSD-2-Clause-Patent
;
; Module Name:
@@ -25,9 +25,8 @@ SECTION .text
;------------------------------------------------------------------------------
global ASM_PFX(InternalX86RdRand16)
ASM_PFX(InternalX86RdRand16):
; rdrand ax ; generate a 16 bit RN into ax
rdrand eax ; generate a 16 bit RN into ax
; CF=1 if RN generated ok, otherwise CF=0
db 0xf, 0xc7, 0xf0 ; rdrand r16: "0f c7 /6 ModRM:r/m(w)"
jc rn16_ok ; jmp if CF=1
xor eax, eax ; reg=0 if CF=0
ret ; return with failure status
@@ -45,9 +44,8 @@ rn16_ok:
;------------------------------------------------------------------------------
global ASM_PFX(InternalX86RdRand32)
ASM_PFX(InternalX86RdRand32):
; rdrand eax ; generate a 32 bit RN into eax
rdrand eax ; generate a 32 bit RN into eax
; CF=1 if RN generated ok, otherwise CF=0
db 0xf, 0xc7, 0xf0 ; rdrand r32: "0f c7 /6 ModRM:r/m(w)"
jc rn32_ok ; jmp if CF=1
xor eax, eax ; reg=0 if CF=0
ret ; return with failure status
@@ -65,14 +63,13 @@ rn32_ok:
;------------------------------------------------------------------------------
global ASM_PFX(InternalX86RdRand64)
ASM_PFX(InternalX86RdRand64):
; rdrand eax ; generate a 32 bit RN into eax
rdrand eax ; generate a 32 bit RN into eax
; CF=1 if RN generated ok, otherwise CF=0
db 0xf, 0xc7, 0xf0 ; rdrand r32: "0f c7 /6 ModRM:r/m(w)"
jnc rn64_ret ; jmp if CF=0
mov edx, dword [esp + 4]
mov [edx], eax
db 0xf, 0xc7, 0xf0 ; generate another 32 bit RN
rdrand eax ; generate another 32 bit RN
jnc rn64_ret ; jmp if CF=0
mov [edx + 4], eax

6
MdePkg/Library/BaseLib/Ia32/ReadDr4.nasm
View File

@@ -1,6 +1,6 @@
;------------------------------------------------------------------------------
;
; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR>
; SPDX-License-Identifier: BSD-2-Clause-Patent
;
; Module Name:
@@ -31,8 +31,8 @@ ASM_PFX(AsmReadDr4):
; this register will cause a #UD exception.
;
; MS assembler doesn't support this instruction since no one would use it
; under normal circustances. Here opcode is used.
; under normal circustances.
;
DB 0xf, 0x21, 0xe0
mov eax, dr4
ret

6
MdePkg/Library/BaseLib/Ia32/ReadDr5.nasm
View File

@@ -1,6 +1,6 @@
;------------------------------------------------------------------------------
;
; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR>
; SPDX-License-Identifier: BSD-2-Clause-Patent
;
; Module Name:
@@ -31,8 +31,8 @@ ASM_PFX(AsmReadDr5):
; this register will cause a #UD exception.
;
; MS assembler doesn't support this instruction since no one would use it
; under normal circustances. Here opcode is used.
; under normal circustances.
;
DB 0xf, 0x21, 0xe8
mov eax, dr5
ret

6
MdePkg/Library/BaseLib/Ia32/SetJump.nasm
View File

@@ -1,6 +1,6 @@
;------------------------------------------------------------------------------
;
; Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>
; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR>
; SPDX-License-Identifier: BSD-2-Clause-Patent
;
; Module Name:
@@ -46,8 +46,8 @@ ASM_PFX(SetJump):
jnc CetDone
mov eax, 1
INCSSP_EAX ; to read original SSP
READSSP_EAX
incsspd eax ; to read original SSP
rdsspd eax
mov [edx + 0x24], eax ; save SSP
CetDone:

6
MdePkg/Library/BaseLib/Ia32/WriteDr4.nasm
View File

@@ -1,6 +1,6 @@
;------------------------------------------------------------------------------
;
; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR>
; SPDX-License-Identifier: BSD-2-Clause-Patent
;
; Module Name:
@@ -32,8 +32,8 @@ ASM_PFX(AsmWriteDr4):
; this register will cause a #UD exception.
;
; MS assembler doesn't support this instruction since no one would use it
; under normal circustances. Here opcode is used.
; under normal circustances.
;
DB 0xf, 0x23, 0xe0
mov dr4, eax
ret

6
MdePkg/Library/BaseLib/Ia32/WriteDr5.nasm
View File

@@ -1,6 +1,6 @@
;------------------------------------------------------------------------------
;
; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR>
; SPDX-License-Identifier: BSD-2-Clause-Patent
;
; Module Name:
@@ -32,8 +32,8 @@ ASM_PFX(AsmWriteDr5):
; this register will cause a #UD exception.
;
; MS assembler doesn't support this instruction since no one would use it
; under normal circustances. Here opcode is used.
; under normal circustances.
;
DB 0xf, 0x23, 0xe8
mov dr5, eax
ret