Fix bugs in the PCI bus driver to support SR-IOV.
1. Expand the type of Offset in the _PCI_BAR structure from UINT8 to UINT16, because a VF BAR’s offset may be >= 0x100; 2. Enable ARI Capable Hierarchy for SR-IOV devices at earlier time because FirstVFOffset and VFStride of a SR-IOV device may change after its ARI Capable Hierarchy is set; 3. Change type of PcdSrIovSupport, PcdAriSupport, PcdMrIovSupport from FeatureFlag to [FixAtBuild, PcdDynamics], which allows SR-IOV/MR-IOV/ARI feature can be turn on/off dynamically, typically via a setup option. 4. Change PCI bus scan algorithm in PciScanBus() to prevent the case where some ARI extended functions may be skipped in the scan loop. git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@10644 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
@@ -1,7 +1,7 @@
|
||||
/** @file
|
||||
Supporting functions implementaion for PCI devices management.
|
||||
|
||||
Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
|
||||
Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
|
||||
This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
@@ -215,10 +215,6 @@ RegisterPciDevice (
|
||||
EFI_PCI_IO_PROTOCOL *PciIo;
|
||||
UINT8 Data8;
|
||||
BOOLEAN HasEfiImage;
|
||||
PCI_IO_DEVICE *ParrentPciIoDevice;
|
||||
EFI_PCI_IO_PROTOCOL *ParrentPciIo;
|
||||
UINT16 Data16;
|
||||
UINT32 Data32;
|
||||
|
||||
//
|
||||
// Install the pciio protocol, device path protocol
|
||||
@@ -255,35 +251,7 @@ RegisterPciDevice (
|
||||
PciIo = &(PciIoDevice->PciIo);
|
||||
Data8 = PCI_INT_LINE_UNKNOWN;
|
||||
PciIo->Pci.Write (PciIo, EfiPciIoWidthUint8, 0x3C, 1, &Data8);
|
||||
|
||||
//
|
||||
// PCI-IOV programming
|
||||
//
|
||||
if (((FeaturePcdGet(PcdAriSupport) & EFI_PCI_IOV_POLICY_ARI) != 0) && (PciIoDevice->AriCapabilityOffset != 0) && ((FeaturePcdGet(PcdSrIovSupport) & EFI_PCI_IOV_POLICY_SRIOV) != 0) &&
|
||||
(PciIoDevice->SrIovCapabilityOffset != 0)) {
|
||||
//
|
||||
// Check its parrent ARI forwarding capability
|
||||
//
|
||||
ParrentPciIoDevice = PciIoDevice->Parent;
|
||||
ParrentPciIo = &(ParrentPciIoDevice->PciIo);
|
||||
ParrentPciIo->Pci.Read (PciIo, EfiPciIoWidthUint32, ParrentPciIoDevice->PciExpressCapabilityOffset + EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_OFFSET, 1, &Data32);
|
||||
if ((Data32 & EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_ARI_FORWARDING) != 0) {
|
||||
//
|
||||
// ARI forward support in bridge, so enable it.
|
||||
//
|
||||
ParrentPciIo->Pci.Read (PciIo, EfiPciIoWidthUint32, ParrentPciIoDevice->PciExpressCapabilityOffset + EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_OFFSET, 1, &Data32);
|
||||
Data32 |= EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_ARI_FORWARDING;
|
||||
ParrentPciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, ParrentPciIoDevice->PciExpressCapabilityOffset + EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_OFFSET, 1, &Data32);
|
||||
|
||||
//
|
||||
// Set ARI Capable Hierarchy for device
|
||||
//
|
||||
PciIo->Pci.Read (PciIo, EfiPciIoWidthUint16, PciIoDevice->SrIovCapabilityOffset + EFI_PCIE_CAPABILITY_ID_SRIOV_CONTROL, 1, &Data16);
|
||||
Data16 |= EFI_PCIE_CAPABILITY_ID_SRIOV_CONTROL_ARI_HIERARCHY;
|
||||
PciIo->Pci.Write (PciIo, EfiPciIoWidthUint16, PciIoDevice->SrIovCapabilityOffset + EFI_PCIE_CAPABILITY_ID_SRIOV_CONTROL, 1, &Data16);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
//
|
||||
// Process OpRom
|
||||
//
|
||||
|
Reference in New Issue
Block a user