Fix bugs in the PCI bus driver to support SR-IOV.
1. Expand the type of Offset in the _PCI_BAR structure from UINT8 to UINT16, because a VF BAR’s offset may be >= 0x100; 2. Enable ARI Capable Hierarchy for SR-IOV devices at earlier time because FirstVFOffset and VFStride of a SR-IOV device may change after its ARI Capable Hierarchy is set; 3. Change type of PcdSrIovSupport, PcdAriSupport, PcdMrIovSupport from FeatureFlag to [FixAtBuild, PcdDynamics], which allows SR-IOV/MR-IOV/ARI feature can be turn on/off dynamically, typically via a setup option. 4. Change PCI bus scan algorithm in PciScanBus() to prevent the case where some ARI extended functions may be skipped in the scan loop. git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@10644 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
@@ -328,11 +328,9 @@ GatherDeviceInfo (
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UINTN Offset;
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UINTN BarIndex;
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PCI_IO_DEVICE *PciIoDevice;
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EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;
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PciRootBridgeIo = Bridge->PciRootBridgeIo;
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PciIoDevice = CreatePciIoDevice (
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PciRootBridgeIo,
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Bridge,
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Pci,
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Bus,
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Device,
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@@ -370,7 +368,7 @@ GatherDeviceInfo (
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//
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// Parse the SR-IOV VF bars
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//
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if ((PciIoDevice->SrIovCapabilityOffset != 0) && ((FeaturePcdGet(PcdSrIovSupport)& EFI_PCI_IOV_POLICY_SRIOV) != 0)) {
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if (PcdGetBool (PcdSrIovSupport) && PciIoDevice->SrIovCapabilityOffset != 0) {
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for (Offset = PciIoDevice->SrIovCapabilityOffset + EFI_PCIE_CAPABILITY_ID_SRIOV_BAR0, BarIndex = 0;
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Offset <= PciIoDevice->SrIovCapabilityOffset + EFI_PCIE_CAPABILITY_ID_SRIOV_BAR5;
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BarIndex++) {
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@@ -403,16 +401,14 @@ GatherPpbInfo (
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IN UINT8 Func
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)
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{
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EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;
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PCI_IO_DEVICE *PciIoDevice;
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EFI_STATUS Status;
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UINT8 Value;
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EFI_PCI_IO_PROTOCOL *PciIo;
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UINT8 Temp;
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PciRootBridgeIo = Bridge->PciRootBridgeIo;
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PciIoDevice = CreatePciIoDevice (
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PciRootBridgeIo,
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Bridge,
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Pci,
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Bus,
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Device,
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@@ -558,12 +554,10 @@ GatherP2CInfo (
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IN UINT8 Func
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)
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{
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EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;
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PCI_IO_DEVICE *PciIoDevice;
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PciRootBridgeIo = Bridge->PciRootBridgeIo;
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PciIoDevice = CreatePciIoDevice (
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PciRootBridgeIo,
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Bridge,
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Pci,
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Bus,
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Device,
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@@ -1415,11 +1409,11 @@ PciIovParseVfBar (
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//
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// Scan all the BARs anyway
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//
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PciIoDevice->VfPciBar[BarIndex].Offset = (UINT8) Offset;
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PciIoDevice->VfPciBar[BarIndex].Offset = (UINT16) Offset;
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return Offset + 4;
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}
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PciIoDevice->VfPciBar[BarIndex].Offset = (UINT8) Offset;
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PciIoDevice->VfPciBar[BarIndex].Offset = (UINT16) Offset;
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if ((Value & 0x01) != 0) {
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//
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// Device I/Os. Impossible
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@@ -1905,14 +1899,14 @@ InitializeP2C (
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**/
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PCI_IO_DEVICE *
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CreatePciIoDevice (
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IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo,
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IN PCI_IO_DEVICE *Bridge,
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IN PCI_TYPE00 *Pci,
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IN UINT8 Bus,
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IN UINT8 Device,
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IN UINT8 Func
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)
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{
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PCI_IO_DEVICE *PciIoDevice;
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PCI_IO_DEVICE *PciIoDevice;
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EFI_PCI_IO_PROTOCOL *PciIo;
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EFI_STATUS Status;
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@@ -1923,7 +1917,7 @@ CreatePciIoDevice (
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PciIoDevice->Signature = PCI_IO_DEVICE_SIGNATURE;
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PciIoDevice->Handle = NULL;
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PciIoDevice->PciRootBridgeIo = PciRootBridgeIo;
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PciIoDevice->PciRootBridgeIo = Bridge->PciRootBridgeIo;
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PciIoDevice->DevicePath = NULL;
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PciIoDevice->BusNumber = Bus;
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PciIoDevice->DeviceNumber = Device;
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@@ -1968,147 +1962,262 @@ CreatePciIoDevice (
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PciIoDevice->IsPciExp = TRUE;
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}
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//
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// Initialize for PCI IOV
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//
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if (PcdGetBool (PcdAriSupport)) {
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//
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// Check if the device is an ARI device.
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//
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Status = LocatePciExpressCapabilityRegBlock (
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PciIoDevice,
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EFI_PCIE_CAPABILITY_ID_ARI,
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&PciIoDevice->AriCapabilityOffset,
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NULL
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);
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if (!EFI_ERROR (Status)) {
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//
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// We need to enable ARI feature before calculate BusReservation,
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// because FirstVFOffset and VFStride may change after that.
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//
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EFI_PCI_IO_PROTOCOL *ParentPciIo;
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UINT32 Data32;
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//
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// Check ARI for function 0 only
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//
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Status = LocatePciExpressCapabilityRegBlock (
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PciIoDevice,
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EFI_PCIE_CAPABILITY_ID_ARI,
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&PciIoDevice->AriCapabilityOffset,
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NULL
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);
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if (!EFI_ERROR (Status)) {
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DEBUG ((
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EFI_D_INFO,
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"PCI-IOV B%x.D%x.F%x - ARI Cap offset - 0x%x\n",
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(UINTN)Bus,
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(UINTN)Device,
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(UINTN)Func,
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(UINTN)PciIoDevice->AriCapabilityOffset
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));
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}
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//
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// Check if its parent supports ARI forwarding.
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//
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ParentPciIo = &Bridge->PciIo;
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ParentPciIo->Pci.Read (
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ParentPciIo,
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EfiPciIoWidthUint32,
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Bridge->PciExpressCapabilityOffset + EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_OFFSET,
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1,
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&Data32
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);
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if ((Data32 & EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_ARI_FORWARDING) != 0) {
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//
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// ARI forward support in bridge, so enable it.
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//
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ParentPciIo->Pci.Read (
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ParentPciIo,
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EfiPciIoWidthUint32,
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Bridge->PciExpressCapabilityOffset + EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_OFFSET,
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1,
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&Data32
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);
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if ((Data32 & EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_ARI_FORWARDING) == 0) {
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Data32 |= EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_ARI_FORWARDING;
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ParentPciIo->Pci.Write (
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ParentPciIo,
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EfiPciIoWidthUint32,
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Bridge->PciExpressCapabilityOffset + EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_OFFSET,
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1,
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&Data32
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);
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DEBUG ((
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EFI_D_INFO,
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"PCI B%x.D%x.F%x - ARI forwarding enabled\n",
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(UINTN)Bridge->BusNumber,
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(UINTN)Bridge->DeviceNumber,
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(UINTN)Bridge->FunctionNumber
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));
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}
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}
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Status = LocatePciExpressCapabilityRegBlock (
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PciIoDevice,
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EFI_PCIE_CAPABILITY_ID_SRIOV,
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&PciIoDevice->SrIovCapabilityOffset,
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NULL
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);
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if (!EFI_ERROR (Status)) {
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DEBUG ((
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EFI_D_INFO,
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"PCI-IOV B%x.D%x.F%x - SRIOV Cap offset - 0x%x\n",
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(UINTN)Bus,
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(UINTN)Device,
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(UINTN)Func,
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(UINTN)PciIoDevice->SrIovCapabilityOffset
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));
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}
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Status = LocatePciExpressCapabilityRegBlock (
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PciIoDevice,
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EFI_PCIE_CAPABILITY_ID_MRIOV,
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&PciIoDevice->MrIovCapabilityOffset,
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NULL
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);
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if (!EFI_ERROR (Status)) {
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DEBUG ((
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EFI_D_INFO,
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"PCI-IOV B%x.D%x.F%x - MRIOV Cap offset - 0x%x\n",
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(UINTN)Bus,
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(UINTN)Device,
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(UINTN)Func,
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(UINTN)PciIoDevice->MrIovCapabilityOffset
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));
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DEBUG ((
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EFI_D_INFO,
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"PCI ARI B%x.D%x.F%x - ARI Cap offset - 0x%x\n",
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(UINTN)Bus,
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(UINTN)Device,
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(UINTN)Func,
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(UINTN)PciIoDevice->AriCapabilityOffset
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));
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}
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}
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//
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// Calculate SystemPageSize
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// Initialization for SR-IOV
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//
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if ((PciIoDevice->SrIovCapabilityOffset != 0) && ((FeaturePcdGet(PcdSrIovSupport)& EFI_PCI_IOV_POLICY_SRIOV) != 0)) {
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PciIo->Pci.Read (
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PciIo,
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EfiPciIoWidthUint32,
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PciIoDevice->SrIovCapabilityOffset + EFI_PCIE_CAPABILITY_ID_SRIOV_SUPPORTED_PAGE_SIZE,
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1,
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&PciIoDevice->SystemPageSize
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);
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DEBUG ((EFI_D_INFO, "PCI-IOV B%x.D%x.F%x - SupportedPageSize - 0x%x\n", (UINTN)Bus, (UINTN)Device, (UINTN)Func, PciIoDevice->SystemPageSize));
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if (PcdGetBool (PcdSrIovSupport)) {
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Status = LocatePciExpressCapabilityRegBlock (
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PciIoDevice,
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EFI_PCIE_CAPABILITY_ID_SRIOV,
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&PciIoDevice->SrIovCapabilityOffset,
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NULL
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);
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if (!EFI_ERROR (Status)) {
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UINT16 VFStride;
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UINT16 FirstVFOffset;
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UINT16 Data16;
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UINT32 PFRid;
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UINT32 LastVF;
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PciIoDevice->SystemPageSize = (PcdGet32 (PcdSrIovSystemPageSize) & PciIoDevice->SystemPageSize);
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ASSERT (PciIoDevice->SystemPageSize != 0);
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//
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// If the SR-IOV device is an ARI device, then Set ARI Capable Hierarchy for the device.
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//
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if (PcdGetBool (PcdAriSupport) && PciIoDevice->AriCapabilityOffset != 0) {
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PciIo->Pci.Read (
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PciIo,
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EfiPciIoWidthUint16,
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PciIoDevice->SrIovCapabilityOffset + EFI_PCIE_CAPABILITY_ID_SRIOV_CONTROL,
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1,
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&Data16
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);
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Data16 |= EFI_PCIE_CAPABILITY_ID_SRIOV_CONTROL_ARI_HIERARCHY;
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PciIo->Pci.Write (
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PciIo,
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EfiPciIoWidthUint16,
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PciIoDevice->SrIovCapabilityOffset + EFI_PCIE_CAPABILITY_ID_SRIOV_CONTROL,
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1,
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&Data16
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);
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}
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PciIo->Pci.Write (
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PciIo,
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EfiPciIoWidthUint32,
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PciIoDevice->SrIovCapabilityOffset + EFI_PCIE_CAPABILITY_ID_SRIOV_SYSTEM_PAGE_SIZE,
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1,
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&PciIoDevice->SystemPageSize
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);
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DEBUG ((EFI_D_INFO, "PCI-IOV B%x.D%x.F%x - SystemPageSize - 0x%x\n", (UINTN)Bus, (UINTN)Device, (UINTN)Func, PciIoDevice->SystemPageSize));
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//
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// Adjust SystemPageSize for Alignment usage later
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//
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PciIoDevice->SystemPageSize <<= 12;
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//
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// Calculate SystemPageSize
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//
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PciIo->Pci.Read (
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PciIo,
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EfiPciIoWidthUint32,
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PciIoDevice->SrIovCapabilityOffset + EFI_PCIE_CAPABILITY_ID_SRIOV_SUPPORTED_PAGE_SIZE,
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1,
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&PciIoDevice->SystemPageSize
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);
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DEBUG ((
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EFI_D_INFO,
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"PCI SR-IOV B%x.D%x.F%x - SupportedPageSize - 0x%x\n",
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(UINTN)Bus,
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(UINTN)Device,
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(UINTN)Func,
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PciIoDevice->SystemPageSize
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));
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PciIoDevice->SystemPageSize = (PcdGet32 (PcdSrIovSystemPageSize) & PciIoDevice->SystemPageSize);
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ASSERT (PciIoDevice->SystemPageSize != 0);
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PciIo->Pci.Write (
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PciIo,
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EfiPciIoWidthUint32,
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PciIoDevice->SrIovCapabilityOffset + EFI_PCIE_CAPABILITY_ID_SRIOV_SYSTEM_PAGE_SIZE,
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1,
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&PciIoDevice->SystemPageSize
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);
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DEBUG ((
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EFI_D_INFO,
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"PCI SR-IOV B%x.D%x.F%x - SystemPageSize - 0x%x\n",
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(UINTN)Bus,
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(UINTN)Device,
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(UINTN)Func,
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PciIoDevice->SystemPageSize
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));
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//
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// Adjust SystemPageSize for Alignment usage later
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//
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PciIoDevice->SystemPageSize <<= 12;
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//
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// Calculate BusReservation for PCI IOV
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//
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//
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// Read First FirstVFOffset, InitialVFs, and VFStride
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//
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PciIo->Pci.Read (
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PciIo,
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EfiPciIoWidthUint16,
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PciIoDevice->SrIovCapabilityOffset + EFI_PCIE_CAPABILITY_ID_SRIOV_FIRSTVF,
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1,
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&FirstVFOffset
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);
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DEBUG ((
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EFI_D_INFO,
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"PCI SR-IOV B%x.D%x.F%x - FirstVFOffset - 0x%x\n",
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(UINTN)Bus,
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(UINTN)Device,
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(UINTN)Func,
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(UINTN)FirstVFOffset
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));
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PciIo->Pci.Read (
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PciIo,
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EfiPciIoWidthUint16,
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PciIoDevice->SrIovCapabilityOffset + EFI_PCIE_CAPABILITY_ID_SRIOV_INITIALVFS,
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1,
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&PciIoDevice->InitialVFs
|
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);
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DEBUG ((
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EFI_D_INFO,
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"PCI SR-IOV B%x.D%x.F%x - InitialVFs - 0x%x\n",
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(UINTN)Bus,
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(UINTN)Device,
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(UINTN)Func,
|
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(UINTN)PciIoDevice->InitialVFs
|
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));
|
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|
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PciIo->Pci.Read (
|
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PciIo,
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EfiPciIoWidthUint16,
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PciIoDevice->SrIovCapabilityOffset + EFI_PCIE_CAPABILITY_ID_SRIOV_VFSTRIDE,
|
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1,
|
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&VFStride
|
||||
);
|
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DEBUG ((
|
||||
EFI_D_INFO,
|
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"PCI SR-IOV B%x.D%x.F%x - VFStride - 0x%x\n",
|
||||
(UINTN)Bus,
|
||||
(UINTN)Device,
|
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(UINTN)Func,
|
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(UINTN)VFStride
|
||||
));
|
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|
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//
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// Calculate LastVF
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||||
//
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||||
PFRid = EFI_PCI_RID(Bus, Device, Func);
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LastVF = PFRid + FirstVFOffset + (PciIoDevice->InitialVFs - 1) * VFStride;
|
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|
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//
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// Calculate ReservedBusNum for this PF
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||||
//
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||||
PciIoDevice->ReservedBusNum = (UINT16)(EFI_PCI_BUS_OF_RID (LastVF) - Bus + 1);
|
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DEBUG ((
|
||||
EFI_D_INFO,
|
||||
"PCI SR-IOV B%x.D%x.F%x - reserved bus number - 0x%x\n",
|
||||
(UINTN)Bus,
|
||||
(UINTN)Device,
|
||||
(UINTN)Func,
|
||||
(UINTN)PciIoDevice->ReservedBusNum
|
||||
));
|
||||
|
||||
DEBUG ((
|
||||
EFI_D_INFO,
|
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"PCI SR-IOV B%x.D%x.F%x - SRIOV Cap offset - 0x%x\n",
|
||||
(UINTN)Bus,
|
||||
(UINTN)Device,
|
||||
(UINTN)Func,
|
||||
(UINTN)PciIoDevice->SrIovCapabilityOffset
|
||||
));
|
||||
}
|
||||
}
|
||||
|
||||
// Calculate BusReservation for PCI IOV
|
||||
//
|
||||
if ((PciIoDevice->SrIovCapabilityOffset != 0) && ((FeaturePcdGet(PcdSrIovSupport)& EFI_PCI_IOV_POLICY_SRIOV) != 0)) {
|
||||
UINT16 VFStride;
|
||||
UINT16 FirstVFOffset;
|
||||
UINT32 PFRid;
|
||||
UINT32 LastVF;
|
||||
|
||||
//
|
||||
// Read First FirstVFOffset, InitialVFs, and VFStride
|
||||
//
|
||||
PciIo->Pci.Read (
|
||||
PciIo,
|
||||
EfiPciIoWidthUint16,
|
||||
PciIoDevice->SrIovCapabilityOffset + EFI_PCIE_CAPABILITY_ID_SRIOV_FIRSTVF,
|
||||
1,
|
||||
&FirstVFOffset
|
||||
);
|
||||
DEBUG ((EFI_D_INFO, "PCI-IOV B%x.D%x.F%x - FirstVFOffset - 0x%x\n", (UINTN)Bus, (UINTN)Device, (UINTN)Func, (UINTN)FirstVFOffset));
|
||||
|
||||
PciIo->Pci.Read (
|
||||
PciIo,
|
||||
EfiPciIoWidthUint16,
|
||||
PciIoDevice->SrIovCapabilityOffset + EFI_PCIE_CAPABILITY_ID_SRIOV_INITIALVFS,
|
||||
1,
|
||||
&PciIoDevice->InitialVFs
|
||||
);
|
||||
DEBUG ((EFI_D_INFO, "PCI-IOV B%x.D%x.F%x - InitialVFs - 0x%x\n", (UINTN)Bus, (UINTN)Device, (UINTN)Func, (UINTN)PciIoDevice->InitialVFs));
|
||||
|
||||
PciIo->Pci.Read (
|
||||
PciIo,
|
||||
EfiPciIoWidthUint16,
|
||||
PciIoDevice->SrIovCapabilityOffset + EFI_PCIE_CAPABILITY_ID_SRIOV_VFSTRIDE,
|
||||
1,
|
||||
&VFStride
|
||||
);
|
||||
DEBUG ((EFI_D_INFO, "PCI-IOV B%x.D%x.F%x - VFStride - 0x%x\n", (UINTN)Bus, (UINTN)Device, (UINTN)Func, (UINTN)VFStride));
|
||||
|
||||
//
|
||||
// Calculate LastVF
|
||||
//
|
||||
PFRid = EFI_PCI_RID(Bus, Device, Func);
|
||||
LastVF = PFRid + FirstVFOffset + (PciIoDevice->InitialVFs - 1) * VFStride;
|
||||
|
||||
//
|
||||
// Calculate ReservedBusNum for this PF
|
||||
//
|
||||
PciIoDevice->ReservedBusNum = (UINT16)(EFI_PCI_BUS_OF_RID (LastVF) - Bus + 1);
|
||||
DEBUG ((EFI_D_INFO, "PCI-IOV B%x.D%x.F%x - reserved bus number - 0x%x\n", (UINTN)Bus, (UINTN)Device, (UINTN)Func, (UINTN)PciIoDevice->ReservedBusNum));
|
||||
if (PcdGetBool (PcdMrIovSupport)) {
|
||||
Status = LocatePciExpressCapabilityRegBlock (
|
||||
PciIoDevice,
|
||||
EFI_PCIE_CAPABILITY_ID_MRIOV,
|
||||
&PciIoDevice->MrIovCapabilityOffset,
|
||||
NULL
|
||||
);
|
||||
if (!EFI_ERROR (Status)) {
|
||||
DEBUG ((
|
||||
EFI_D_INFO,
|
||||
"PCI MR-IOV B%x.D%x.F%x - MRIOV Cap offset - 0x%x\n",
|
||||
(UINTN)Bus,
|
||||
(UINTN)Device,
|
||||
(UINTN)Func,
|
||||
(UINTN)PciIoDevice->MrIovCapabilityOffset
|
||||
));
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
//
|
||||
// Initialize the reserved resource list
|
||||
//
|
||||
|
Reference in New Issue
Block a user