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Update IntelFspPkg according to FSP1.1.

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Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: "Yao, Jiewen" <jiewen.yao@intel.com>
Reviewed-by: "Rangarajan, Ravi P" <ravi.p.rangarajan@intel.com>


git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16825 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
Yao, Jiewen
2015-02-11 02:57:40 +00:00
committed by jyao1
parent 6cffee0cb0
commit d5fb1edfb1
23 changed files with 908 additions and 501 deletions
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365
IntelFspPkg/FspSecCore/Ia32/FspApiEntry.asm
View File

@@ -1,6 +1,7 @@
;------------------------------------------------------------------------------
;; @file
; Provide FSP API entry points.
;
; Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
; Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
; This program and the accompanying materials
; are licensed and made available under the terms and conditions of the BSD License
; which accompanies this distribution. The full text of the license may be found at
@@ -8,12 +9,7 @@
;
; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
;
; Abstract:
;
; Provide FSP API entry points.
;
;------------------------------------------------------------------------------
;;
.586p
.model flat,C
@@ -29,11 +25,12 @@ INCLUDE UcodeLoad.inc
EXTERN PcdGet32(PcdTemporaryRamBase):DWORD
EXTERN PcdGet32(PcdTemporaryRamSize):DWORD
EXTERN PcdGet32(PcdFspTemporaryRamSize):DWORD
EXTERN PcdGet32(PcdFspAreaSize):DWORD
;
; Following functions will be provided in C
;
EXTERN FspImageSizeOffset:DWORD
EXTERN SecStartup:PROC
EXTERN FspApiCallingCheck:PROC
@@ -42,11 +39,12 @@ EXTERN FspApiCallingCheck:PROC
;
EXTERN GetFspBaseAddress:PROC
EXTERN GetBootFirmwareVolumeOffset:PROC
EXTERN PlatformTempRamInit:PROC
EXTERN Pei2LoaderSwitchStack:PROC
EXTERN FspSelfCheck(FspSelfCheckDflt):PROC
EXTERN PlatformBasicInit(PlatformBasicInitDflt):PROC
EXTERN LoadUcode(LoadUcodeDflt):PROC
EXTERN SecPlatformInit:PROC
EXTERN SecCarInit:PROC
;
; Define the data length that we saved on the stack top
@@ -55,6 +53,35 @@ DATA_LEN_OF_PER0 EQU 18h
DATA_LEN_OF_MCUD EQU 18h
DATA_LEN_AT_STACK_TOP EQU (DATA_LEN_OF_PER0 + DATA_LEN_OF_MCUD + 4)
;
; Define SSE macros
;
LOAD_MMX_EXT MACRO ReturnAddress, MmxRegister
mov esi, ReturnAddress
movd MmxRegister, esi ; save ReturnAddress into MM7
ENDM
CALL_MMX_EXT MACRO RoutineLabel, MmxRegister
local ReturnAddress
mov esi, offset ReturnAddress
movd MmxRegister, esi ; save ReturnAddress into MM7
jmp RoutineLabel
ReturnAddress:
ENDM
RET_ESI_EXT MACRO MmxRegister
movd esi, MmxRegister ; restore ESP from MM7
jmp esi
ENDM
CALL_MMX MACRO RoutineLabel
CALL_MMX_EXT RoutineLabel, mm7
ENDM
RET_ESI MACRO
RET_ESI_EXT mm7
ENDM
;------------------------------------------------------------------------------
FspSelfCheckDflt PROC NEAR PUBLIC
; Inputs:
@@ -106,7 +133,7 @@ LoadUcodeDflt PROC NEAR PUBLIC
;
;
; Save return address to EBP
mov ebp, eax
movd ebp, mm7
cmp esp, 0
jz paramerror
@@ -276,6 +303,67 @@ exit:
LoadUcodeDflt ENDP
EstablishStackFsp PROC NEAR PRIVATE
; Following is the code copied from BYTFSP, need to figure out what it is doing..
;
; Save parameter pointer in edx
;
mov edx, dword ptr [esp + 4]
;
; Enable FSP STACK
;
mov esp, PcdGet32 (PcdTemporaryRamBase)
add esp, PcdGet32 (PcdTemporaryRamSize)
push DATA_LEN_OF_MCUD ; Size of the data region
push 4455434Dh ; Signature of the data region 'MCUD'
push dword ptr [edx + 12] ; Code size
push dword ptr [edx + 8] ; Code base
cmp edx, 0 ; Is parameter pointer valid ?
jz InvalidMicrocodeRegion
push dword ptr [edx + 4] ; Microcode size
push dword ptr [edx] ; Microcode base
jmp @F
InvalidMicrocodeRegion:
push 0 ; Microcode size
push 0 ; Microcode base
@@:
;
; Save API entry/exit timestamp into stack
;
push DATA_LEN_OF_PER0 ; Size of the data region
push 30524550h ; Signature of the data region 'PER0'
movd eax, xmm4
push eax
movd eax, xmm5
push eax
rdtsc
push edx
push eax
;
; Terminator for the data on stack
;
push 0
;
; Set ECX/EDX to the bootloader temporary memory range
;
mov ecx, PcdGet32 (PcdTemporaryRamBase)
mov edx, ecx
add edx, PcdGet32 (PcdTemporaryRamSize)
sub edx, PcdGet32 (PcdFspTemporaryRamSize)
xor eax, eax
RET_ESI
EstablishStackFsp ENDP
;----------------------------------------------------------------------------
; TempRamInit API
;
@@ -299,17 +387,9 @@ TempRamInitApi PROC NEAR PUBLIC
; Save timestamp into XMM4 & XMM5
;
rdtsc
SAVE_EAX
SAVE_EDX
;
; Check Parameter
;
mov eax, dword ptr [esp + 4]
cmp eax, 0
mov eax, 80000002h
jz NemInitExit
movd xmm4, edx
movd xmm5, eax
;
; CPUID/DeviceID check
;
@@ -319,82 +399,18 @@ TempRamInitApi PROC NEAR PUBLIC
cmp eax, 0
jnz NemInitExit
;
; Platform Basic Init.
;
mov eax, @F
jmp PlatformBasicInit
@@:
cmp eax, 0
jnz NemInitExit
CALL_MMX SecPlatformInit
;
; Call Sec CAR Init
CALL_MMX SecCarInit
; @todo: ESP has been modified, we need to restore here.
LOAD_REGS
SAVE_REGS
; Load microcode
;
mov eax, @F
add esp, 4
jmp LoadUcode
@@:
LOAD_ESP
cmp eax, 0
jnz NemInitExit
CALL_MMX LoadUcode
;
; Call platform NEM init
;
mov eax, @F
add esp, 4
jmp PlatformTempRamInit
@@:
LOAD_ESP
cmp eax, 0
jnz NemInitExit
;
; Save parameter pointer in edx
;
mov edx, dword ptr [esp + 4]
;
; Enable FSP STACK
;
mov esp, PcdGet32(PcdTemporaryRamBase)
add esp, PcdGet32(PcdTemporaryRamSize)
push DATA_LEN_OF_MCUD ; Size of the data region
push 4455434Dh ; Signature of the data region 'MCUD'
push dword ptr [edx + 4] ; Microcode size
push dword ptr [edx + 0] ; Microcode base
push dword ptr [edx + 12] ; Code size
push dword ptr [edx + 8] ; Code base
;
; Save API entry/exit timestamp into stack
;
push DATA_LEN_OF_PER0 ; Size of the data region
push 30524550h ; Signature of the data region 'PER0'
rdtsc
push edx
push eax
LOAD_EAX
LOAD_EDX
push edx
push eax
;
; Terminator for the data on stack
;
push 0
;
; Set ECX/EDX to the bootloader temporary memory range
;
mov ecx, PcdGet32(PcdTemporaryRamBase)
mov edx, ecx
add edx, PcdGet32(PcdTemporaryRamSize)
sub edx, PcdGet32(PcdFspTemporaryRamSize)
xor eax, eax
CALL_MMX EstablishStackFsp
NemInitExit:
;
@@ -413,31 +429,106 @@ TempRamInitApi ENDP
;
;----------------------------------------------------------------------------
FspInitApi PROC NEAR PUBLIC
mov eax, 1
jmp FspApiCommon
FspInitApi ENDP
;----------------------------------------------------------------------------
; NotifyPhase API
;
; This FSP API will notify the FSP about the different phases in the boot
; process
;
;----------------------------------------------------------------------------
NotifyPhaseApi PROC C PUBLIC
mov eax, 2
jmp FspApiCommon
NotifyPhaseApi ENDP
;----------------------------------------------------------------------------
; FspMemoryInit API
;
; This FSP API is called after TempRamInit and initializes the memory.
;
;----------------------------------------------------------------------------
FspMemoryInitApi PROC NEAR PUBLIC
mov eax, 3
jmp FspApiCommon
FspMemoryInitApi ENDP
;----------------------------------------------------------------------------
; TempRamExitApi API
;
; This API tears down temporary RAM
;
;----------------------------------------------------------------------------
TempRamExitApi PROC C PUBLIC
mov eax, 4
jmp FspApiCommon
TempRamExitApi ENDP
;----------------------------------------------------------------------------
; FspSiliconInit API
;
; This FSP API initializes the CPU and the chipset including the IO
; controllers in the chipset to enable normal operation of these devices.
;
;----------------------------------------------------------------------------
FspSiliconInitApi PROC C PUBLIC
mov eax, 5
jmp FspApiCommon
FspSiliconInitApi ENDP
;----------------------------------------------------------------------------
; FspApiCommon API
;
; This is the FSP API common entry point to resume the FSP execution
;
;----------------------------------------------------------------------------
FspApiCommon PROC C PUBLIC
;
; EAX holds the API index
;
;
; Stack must be ready
;
push 087654321h
pop eax
cmp eax, 087654321h
;
push eax
add esp, 4
cmp eax, dword ptr [esp - 4]
jz @F
mov eax, 080000003h
jmp exit
@@:
;
; Additional check
; Verify the calling condition
;
pushad
push 1
push eax
call FspApiCallingCheck
add esp, 4
mov dword ptr [esp + 4 * 7], eax
popad
cmp eax, 0
jz @F
jmp exit
mov dword ptr [esp + 4 * 7], eax
popad
ret
@@:
popad
cmp eax, 1 ; FspInit API
jz @F
cmp eax, 3 ; FspMemoryInit API
jz @F
jmp Pei2LoaderSwitchStack
@@:
;
; FspInit and FspMemoryInit APIs, setup the initial stack frame
;
;
; Store the address in FSP which will return control to the BL
;
@@ -452,30 +543,34 @@ FspInitApi PROC NEAR PUBLIC
; Reserve 8 bytes for IDT save/restore
sub esp, 8
sidt fword ptr [esp]
sidt fword ptr [esp]
;
; Setup new FSP stack
;
mov eax, esp
mov edi, esp
mov esp, PcdGet32(PcdTemporaryRamBase)
add esp, PcdGet32(PcdTemporaryRamSize)
sub esp, (DATA_LEN_AT_STACK_TOP + 40h)
;
; Save the bootloader's stack pointer
; Pass the API Idx to SecStartup
;
push eax
;
; Pass the bootloader stack to SecStartup
;
push edi
;
; Pass entry point of the PEI core
;
call GetFspBaseAddress
mov edi, FspImageSizeOffset
mov edi, DWORD PTR [eax + edi]
add edi, eax
mov edi, eax
add edi, PcdGet32 (PcdFspAreaSize)
sub edi, 20h
add eax, DWORD PTR [edi]
add eax, DWORD PTR ds:[edi]
push eax
;
@@ -505,53 +600,9 @@ FspInitApi PROC NEAR PUBLIC
;
call SecStartup
exit:
exit:
ret
FspInitApi ENDP
;----------------------------------------------------------------------------
; NotifyPhase API
;
; This FSP API will notify the FSP about the different phases in the boot
; process
;
;----------------------------------------------------------------------------
NotifyPhaseApi PROC C PUBLIC
;
; Stack must be ready
;
push 087654321h
pop eax
cmp eax, 087654321h
jz @F
mov eax, 080000003h
jmp err_exit
@@:
;
; Verify the calling condition
;
pushad
push 2
call FspApiCallingCheck
add esp, 4
mov dword ptr [esp + 4 * 7], eax
popad
cmp eax, 0
jz @F
;
; Error return
;
err_exit:
ret
@@:
jmp Pei2LoaderSwitchStack
NotifyPhaseApi ENDP
FspApiCommon ENDP
END

380
IntelFspPkg/FspSecCore/Ia32/FspApiEntry.s
View File

@@ -1,6 +1,6 @@
#------------------------------------------------------------------------------
#
# Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
# Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
@@ -165,7 +165,6 @@ ASM_GLOBAL ASM_PFX(_gPcd_FixedAtBuild_PcdFspTemporaryRamSize)
#
# Following functions will be provided in C
#
ASM_GLOBAL ASM_PFX(FspImageSizeOffset)
ASM_GLOBAL ASM_PFX(SecStartup)
ASM_GLOBAL ASM_PFX(FspApiCallingCheck)
@@ -245,7 +244,8 @@ ASM_PFX(LoadUcode):
#
# Save return address to EBP
#
movl %eax, %ebp
movd %xmm7, %ebp
cmpl $0x00, %esp
jz ParamError
movl (%esp), %eax #dword ptr [] Parameter pointer
@@ -448,6 +448,71 @@ LoadUcodeExit:
jmp *%ebp
#----------------------------------------------------------------------------
# EstablishStackFsp
#
# Following is the code copied from BYTFSP, need to figure out what it is doing..
#
#----------------------------------------------------------------------------
ASM_GLOBAL ASM_PFX(EstablishStackFsp)
ASM_PFX(EstablishStackFsp):
#
# Save parameter pointer in edx
#
movl 4(%esp), %edx
#
# Enable FSP STACK
#
movl PcdGet32(PcdTemporaryRamBase), %esp
addl PcdGet32(PcdTemporaryRamSize), %esp
pushl $DATA_LEN_OF_MCUD # Size of the data region
pushl $0x4455434D # Signature of the data region 'MCUD'
pushl 12(%edx) # Code size
pushl 8(%edx) # Code base
cmpl $0, %edx # Is parameter pointer valid ?
jz InvalidMicrocodeRegion
pushl 4(%edx) # Microcode size
pushl (%edx) # Microcode base
jmp EstablishStackFspExit
InvalidMicrocodeRegion:
push $0 # Microcode size
push $0 # Microcode base
EstablishStackFspExit:
#
# Save API entry/exit timestamp into stack
#
pushl $DATA_LEN_OF_PER0 # Size of the data region
pushl $0x30524550 # Signature of the data region 'PER0'
movd %xmm4, %eax
pushl %eax
movd %xmm5, %eax
pushl %eax
rdtsc
pushl %edx
pushl %eax
#
# Terminator for the data on stack
#
push $0x00
#
# Set ECX/EDX to the bootloader temporary memory range
#
movl PcdGet32 (PcdTemporaryRamBase), %ecx
movl %ecx, %edx
addl PcdGet32 (PcdTemporaryRamSize), %edx
subl PcdGet32 (PcdFspTemporaryRamSize), %edx
xorl %eax, %eax
movd %mm7, %esi #RET_ESI
jmp *%esi
#----------------------------------------------------------------------------
# TempRamInit API
#
@@ -472,103 +537,54 @@ ASM_PFX(TempRamInitApi):
# Save timestamp into XMM4 & XMM5
#
rdtsc
SAVE_EAX
SAVE_EDX
#
# Check Parameter
#
movl 4(%esp), %eax
cmpl $0x00, %eax
movl $0x80000002, %eax
jz NemInitExit
movd %edx, %xmm4
movd %eax, %xmm5
#
# CPUID/DeviceID check
#
movl $TempRamInitApiL0, %eax
jmp ASM_PFX(FspSelfCheckDflt) # Note: ESP can not be changed.
jmp ASM_PFX(FspSelfCheckDflt) # @note: ESP can not be changed.
TempRamInitApiL0:
cmpl $0x00, %eax
jnz NemInitExit
#
# Platform Basic Init.
# Sec Platform Init
#
movl $TempRamInitApiL1, %eax
jmp ASM_PFX(PlatformBasicInitDflt)
movl $TempRamInitApiL1, %esi #CALL_MMX SecPlatformInit
movd %mm7, %esi
jmp ASM_PFX(SecPlatformInit)
TempRamInitApiL1:
cmpl $0x00, %eax
jnz NemInitExit
#
# Call Sec CAR Init
#
movl $TempRamInitApiL2, %esi #CALL_MMX SecCarInit
movd %mm7, %esi
jmp ASM_PFX(SecCarInit)
TempRamInitApiL2:
# @todo: ESP has been modified, we need to restore here.
LOAD_REGS
SAVE_REGS
#
# Load microcode
#
movl $TempRamInitApiL2, %eax
addl $0x04, %esp
jmp LoadUcode
TempRamInitApiL2:
LOAD_ESP
cmpl $0x00, %eax
jnz NemInitExit
#
# Call platform NEM init
#
movl $TempRamInitApiL3, %eax
addl $0x04, %esp
jmp ASM_PFX(PlatformTempRamInit)
movl $TempRamInitApiL3, %esi #CALL_MMX LoadUcode
movd %mm7, %esi
jmp ASM_PFX(LoadUcode)
TempRamInitApiL3:
subl $0x04, %esp
cmpl $0x00, %eax
jnz NemInitExit
#
# Save parameter pointer in edx
# EstablishStackFsp
#
movl 4(%esp), %edx
#
# Enable FSP STACK
#
movl ASM_PFX(_gPcd_FixedAtBuild_PcdTemporaryRamBase), %esp
addl ASM_PFX(_gPcd_FixedAtBuild_PcdTemporaryRamSize), %esp
pushl $DATA_LEN_OF_MCUD # Size of the data region
pushl $0x4455434D # Signature of the data region 'MCUD'
pushl 4(%edx) # Microcode size
pushl (%edx) # Microcode base
pushl 12(%edx) # Code size
pushl 8(%edx) # Code base
#
# Save API entry/exit timestamp into stack
#
pushl $DATA_LEN_OF_PER0 # Size of the data region
pushl $0x30524550 # Signature of the data region 'PER0'
rdtsc
pushl %edx
pushl %eax
LOAD_EAX
LOAD_EDX
pushl %edx
pushl %eax
#
# Terminator for the data on stack
#
pushl $0x00
#
# Set ECX/EDX to the bootloader temporary memory range
#
movl ASM_PFX(_gPcd_FixedAtBuild_PcdTemporaryRamBase), %ecx
movl %ecx, %edx
addl ASM_PFX(_gPcd_FixedAtBuild_PcdTemporaryRamSize), %edx
subl ASM_PFX(_gPcd_FixedAtBuild_PcdFspTemporaryRamSize), %edx
xorl %eax, %eax
movl $TempRamInitApiL4, %esi #CALL_MMX EstablishStackFsp
movd %mm7, %esi
jmp ASM_PFX(EstablishStackFsp)
TempRamInitApiL4:
NemInitExit:
#
@@ -577,7 +593,6 @@ NemInitExit:
LOAD_REGS
ret
#----------------------------------------------------------------------------
# FspInit API
#
@@ -588,40 +603,113 @@ NemInitExit:
#----------------------------------------------------------------------------
ASM_GLOBAL ASM_PFX(FspInitApi)
ASM_PFX(FspInitApi):
movl $0x01, %eax
jmp FspApiCommon
#----------------------------------------------------------------------------
# NotifyPhase API
#
# This FSP API will notify the FSP about the different phases in the boot
# process
#
#----------------------------------------------------------------------------
ASM_GLOBAL ASM_PFX(NotifyPhaseApi)
ASM_PFX(NotifyPhaseApi):
movl $0x02, %eax
jmp FspApiCommon
#----------------------------------------------------------------------------
# FspMemoryInit API
#
# This FSP API is called after TempRamInit and initializes the memory.
#
#----------------------------------------------------------------------------
ASM_GLOBAL ASM_PFX(FspMemoryInitApi)
ASM_PFX(FspMemoryInitApi):
movl $0x03, %eax
jmp FspApiCommon
#----------------------------------------------------------------------------
# TempRamExitApi API
#
# This API tears down temporary RAM
#
#----------------------------------------------------------------------------
ASM_GLOBAL ASM_PFX(TempRamExitApi)
ASM_PFX(TempRamExitApi):
movl $0x04, %eax
jmp FspApiCommon
#----------------------------------------------------------------------------
# FspSiliconInit API
#
# This FSP API initializes the CPU and the chipset including the IO
# controllers in the chipset to enable normal operation of these devices.
#
#----------------------------------------------------------------------------
ASM_GLOBAL ASM_PFX(FspSiliconInitApi)
ASM_PFX(FspSiliconInitApi):
movl $0x05, %eax
jmp FspApiCommon
#----------------------------------------------------------------------------
# FspApiCommon API
#
# This is the FSP API common entry point to resume the FSP execution
#
#----------------------------------------------------------------------------
ASM_GLOBAL ASM_PFX(FspApiCommon)
ASM_PFX(FspApiCommon):
#
# EAX holds the API index
#
#
# Stack must be ready
#
pushl $0x087654321
popl %eax
cmpl $0x087654321, %eax
jz FspInitApiL0
#
pushl %eax
addl $0x04, %esp
cmpl -4(%esp), %eax
jz FspApiCommonL0
movl $0x080000003, %eax
jmp FspInitApiexit
jmp FspApiCommonExit
FspInitApiL0:
FspApiCommonL0:
#
# Additional check
# Verify the calling condition
#
pusha
pushl $0x01
pushal
pushl %eax
call ASM_PFX(FspApiCallingCheck)
addl $0x04, %esp
movl %eax, 28(%esp)
popa
cmpl $0x00, %eax
jz FspInitApiL1
jmp FspInitApiexit
jz FspApiCommonL1
movl %eax, 0x1C(%esp) # mov dword ptr [esp + 4 * 7], eax
popal
ret
FspInitApiL1:
FspApiCommonL1:
popal
cmpl $0x01, %eax # FspInit API
jz FspApiCommonL2
cmpl $0x03, %eax # FspMemoryInit API
jz FspApiCommonL2
jmp Pei2LoaderSwitchStack
FspApiCommonL2:
#
# FspInit and FspMemoryInit APIs, setup the initial stack frame
#
#
# Store the address in FSP which will return control to the BL
#
pushl $FspInitApiexit
pushl $FspApiCommonExit
#
# Create a Task Frame in the stack for the Boot Loader
#
pushfl # 2 pushf for 4 byte alignment
pushfl # 2 pushf for 4 byte alignment
cli
pushal
@@ -634,25 +722,30 @@ FspInitApiL1:
#
# Setup new FSP stack
#
movl %esp, %eax
movl ASM_PFX(_gPcd_FixedAtBuild_PcdTemporaryRamBase), %esp
addl ASM_PFX(_gPcd_FixedAtBuild_PcdTemporaryRamSize), %esp
movl %esp, %edi
movl PcdGet32(PcdTemporaryRamBase), %esp
addl PcdGet32(PcdTemporaryRamSize), %esp
subl $(DATA_LEN_AT_STACK_TOP + 0x40), %esp
# Save the bootloader's stack pointer
#
pushl %eax
# Pass the API Idx to SecStartup
#
pushl %eax
#
# Pass the bootloader stack to SecStartup
#
pushl %edi
#
# Pass entry point of the PEI core
#
call ASM_PFX(GetFspBaseAddress)
movl ASM_PFX(FspImageSizeOffset), %edi
movl (%eax, %edi), %edi
addl %eax, %edi
subl $0x20, %edi
addl (%edi), %eax
pushl %eax
call ASM_PFX(GetFspBaseAddress)
movl %eax, %edi
addl PcdGet32(PcdFspAreaSize), %edi
subl $0x20, %edi
addl %ds:(%edi), %eax
pushl %eax
#
# Pass BFV into the PEI Core
@@ -661,72 +754,27 @@ FspInitApiL1:
# PcdFspAreaBaseAddress are the same. For FSP with mulitple FVs,
# they are different. The code below can handle both cases.
#
call ASM_PFX(GetFspBaseAddress)
movl %eax , %edi
call ASM_PFX(GetBootFirmwareVolumeOffset)
addl %edi ,%eax
pushl %eax
call ASM_PFX(GetFspBaseAddress)
movl %eax, %edi
call ASM_PFX(GetBootFirmwareVolumeOffset)
addl %edi, %eax
pushl %eax
#
# Pass stack base and size into the PEI Core
#
movl ASM_PFX(_gPcd_FixedAtBuild_PcdTemporaryRamBase), %eax
addl ASM_PFX(_gPcd_FixedAtBuild_PcdTemporaryRamSize), %eax
subl ASM_PFX(_gPcd_FixedAtBuild_PcdFspTemporaryRamSize), %eax
pushl %eax
pushl ASM_PFX(_gPcd_FixedAtBuild_PcdFspTemporaryRamSize)
movl PcdGet32(PcdTemporaryRamBase), %eax
addl PcdGet32(PcdTemporaryRamSize), %eax
subl PcdGet32(PcdFspTemporaryRamSize), %eax
pushl %eax
pushl PcdGet32(PcdFspTemporaryRamSize)
#
# Pass Control into the PEI Core
#
call ASM_PFX(SecStartup)
FspInitApiexit:
FspApiCommonExit:
ret
#----------------------------------------------------------------------------
# NotifyPhase API
#
# This FSP API will notify the FSP about the different phases in the boot
# process
#
#----------------------------------------------------------------------------
ASM_GLOBAL ASM_PFX(NotifyPhaseApi)
ASM_PFX(NotifyPhaseApi):
#
# Stack must be ready
#
pushl $0x0087654321
popl %eax
cmpl $0x087654321, %eax
jz NotifyPhaseApiL0
movl $0x080000003, %eax
jmp NotifyPhaseApiErrExit
NotifyPhaseApiL0:
#
# Verify the calling condition
#
pusha
pushl $0x02
call ASM_PFX(FspApiCallingCheck)
addl $0x04, %esp
movl %eax, 28(%esp)
popa
cmpl $0x00, %eax
jz NotifyPhaseApiL1
#
# Error return
#
NotifyPhaseApiErrExit:
ret
NotifyPhaseApiL1:
jmp ASM_PFX(Pei2LoaderSwitchStack)
#END

4
IntelFspPkg/FspSecCore/Ia32/InitializeFpu.s
View File

@@ -1,6 +1,6 @@
#------------------------------------------------------------------------------
#
# Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
# Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
@@ -58,7 +58,7 @@ ASM_PFX(InitializeFloatingPointUnits):
# Set OSFXSR bit 9 in CR4
#
movl %cr4, %eax
or BIT9, %eax
orl $BIT9, %eax
movl %eax, %cr4
#

30
IntelFspPkg/FspSecCore/Ia32/Stacks.s
View File

@@ -1,6 +1,6 @@
#------------------------------------------------------------------------------
#
# Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
# Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
@@ -28,12 +28,12 @@ ASM_GLOBAL ASM_PFX(SecSwitchStack)
ASM_GLOBAL ASM_PFX(SecSwitchStack)
ASM_PFX(SecSwitchStack):
#
# Save three register: eax, ebx, ecx
# Save four registers: eax, ebx, ecx, edx
#
push %eax
push %ebx
push %ecx
push %edx
pushl %eax
pushl %ebx
pushl %ecx
pushl %edx
#
# !!CAUTION!! this function address's is pushed into stack after
@@ -67,7 +67,6 @@ ASM_PFX(SecSwitchStack):
#
# Fixup the ebp point to permenent memory
#
movl %ebp, %eax
subl %ebx, %eax
addl %ecx, %eax
@@ -76,13 +75,12 @@ ASM_PFX(SecSwitchStack):
#
# Fixup callee's ebp point for PeiDispatch
#
movl %ebp, %eax
subl %ebx, %eax
addl %ecx, %eax
movl %eax, %ebp # From now, ebp is pointed to permenent memory
pop %edx
pop %ecx
pop %ebx
pop %eax
# movl %ebp, %eax
# subl %ebx, %eax
# addl %ecx, %eax
# movl %eax, %ebp # From now, ebp is pointed to permenent memory
popl %edx
popl %ecx
popl %ebx
popl %eax
ret

55
IntelFspPkg/FspSecCore/SecFsp.c
View File

@@ -1,6 +1,6 @@
/** @file
Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -13,8 +13,6 @@
#include "SecFsp.h"
UINT32 FspImageSizeOffset = FSP_INFO_HEADER_OFF + OFFSET_IN_FSP_INFO_HEADER(ImageSize);
/**
Calculate the FSP IDT gate descriptor.
@@ -140,13 +138,15 @@ SecGetPlatformData (
It needs to be done as soon as possible after the stack is setup.
@param[in,out] PeiFspData Pointer of the FSP global data.
@param[in] BootFirmwareVolume Point to the address of BootFirmwareVolume in stack.
@param[in] BootloaderStack Bootloader stack.
@param[in] ApiIdx The index of the FSP API.
**/
VOID
FspGlobalDataInit (
IN OUT FSP_GLOBAL_DATA *PeiFspData,
IN VOID **BootFirmwareVolume
IN UINT32 BootloaderStack,
IN UINT8 ApiIdx
)
{
VOID *UpdDataRgnPtr;
@@ -162,7 +162,7 @@ FspGlobalDataInit (
ZeroMem ((VOID *)PeiFspData, sizeof(FSP_GLOBAL_DATA));
PeiFspData->Signature = FSP_GLOBAL_DATA_SIGNATURE;
PeiFspData->CoreStack = *(UINTN *)(BootFirmwareVolume + 2);
PeiFspData->CoreStack = BootloaderStack;
PeiFspData->PerfIdx = 2;
SetFspMeasurePoint (FSP_PERF_ID_API_FSPINIT_ENTRY);
@@ -174,6 +174,11 @@ FspGlobalDataInit (
PeiFspData->FspInfoHeader = (FSP_INFO_HEADER *)(GetFspBaseAddress() + FSP_INFO_HEADER_OFF);
SecGetPlatformData (PeiFspData);
//
// Set API calling mode
//
SetFspApiCallingMode (ApiIdx == 1 ? 0 : 1);
//
// Initialize UPD pointer.
//
@@ -202,8 +207,13 @@ FspGlobalDataInit (
}
ImageId[Idx] = 0;
DEBUG ((DEBUG_INFO | DEBUG_INIT, "\n============= PEIM FSP (%a 0x%08X) =============\n", \
ImageId, PeiFspData->FspInfoHeader->ImageRevision));
DEBUG ((DEBUG_INFO | DEBUG_INIT, "\n============= PEIM FSP v1.%x (%a v%x.%x.%x.%x) =============\n", \
PeiFspData->FspInfoHeader->HeaderRevision - 1, \
ImageId, \
(PeiFspData->FspInfoHeader->ImageRevision >> 24) & 0xff, \
(PeiFspData->FspInfoHeader->ImageRevision >> 16) & 0xff, \
(PeiFspData->FspInfoHeader->ImageRevision >> 8) & 0xff, \
(PeiFspData->FspInfoHeader->ImageRevision >> 0) & 0xff));
}
@@ -260,6 +270,35 @@ FspApiCallingCheck (
Status = EFI_UNSUPPORTED;
}
}
} else if (ApiIdx == 3) {
//
// FspMemoryInit check
//
if ((UINT32)FspData != 0xFFFFFFFF) {
Status = EFI_UNSUPPORTED;
}
} else if (ApiIdx == 4) {
//
// TempRamExit check
//
if ((FspData == NULL) || ((UINT32)FspData == 0xFFFFFFFF)) {
Status = EFI_UNSUPPORTED;
} else {
if (FspData->Signature != FSP_GLOBAL_DATA_SIGNATURE) {
Status = EFI_UNSUPPORTED;
}
}
} else if (ApiIdx == 5) {
//
// FspSiliconInit check
//
if ((FspData == NULL) || ((UINT32)FspData == 0xFFFFFFFF)) {
Status = EFI_UNSUPPORTED;
} else {
if (FspData->Signature != FSP_GLOBAL_DATA_SIGNATURE) {
Status = EFI_UNSUPPORTED;
}
}
} else {
Status = EFI_UNSUPPORTED;
}

8
IntelFspPkg/FspSecCore/SecFsp.h
View File

@@ -1,6 +1,6 @@
/** @file
Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -47,13 +47,15 @@ FspGetExceptionHandler(
It needs to be done as soon as possible after the stack is setup.
@param[in,out] PeiFspData Pointer of the FSP global data.
@param[in] BootFirmwareVolume Point to the address of BootFirmwareVolume in stack.
@param[in] BootloaderStack Bootloader stack.
@param[in] ApiIdx The index of the FSP API.
**/
VOID
FspGlobalDataInit (
IN OUT FSP_GLOBAL_DATA *PeiFspData,
IN VOID **BootFirmwareVolume
IN UINT32 BootloaderStack,
IN UINT8 ApiIdx
);

16
IntelFspPkg/FspSecCore/SecMain.c
View File

@@ -1,6 +1,6 @@
/** @file
Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -41,7 +41,9 @@ UINT64 mIdtEntryTemplate = 0xffff8e000008ffe4ULL;
@param[in] SizeOfRam Size of the temporary memory available for use.
@param[in] TempRamBase Base address of tempory ram
@param[in] BootFirmwareVolume Base address of the Boot Firmware Volume.
@param[in] PeiCoreEntry Pei Core entrypoint.
@param[in] PeiCore PeiCore entry point.
@param[in] BootloaderStack Bootloader stack.
@param[in] ApiIdx the index of API
@return This function never returns.
@@ -52,7 +54,9 @@ SecStartup (
IN UINT32 SizeOfRam,
IN UINT32 TempRamBase,
IN VOID *BootFirmwareVolume,
IN UINTN PeiCoreEntry
IN PEI_CORE_ENTRY PeiCore,
IN UINT32 BootloaderStack,
IN UINT32 ApiIdx
)
{
EFI_SEC_PEI_HAND_OFF SecCoreData;
@@ -60,7 +64,6 @@ SecStartup (
SEC_IDT_TABLE IdtTableInStack;
UINT32 Index;
FSP_GLOBAL_DATA PeiFspData;
PEI_CORE_ENTRY PeiCore;
UINT64 ExceptionHandler;
//
@@ -103,7 +106,7 @@ SecStartup (
//
// Iniitalize the global FSP data region
//
FspGlobalDataInit (&PeiFspData, &BootFirmwareVolume);
FspGlobalDataInit (&PeiFspData, BootloaderStack, (UINT8)ApiIdx);
//
// Update the base address and length of Pei temporary memory
@@ -120,8 +123,7 @@ SecStartup (
//
// Call PeiCore Entry
//
PeiCore = (PEI_CORE_ENTRY)(PeiCoreEntry);
//
PeiCore (&SecCoreData, mPeiSecPlatformInformationPpi);
//

9
IntelFspPkg/FspSecCore/SecMain.h
View File

@@ -1,6 +1,6 @@
/** @file
Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -107,7 +107,8 @@ InitializeFloatingPointUnits (
@param[in] SizeOfRam Size of the temporary memory available for use.
@param[in] TempRamBase Base address of tempory ram
@param[in] BootFirmwareVolume Base address of the Boot Firmware Volume.
@param[in] PeiCoreEntry Pei Core entrypoint.
@param[in] PeiCore PeiCore entry point.
@param[in] BootloaderStack Bootloader stack.
@return This function never returns.
@@ -118,7 +119,9 @@ SecStartup (
IN UINT32 SizeOfRam,
IN UINT32 TempRamBase,
IN VOID *BootFirmwareVolume,
IN UINTN PeiCoreEntry
IN PEI_CORE_ENTRY PeiCore,
IN UINT32 BootloaderStack,
IN UINT32 ApiIdx
);
/**