ARM: Remove NSACR from the common code

NSACR (Non-Secure Access Control Register) is AArch32 specific.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14522 6f19259b-4bc3-4df7-8a09-765794883524

ArmPkg/Library/ArmLib/ArmV7/ArmLibSupportV7.S

@@ -1,7 +1,7 @@
 #------------------------------------------------------------------------------ 
 #
 # Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
-# Copyright (c) 2011, ARM Limited. All rights reserved.
+# Copyright (c) 2011-2013, ARM Limited. All rights reserved.
 #
 # This program and the accompanying materials
 # are licensed and made available under the terms and conditions of the BSD License
@@ -29,6 +29,8 @@ GCC_ASM_EXPORT(ArmEnableInterrupts)
 GCC_ASM_EXPORT(ArmDisableInterrupts)
 GCC_ASM_EXPORT(ReadCCSIDR)
 GCC_ASM_EXPORT(ReadCLIDR)
+GCC_ASM_EXPORT(ArmReadNsacr)
+GCC_ASM_EXPORT(ArmWriteNsacr)
 
 #------------------------------------------------------------------------------
 
@@ -98,4 +100,12 @@ ASM_PFX(ReadCLIDR):
   mrc p15,1,r0,c0,c0,1 @ Read CP15 Cache Level ID Register
   bx  lr
 
+ASM_PFX(ArmReadNsacr):
+  mrc     p15, 0, r0, c1, c1, 2
+  bx      lr
+
+ASM_PFX(ArmWriteNsacr):
+  mcr     p15, 0, r0, c1, c1, 2
+  bx      lr
+
 ASM_FUNCTION_REMOVE_IF_UNREFERENCED

ArmPkg/Library/ArmLib/ArmV7/ArmLibSupportV7.asm

@@ -1,7 +1,7 @@
 //------------------------------------------------------------------------------ 
 //
 // Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
-// Copyright (c) 2011, ARM Limited. All rights reserved.
+// Copyright (c) 2011-2013, ARM Limited. All rights reserved.
 //
 // This program and the accompanying materials
 // are licensed and made available under the terms and conditions of the BSD License
@@ -25,7 +25,9 @@
     EXPORT  ArmDisableInterrupts
     EXPORT  ReadCCSIDR
     EXPORT  ReadCLIDR
-    
+    EXPORT  ArmReadNsacr
+    EXPORT  ArmWriteNsacr
+
     AREA ArmLibSupportV7, CODE, READONLY
 
 
@@ -96,5 +98,13 @@ ReadCCSIDR
 ReadCLIDR
   mrc p15,1,r0,c0,c0,1 ; Read CP15 Cache Level ID Register
   bx  lr
-  
+
+ArmReadNsacr
+  mrc     p15, 0, r0, c1, c1, 2
+  bx      lr
+
+ArmWriteNsacr
+  mcr     p15, 0, r0, c1, c1, 2
+  bx      lr
+
   END

ArmPkg/Library/ArmLib/Common/AArch64/ArmLibSupport.S

@@ -32,7 +32,7 @@ GCC_ASM_EXPORT (ArmWriteAuxCr)
 GCC_ASM_EXPORT (ArmReadAuxCr)
 GCC_ASM_EXPORT (ArmInvalidateTlb)
 GCC_ASM_EXPORT (ArmUpdateTranslationTableEntry)
-GCC_ASM_EXPORT (ArmWriteNsacr)
+GCC_ASM_EXPORT (ArmWriteCptr)
 GCC_ASM_EXPORT (ArmWriteScr)
 GCC_ASM_EXPORT (ArmWriteMVBar)
 GCC_ASM_EXPORT (ArmCallWFE)
@@ -176,9 +176,9 @@ ASM_PFX(ArmInvalidateTlb):
    isb
    ret
 
-ASM_PFX(ArmWriteNsacr):
+ASM_PFX(ArmWriteCptr):
   msr     cptr_el3, x0           // EL3 Coprocessor Trap Reg (CPTR)
-  ret                            // Non-Secure Access Control Reg (NSACR) in ARMv7
+  ret
 
 ASM_PFX(ArmWriteScr):
   msr     scr_el3, x0            // Secure configuration register EL3

ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.S

@@ -38,8 +38,6 @@ GCC_ASM_EXPORT(ArmWriteAuxCr)
 GCC_ASM_EXPORT(ArmReadAuxCr)
 GCC_ASM_EXPORT(ArmInvalidateTlb)
 GCC_ASM_EXPORT(ArmUpdateTranslationTableEntry)
-GCC_ASM_EXPORT(ArmReadNsacr)
-GCC_ASM_EXPORT(ArmWriteNsacr)
 GCC_ASM_EXPORT(ArmReadScr)
 GCC_ASM_EXPORT(ArmWriteScr)
 GCC_ASM_EXPORT(ArmReadMVBar)
@@ -147,14 +145,6 @@ ASM_PFX(ArmInvalidateTlb):
   isb
   bx      lr
 
-ASM_PFX(ArmReadNsacr):
-  mrc     p15, 0, r0, c1, c1, 2
-  bx      lr
-
-ASM_PFX(ArmWriteNsacr):
-  mcr     p15, 0, r0, c1, c1, 2
-  bx      lr
-
 ASM_PFX(ArmReadScr):
   mrc     p15, 0, r0, c1, c1, 0
   bx      lr

ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.asm

@@ -38,8 +38,6 @@
     EXPORT ArmReadAuxCr
     EXPORT ArmInvalidateTlb
     EXPORT ArmUpdateTranslationTableEntry
-    EXPORT ArmReadNsacr
-    EXPORT ArmWriteNsacr
     EXPORT ArmReadScr
     EXPORT ArmWriteScr
     EXPORT ArmReadMVBar
@@ -147,14 +145,6 @@ ArmInvalidateTlb
   isb
   bx      lr
 
-ArmReadNsacr
-  mrc     p15, 0, r0, c1, c1, 2
-  bx      lr
-
-ArmWriteNsacr
-  mcr     p15, 0, r0, c1, c1, 2
-  bx      lr
-
 ArmReadScr
   mrc     p15, 0, r0, c1, c1, 0
   bx      lr