ArmPkg: introduce base ArmMmuLib implementation
This base library encapsulates the MMU manipulation routines that have been factored out of ArmLib. The functionality covers initial creation of the 1:1 mapping in the page tables, and remapping regions to change permissions or cacheability attributes. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
This commit is contained in:
Ard Biesheuvel
452
ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c
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452
ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c
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@@ -0,0 +1,452 @@
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/** @file
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* File managing the MMU for ARMv7 architecture
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*
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* Copyright (c) 2011-2016, ARM Limited. All rights reserved.
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*
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* This program and the accompanying materials
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* are licensed and made available under the terms and conditions of the BSD License
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* which accompanies this distribution. The full text of the license may be found at
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* http://opensource.org/licenses/bsd-license.php
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*
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* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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*
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**/
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#include <Uefi.h>
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#include <Chipset/ArmV7.h>
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#include <Library/BaseMemoryLib.h>
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#include <Library/MemoryAllocationLib.h>
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#include <Library/ArmLib.h>
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#include <Library/BaseLib.h>
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#include <Library/DebugLib.h>
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#include <Library/PcdLib.h>
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#define ID_MMFR0_SHARELVL_SHIFT 12
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#define ID_MMFR0_SHARELVL_MASK 0xf
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#define ID_MMFR0_SHARELVL_ONE 0
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#define ID_MMFR0_SHARELVL_TWO 1
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#define ID_MMFR0_INNERSHR_SHIFT 28
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#define ID_MMFR0_INNERSHR_MASK 0xf
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#define ID_MMFR0_OUTERSHR_SHIFT 8
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#define ID_MMFR0_OUTERSHR_MASK 0xf
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#define ID_MMFR0_SHR_IMP_UNCACHED 0
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#define ID_MMFR0_SHR_IMP_HW_COHERENT 1
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#define ID_MMFR0_SHR_IGNORED 0xf
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UINTN
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EFIAPI
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ArmReadIdMmfr0 (
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VOID
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);
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BOOLEAN
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EFIAPI
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ArmHasMpExtensions (
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VOID
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);
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UINT32
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ConvertSectionAttributesToPageAttributes (
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IN UINT32 SectionAttributes,
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IN BOOLEAN IsLargePage
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)
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{
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UINT32 PageAttributes;
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PageAttributes = 0;
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PageAttributes |= TT_DESCRIPTOR_CONVERT_TO_PAGE_CACHE_POLICY (SectionAttributes, IsLargePage);
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PageAttributes |= TT_DESCRIPTOR_CONVERT_TO_PAGE_AP (SectionAttributes);
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PageAttributes |= TT_DESCRIPTOR_CONVERT_TO_PAGE_XN (SectionAttributes, IsLargePage);
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PageAttributes |= TT_DESCRIPTOR_CONVERT_TO_PAGE_NG (SectionAttributes);
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PageAttributes |= TT_DESCRIPTOR_CONVERT_TO_PAGE_S (SectionAttributes);
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return PageAttributes;
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}
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STATIC
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BOOLEAN
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PreferNonshareableMemory (
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VOID
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)
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{
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UINTN Mmfr;
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UINTN Val;
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if (FeaturePcdGet (PcdNormalMemoryNonshareableOverride)) {
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return TRUE;
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}
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//
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// Check whether the innermost level of shareability (the level we will use
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// by default to map normal memory) is implemented with hardware coherency
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// support. Otherwise, revert to mapping as non-shareable.
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//
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Mmfr = ArmReadIdMmfr0 ();
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switch ((Mmfr >> ID_MMFR0_SHARELVL_SHIFT) & ID_MMFR0_SHARELVL_MASK) {
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case ID_MMFR0_SHARELVL_ONE:
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// one level of shareability
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Val = (Mmfr >> ID_MMFR0_OUTERSHR_SHIFT) & ID_MMFR0_OUTERSHR_MASK;
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break;
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case ID_MMFR0_SHARELVL_TWO:
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// two levels of shareability
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Val = (Mmfr >> ID_MMFR0_INNERSHR_SHIFT) & ID_MMFR0_INNERSHR_MASK;
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break;
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default:
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// unexpected value -> shareable is the safe option
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ASSERT (FALSE);
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return FALSE;
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}
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return Val != ID_MMFR0_SHR_IMP_HW_COHERENT;
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}
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STATIC
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VOID
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PopulateLevel2PageTable (
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IN UINT32 *SectionEntry,
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IN UINT32 PhysicalBase,
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IN UINT32 RemainLength,
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IN ARM_MEMORY_REGION_ATTRIBUTES Attributes
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)
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{
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UINT32* PageEntry;
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UINT32 Pages;
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UINT32 Index;
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UINT32 PageAttributes;
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UINT32 SectionDescriptor;
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UINT32 TranslationTable;
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UINT32 BaseSectionAddress;
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switch (Attributes) {
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case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK:
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case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK:
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PageAttributes = TT_DESCRIPTOR_PAGE_WRITE_BACK;
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break;
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case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH:
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case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH:
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PageAttributes = TT_DESCRIPTOR_PAGE_WRITE_THROUGH;
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break;
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case ARM_MEMORY_REGION_ATTRIBUTE_DEVICE:
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case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE:
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PageAttributes = TT_DESCRIPTOR_PAGE_DEVICE;
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break;
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case ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED:
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case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED:
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PageAttributes = TT_DESCRIPTOR_PAGE_UNCACHED;
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break;
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default:
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PageAttributes = TT_DESCRIPTOR_PAGE_UNCACHED;
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break;
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}
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if (PreferNonshareableMemory ()) {
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PageAttributes &= ~TT_DESCRIPTOR_PAGE_S_SHARED;
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}
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// Check if the Section Entry has already been populated. Otherwise attach a
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// Level 2 Translation Table to it
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if (*SectionEntry != 0) {
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// The entry must be a page table. Otherwise it exists an overlapping in the memory map
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if (TT_DESCRIPTOR_SECTION_TYPE_IS_PAGE_TABLE(*SectionEntry)) {
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TranslationTable = *SectionEntry & TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK;
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} else if ((*SectionEntry & TT_DESCRIPTOR_SECTION_TYPE_MASK) == TT_DESCRIPTOR_SECTION_TYPE_SECTION) {
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// Case where a virtual memory map descriptor overlapped a section entry
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// Allocate a Level2 Page Table for this Section
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TranslationTable = (UINTN)AllocatePages(EFI_SIZE_TO_PAGES(TRANSLATION_TABLE_PAGE_SIZE + TRANSLATION_TABLE_PAGE_ALIGNMENT));
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TranslationTable = ((UINTN)TranslationTable + TRANSLATION_TABLE_PAGE_ALIGNMENT_MASK) & ~TRANSLATION_TABLE_PAGE_ALIGNMENT_MASK;
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// Translate the Section Descriptor into Page Descriptor
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SectionDescriptor = TT_DESCRIPTOR_PAGE_TYPE_PAGE | ConvertSectionAttributesToPageAttributes (*SectionEntry, FALSE);
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BaseSectionAddress = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(*SectionEntry);
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// Populate the new Level2 Page Table for the section
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PageEntry = (UINT32*)TranslationTable;
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for (Index = 0; Index < TRANSLATION_TABLE_PAGE_COUNT; Index++) {
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PageEntry[Index] = TT_DESCRIPTOR_PAGE_BASE_ADDRESS(BaseSectionAddress + (Index << 12)) | SectionDescriptor;
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}
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// Overwrite the section entry to point to the new Level2 Translation Table
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*SectionEntry = (TranslationTable & TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK) |
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(IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE(Attributes) ? (1 << 3) : 0) |
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TT_DESCRIPTOR_SECTION_TYPE_PAGE_TABLE;
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} else {
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// We do not support the other section type (16MB Section)
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ASSERT(0);
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return;
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}
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} else {
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TranslationTable = (UINTN)AllocatePages(EFI_SIZE_TO_PAGES(TRANSLATION_TABLE_PAGE_SIZE + TRANSLATION_TABLE_PAGE_ALIGNMENT));
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TranslationTable = ((UINTN)TranslationTable + TRANSLATION_TABLE_PAGE_ALIGNMENT_MASK) & ~TRANSLATION_TABLE_PAGE_ALIGNMENT_MASK;
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ZeroMem ((VOID *)TranslationTable, TRANSLATION_TABLE_PAGE_SIZE);
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*SectionEntry = (TranslationTable & TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK) |
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(IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE(Attributes) ? (1 << 3) : 0) |
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TT_DESCRIPTOR_SECTION_TYPE_PAGE_TABLE;
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}
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PageEntry = ((UINT32 *)(TranslationTable) + ((PhysicalBase & TT_DESCRIPTOR_PAGE_INDEX_MASK) >> TT_DESCRIPTOR_PAGE_BASE_SHIFT));
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Pages = RemainLength / TT_DESCRIPTOR_PAGE_SIZE;
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for (Index = 0; Index < Pages; Index++) {
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*PageEntry++ = TT_DESCRIPTOR_PAGE_BASE_ADDRESS(PhysicalBase) | PageAttributes;
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PhysicalBase += TT_DESCRIPTOR_PAGE_SIZE;
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}
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}
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STATIC
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VOID
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FillTranslationTable (
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IN UINT32 *TranslationTable,
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IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryRegion
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)
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{
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UINT32 *SectionEntry;
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UINT32 Attributes;
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UINT32 PhysicalBase;
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UINT64 RemainLength;
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ASSERT(MemoryRegion->Length > 0);
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if (MemoryRegion->PhysicalBase >= SIZE_4GB) {
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return;
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}
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PhysicalBase = MemoryRegion->PhysicalBase;
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RemainLength = MIN(MemoryRegion->Length, SIZE_4GB - PhysicalBase);
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switch (MemoryRegion->Attributes) {
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case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK:
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Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK(0);
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break;
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case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH:
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Attributes = TT_DESCRIPTOR_SECTION_WRITE_THROUGH(0);
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break;
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case ARM_MEMORY_REGION_ATTRIBUTE_DEVICE:
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Attributes = TT_DESCRIPTOR_SECTION_DEVICE(0);
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break;
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case ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED:
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Attributes = TT_DESCRIPTOR_SECTION_UNCACHED(0);
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break;
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case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK:
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Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK(1);
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break;
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case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH:
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Attributes = TT_DESCRIPTOR_SECTION_WRITE_THROUGH(1);
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break;
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case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE:
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Attributes = TT_DESCRIPTOR_SECTION_DEVICE(1);
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break;
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case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED:
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Attributes = TT_DESCRIPTOR_SECTION_UNCACHED(1);
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break;
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default:
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Attributes = TT_DESCRIPTOR_SECTION_UNCACHED(0);
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break;
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}
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if (PreferNonshareableMemory ()) {
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Attributes &= ~TT_DESCRIPTOR_SECTION_S_SHARED;
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}
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// Get the first section entry for this mapping
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SectionEntry = TRANSLATION_TABLE_ENTRY_FOR_VIRTUAL_ADDRESS(TranslationTable, MemoryRegion->VirtualBase);
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while (RemainLength != 0) {
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if (PhysicalBase % TT_DESCRIPTOR_SECTION_SIZE == 0) {
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if (RemainLength >= TT_DESCRIPTOR_SECTION_SIZE) {
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// Case: Physical address aligned on the Section Size (1MB) && the length is greater than the Section Size
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*SectionEntry++ = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(PhysicalBase) | Attributes;
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PhysicalBase += TT_DESCRIPTOR_SECTION_SIZE;
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} else {
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// Case: Physical address aligned on the Section Size (1MB) && the length does not fill a section
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PopulateLevel2PageTable (SectionEntry++, PhysicalBase, RemainLength, MemoryRegion->Attributes);
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// It must be the last entry
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break;
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}
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} else {
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// Case: Physical address NOT aligned on the Section Size (1MB)
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PopulateLevel2PageTable (SectionEntry++, PhysicalBase, RemainLength, MemoryRegion->Attributes);
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// Aligned the address
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PhysicalBase = (PhysicalBase + TT_DESCRIPTOR_SECTION_SIZE) & ~(TT_DESCRIPTOR_SECTION_SIZE-1);
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// If it is the last entry
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if (RemainLength < TT_DESCRIPTOR_SECTION_SIZE) {
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break;
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}
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}
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RemainLength -= TT_DESCRIPTOR_SECTION_SIZE;
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}
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}
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RETURN_STATUS
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EFIAPI
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ArmConfigureMmu (
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IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable,
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OUT VOID **TranslationTableBase OPTIONAL,
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OUT UINTN *TranslationTableSize OPTIONAL
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)
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{
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VOID* TranslationTable;
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ARM_MEMORY_REGION_ATTRIBUTES TranslationTableAttribute;
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UINT32 TTBRAttributes;
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// Allocate pages for translation table.
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TranslationTable = AllocatePages (EFI_SIZE_TO_PAGES (TRANSLATION_TABLE_SECTION_SIZE + TRANSLATION_TABLE_SECTION_ALIGNMENT));
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if (TranslationTable == NULL) {
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return RETURN_OUT_OF_RESOURCES;
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}
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TranslationTable = (VOID*)(((UINTN)TranslationTable + TRANSLATION_TABLE_SECTION_ALIGNMENT_MASK) & ~TRANSLATION_TABLE_SECTION_ALIGNMENT_MASK);
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if (TranslationTableBase != NULL) {
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*TranslationTableBase = TranslationTable;
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}
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if (TranslationTableSize != NULL) {
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*TranslationTableSize = TRANSLATION_TABLE_SECTION_SIZE;
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}
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ZeroMem (TranslationTable, TRANSLATION_TABLE_SECTION_SIZE);
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// By default, mark the translation table as belonging to a uncached region
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TranslationTableAttribute = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;
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while (MemoryTable->Length != 0) {
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// Find the memory attribute for the Translation Table
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if (((UINTN)TranslationTable >= MemoryTable->PhysicalBase) && ((UINTN)TranslationTable <= MemoryTable->PhysicalBase - 1 + MemoryTable->Length)) {
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TranslationTableAttribute = MemoryTable->Attributes;
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}
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FillTranslationTable (TranslationTable, MemoryTable);
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MemoryTable++;
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}
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// Translate the Memory Attributes into Translation Table Register Attributes
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if ((TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED) ||
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(TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED)) {
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TTBRAttributes = ArmHasMpExtensions () ? TTBR_MP_NON_CACHEABLE : TTBR_NON_CACHEABLE;
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} else if ((TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK) ||
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(TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK)) {
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TTBRAttributes = ArmHasMpExtensions () ? TTBR_MP_WRITE_BACK_ALLOC : TTBR_WRITE_BACK_ALLOC;
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} else if ((TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH) ||
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(TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH)) {
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TTBRAttributes = ArmHasMpExtensions () ? TTBR_MP_WRITE_THROUGH : TTBR_WRITE_THROUGH;
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} else {
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ASSERT (0); // No support has been found for the attributes of the memory region that the translation table belongs to.
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return RETURN_UNSUPPORTED;
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}
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if (TTBRAttributes & TTBR_SHAREABLE) {
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if (PreferNonshareableMemory ()) {
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TTBRAttributes ^= TTBR_SHAREABLE;
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} else {
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//
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// Unlike the S bit in the short descriptors, which implies inner shareable
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// on an implementation that supports two levels, the meaning of the S bit
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// in the TTBR depends on the NOS bit, which defaults to Outer Shareable.
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// However, we should only set this bit after we have confirmed that the
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// implementation supports multiple levels, or else the NOS bit is UNK/SBZP
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//
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if (((ArmReadIdMmfr0 () >> 12) & 0xf) != 0) {
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TTBRAttributes |= TTBR_NOT_OUTER_SHAREABLE;
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}
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}
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}
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ArmCleanInvalidateDataCache ();
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ArmInvalidateInstructionCache ();
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ArmDisableDataCache ();
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ArmDisableInstructionCache();
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// TLBs are also invalidated when calling ArmDisableMmu()
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ArmDisableMmu ();
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// Make sure nothing sneaked into the cache
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ArmCleanInvalidateDataCache ();
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ArmInvalidateInstructionCache ();
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ArmSetTTBR0 ((VOID *)(UINTN)(((UINTN)TranslationTable & ~TRANSLATION_TABLE_SECTION_ALIGNMENT_MASK) | (TTBRAttributes & 0x7F)));
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//
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// The TTBCR register value is undefined at reset in the Non-Secure world.
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// Writing 0 has the effect of:
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// Clearing EAE: Use short descriptors, as mandated by specification.
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// Clearing PD0 and PD1: Translation Table Walk Disable is off.
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// Clearing N: Perform all translation table walks through TTBR0.
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// (0 is the default reset value in systems not implementing
|
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// the Security Extensions.)
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//
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ArmSetTTBCR (0);
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ArmSetDomainAccessControl (DOMAIN_ACCESS_CONTROL_NONE(15) |
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DOMAIN_ACCESS_CONTROL_NONE(14) |
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DOMAIN_ACCESS_CONTROL_NONE(13) |
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DOMAIN_ACCESS_CONTROL_NONE(12) |
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DOMAIN_ACCESS_CONTROL_NONE(11) |
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DOMAIN_ACCESS_CONTROL_NONE(10) |
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DOMAIN_ACCESS_CONTROL_NONE( 9) |
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DOMAIN_ACCESS_CONTROL_NONE( 8) |
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DOMAIN_ACCESS_CONTROL_NONE( 7) |
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DOMAIN_ACCESS_CONTROL_NONE( 6) |
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DOMAIN_ACCESS_CONTROL_NONE( 5) |
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DOMAIN_ACCESS_CONTROL_NONE( 4) |
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DOMAIN_ACCESS_CONTROL_NONE( 3) |
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DOMAIN_ACCESS_CONTROL_NONE( 2) |
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DOMAIN_ACCESS_CONTROL_NONE( 1) |
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DOMAIN_ACCESS_CONTROL_CLIENT(0));
|
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ArmEnableInstructionCache();
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ArmEnableDataCache();
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ArmEnableMmu();
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return RETURN_SUCCESS;
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}
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RETURN_STATUS
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ArmSetMemoryRegionNoExec (
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IN EFI_PHYSICAL_ADDRESS BaseAddress,
|
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IN UINT64 Length
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)
|
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{
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return RETURN_UNSUPPORTED;
|
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}
|
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|
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RETURN_STATUS
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ArmClearMemoryRegionNoExec (
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IN EFI_PHYSICAL_ADDRESS BaseAddress,
|
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IN UINT64 Length
|
||||
)
|
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{
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return RETURN_UNSUPPORTED;
|
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}
|
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|
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RETURN_STATUS
|
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ArmSetMemoryRegionReadOnly (
|
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IN EFI_PHYSICAL_ADDRESS BaseAddress,
|
||||
IN UINT64 Length
|
||||
)
|
||||
{
|
||||
return RETURN_UNSUPPORTED;
|
||||
}
|
||||
|
||||
RETURN_STATUS
|
||||
ArmClearMemoryRegionReadOnly (
|
||||
IN EFI_PHYSICAL_ADDRESS BaseAddress,
|
||||
IN UINT64 Length
|
||||
)
|
||||
{
|
||||
return RETURN_UNSUPPORTED;
|
||||
}
|
||||
|
||||
RETURN_STATUS
|
||||
EFIAPI
|
||||
ArmMmuBaseLibConstructor (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
return RETURN_SUCCESS;
|
||||
}
|
||||
Reference in New Issue
Block a user