ArmPkg: Add ARM Architectural Timer support
ARM Architectural Timer support is defined by the ARM Generic Timer Specification. git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12455 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
275
ArmPkg/Library/ArmLib/ArmV7/ArmV7ArchTimer.c
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275
ArmPkg/Library/ArmLib/ArmV7/ArmV7ArchTimer.c
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@@ -0,0 +1,275 @@
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/** @file
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*
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* Copyright (c) 2011, ARM Limited. All rights reserved.
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*
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* This program and the accompanying materials
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* are licensed and made available under the terms and conditions of the BSD License
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* which accompanies this distribution. The full text of the license may be found at
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* http://opensource.org/licenses/bsd-license.php
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*
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* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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*
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**/
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#include <Uefi.h>
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#include <Chipset/ArmV7.h>
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#include <Library/BaseMemoryLib.h>
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#include <Library/MemoryAllocationLib.h>
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#include <Library/ArmLib.h>
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#include <Library/BaseLib.h>
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#include <Library/DebugLib.h>
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#include "ArmV7Lib.h"
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#include "ArmLibPrivate.h"
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#include <Library/ArmV7ArchTimerLib.h>
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VOID
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EFIAPI
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ArmArchTimerReadReg (
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IN ARM_ARCH_TIMER_REGS Reg,
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OUT VOID *DstBuf
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)
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{
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// Check if the Generic/Architecture timer is implemented
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if (ArmIsArchTimerImplemented ()) {
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switch (Reg) {
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case CntFrq:
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*((UINTN *)DstBuf) = ArmReadCntFrq ();
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break;
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case CntPct:
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*((UINT64 *)DstBuf) = ArmReadCntPct ();
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break;
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case CntkCtl:
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*((UINTN *)DstBuf) = ArmReadCntkCtl();
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break;
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case CntpTval:
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*((UINTN *)DstBuf) = ArmReadCntpTval ();
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break;
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case CntpCtl:
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*((UINTN *)DstBuf) = ArmReadCntpCtl ();
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break;
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case CntvTval:
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*((UINTN *)DstBuf) = ArmReadCntvTval ();
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break;
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case CntvCtl:
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*((UINTN *)DstBuf) = ArmReadCntvCtl ();
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break;
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case CntvCt:
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*((UINT64 *)DstBuf) = ArmReadCntvCt ();
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break;
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case CntpCval:
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*((UINT64 *)DstBuf) = ArmReadCntpCval ();
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break;
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case CntvCval:
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*((UINT64 *)DstBuf) = ArmReadCntvCval ();
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break;
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case CntvOff:
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*((UINT64 *)DstBuf) = ArmReadCntvOff ();
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break;
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case CnthCtl:
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case CnthpTval:
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case CnthpCtl:
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case CnthpCval:
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DEBUG ((EFI_D_ERROR, "The register is related to Hyperviser Mode. Can't perform requested operation\n "));
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break;
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default:
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DEBUG ((EFI_D_ERROR, "Unknown ARM Generic Timer register %x. \n ", Reg));
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}
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} else {
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DEBUG ((EFI_D_ERROR, "Attempt to read ARM Generic Timer registers. But ARM Generic Timer extension is not implemented \n "));
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ASSERT (0);
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}
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}
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VOID
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EFIAPI
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ArmArchTimerWriteReg (
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IN ARM_ARCH_TIMER_REGS Reg,
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IN VOID *SrcBuf
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)
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{
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// Check if the Generic/Architecture timer is implemented
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if (ArmIsArchTimerImplemented ()) {
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switch (Reg) {
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case CntFrq:
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ArmWriteCntFrq (*((UINTN *)SrcBuf));
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break;
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case CntPct:
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DEBUG ((EFI_D_ERROR, "Can't write to Read Only Register: CNTPCT \n"));
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break;
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case CntkCtl:
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ArmWriteCntkCtl (*((UINTN *)SrcBuf));
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break;
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case CntpTval:
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ArmWriteCntpTval (*((UINTN *)SrcBuf));
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break;
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case CntpCtl:
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ArmWriteCntpCtl (*((UINTN *)SrcBuf));
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break;
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case CntvTval:
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ArmWriteCntvTval (*((UINTN *)SrcBuf));
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break;
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case CntvCtl:
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ArmWriteCntvCtl (*((UINTN *)SrcBuf));
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break;
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case CntvCt:
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DEBUG ((EFI_D_ERROR, "Can't write to Read Only Register: CNTVCT \n"));
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break;
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case CntpCval:
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ArmWriteCntpCval (*((UINT64 *)SrcBuf) );
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break;
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case CntvCval:
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ArmWriteCntvCval (*((UINT64 *)SrcBuf) );
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break;
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case CntvOff:
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ArmWriteCntvOff (*((UINT64 *)SrcBuf));
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break;
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case CnthCtl:
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case CnthpTval:
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case CnthpCtl:
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case CnthpCval:
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DEBUG ((EFI_D_ERROR, "The register is related to Hypervisor Mode. Can't perform requested operation\n "));
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break;
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default:
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DEBUG ((EFI_D_ERROR, "Unknown ARM Generic Timer register %x. \n ", Reg));
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}
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} else {
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DEBUG ((EFI_D_ERROR, "Attempt to write to ARM Generic Timer registers. But ARM Generic Timer extension is not implemented \n "));
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ASSERT (0);
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}
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}
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VOID
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EFIAPI
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ArmArchTimerEnableTimer (
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VOID
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)
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{
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UINTN TimerCtrlReg;
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ArmArchTimerReadReg (CntpCtl, (VOID *)&TimerCtrlReg);
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TimerCtrlReg |= ARM_ARCH_TIMER_ENABLE;
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ArmArchTimerWriteReg (CntpCtl, (VOID *)&TimerCtrlReg);
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}
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VOID
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EFIAPI
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ArmArchTimerDisableTimer (
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VOID
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)
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{
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UINTN TimerCtrlReg;
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ArmArchTimerReadReg (CntpCtl, (VOID *)&TimerCtrlReg);
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TimerCtrlReg &= ~ARM_ARCH_TIMER_ENABLE;
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ArmArchTimerWriteReg (CntpCtl, (VOID *)&TimerCtrlReg);
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}
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VOID
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EFIAPI
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ArmArchTimerSetTimerFreq (
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IN UINTN FreqInHz
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)
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{
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ArmArchTimerWriteReg (CntFrq, (VOID *)&FreqInHz);
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}
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UINTN
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EFIAPI
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ArmArchTimerGetTimerFreq (
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VOID
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)
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{
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UINTN ArchTimerFreq = 0;
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ArmArchTimerReadReg (CntFrq, (VOID *)&ArchTimerFreq);
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return ArchTimerFreq;
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}
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UINTN
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EFIAPI
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ArmArchTimerGetTimerVal (
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VOID
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)
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{
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UINTN ArchTimerVal;
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ArmArchTimerReadReg (CntpTval, (VOID *)&ArchTimerVal);
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return ArchTimerVal;
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}
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VOID
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EFIAPI
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ArmArchTimerSetTimerVal (
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IN UINTN Val
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)
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{
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ArmArchTimerWriteReg (CntpTval, (VOID *)&Val);
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}
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UINT64
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EFIAPI
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ArmArchTimerGetSystemCount (
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VOID
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)
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{
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UINT64 SystemCount;
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ArmArchTimerReadReg (CntPct, (VOID *)&SystemCount);
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return SystemCount;
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}
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UINTN
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EFIAPI
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ArmArchTimerGetTimerCtrlReg (
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VOID
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)
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{
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UINTN Val;
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ArmArchTimerReadReg (CntpCtl, (VOID *)&Val);
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return Val;
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}
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VOID
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EFIAPI
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ArmArchTimerSetTimerCtrlReg (
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UINTN Val
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)
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{
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ArmArchTimerWriteReg (CntpCtl, (VOID *)&Val);
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}
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VOID
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EFIAPI
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ArmArchTimerSetCompareVal (
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IN UINT64 Val
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)
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{
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ArmArchTimerWriteReg (CntpCval, (VOID *)&Val);
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}
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119
ArmPkg/Library/ArmLib/ArmV7/ArmV7ArchTimerSupport.S
Normal file
119
ArmPkg/Library/ArmLib/ArmV7/ArmV7ArchTimerSupport.S
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@@ -0,0 +1,119 @@
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#------------------------------------------------------------------------------
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#
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# Copyright (c) 2011, ARM Limited. All rights reserved.
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#
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# This program and the accompanying materials
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# are licensed and made available under the terms and conditions of the BSD License
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# which accompanies this distribution. The full text of the license may be found at
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# http://opensource.org/licenses/bsd-license.php
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#
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# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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#
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#------------------------------------------------------------------------------
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.text
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.align 2
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GCC_ASM_EXPORT (ArmReadCntFrq)
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GCC_ASM_EXPORT (ArmWriteCntFrq)
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GCC_ASM_EXPORT (ArmReadCntPct)
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GCC_ASM_EXPORT (ArmReadCntkCtl)
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GCC_ASM_EXPORT (ArmWriteCntkCtl)
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GCC_ASM_EXPORT (ArmReadCntpTval)
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GCC_ASM_EXPORT (ArmWriteCntpTval)
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GCC_ASM_EXPORT (ArmReadCntpCtl)
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GCC_ASM_EXPORT (ArmWriteCntpCtl)
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GCC_ASM_EXPORT (ArmReadCntvTval)
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GCC_ASM_EXPORT (ArmWriteCntvTval)
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GCC_ASM_EXPORT (ArmReadCntvCtl)
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GCC_ASM_EXPORT (ArmWriteCntvCtl)
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GCC_ASM_EXPORT (ArmReadCntvCt)
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GCC_ASM_EXPORT (ArmReadCntpCval)
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GCC_ASM_EXPORT (ArmWriteCntpCval)
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GCC_ASM_EXPORT (ArmReadCntvCval)
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GCC_ASM_EXPORT (ArmWriteCntvCval)
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GCC_ASM_EXPORT (ArmReadCntvOff)
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GCC_ASM_EXPORT (ArmWriteCntvOff)
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ASM_PFX(ArmReadCntFrq):
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mrc p15, 0, r0, c14, c0, 0 @ Read CNTFRQ
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bx lr
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ASM_PFX(ArmWriteCntFrq):
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mcr p15, 0, r0, c14, c0, 0 @ Write to CNTFRQ
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bx lr
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ASM_PFX(ArmReadCntPct):
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mrrc p15, 0, r0, r1, c14 @ Read CNTPT (Physical counter register)
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bx lr
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ASM_PFX(ArmReadCntkCtl):
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mrc p15, 0, r0, c14, c1, 0 @ Read CNTK_CTL (Timer PL1 Control Register)
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bx lr
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ASM_PFX(ArmWriteCntkCtl):
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mcr p15, 0, r0, c14, c1, 0 @ Write to CNTK_CTL (Timer PL1 Control Register)
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bx lr
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ASM_PFX(ArmReadCntpTval):
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mrc p15, 0, r0, c14, c2, 0 @ Read CNTP_TVAL (PL1 physical timer value register)
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bx lr
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ASM_PFX(ArmWriteCntpTval):
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mcr p15, 0, r0, c14, c2, 0 @ Write to CNTP_TVAL (PL1 physical timer value register)
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bx lr
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ASM_PFX(ArmReadCntpCtl):
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mrc p15, 0, r0, c14, c2, 1 @ Read CNTP_CTL (PL1 Physical Timer Control Register)
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bx lr
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ASM_PFX(ArmWriteCntpCtl):
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mcr p15, 0, r0, c14, c2, 1 @ Write to CNTP_CTL (PL1 Physical Timer Control Register)
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bx lr
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ASM_PFX(ArmReadCntvTval):
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mrc p15, 0, r0, c14, c3, 0 @ Read CNTV_TVAL (Virtual Timer Value register)
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bx lr
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ASM_PFX(ArmWriteCntvTval):
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mcr p15, 0, r0, c14, c3, 0 @ Write to CNTV_TVAL (Virtual Timer Value register)
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bx lr
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ASM_PFX(ArmReadCntvCtl):
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mrc p15, 0, r0, c14, c3, 1 @ Read CNTV_CTL (Virtual Timer Control Register)
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bx lr
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ASM_PFX(ArmWriteCntvCtl):
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mcr p15, 0, r0, c14, c3, 1 @ Write to CNTV_CTL (Virtual Timer Control Register)
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bx lr
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ASM_PFX(ArmReadCntvCt):
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mrrc p15, 1, r0, r1, c14 @ Read CNTVCT (Virtual Count Register)
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bx lr
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ASM_PFX(ArmReadCntpCval):
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mrrc p15, 2, r0, r1, c14 @ Read CNTP_CTVAL (Physical Timer Compare Value Register)
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bx lr
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ASM_PFX(ArmWriteCntpCval):
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mcrr p15, 2, r0, r1, c14 @ Write to CNTP_CTVAL (Physical Timer Compare Value Register)
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bx lr
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ASM_PFX(ArmReadCntvCval):
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mrrc p15, 3, r0, r1, c14 @ Read CNTV_CTVAL (Virtual Timer Compare Value Register)
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bx lr
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ASM_PFX(ArmWriteCntvCval):
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mcrr p15, 3, r0, r1, c14 @ write to CNTV_CTVAL (Virtual Timer Compare Value Register)
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bx lr
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ASM_PFX(ArmReadCntvOff):
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mrrc p15, 4, r0, r1, c14 @ Read CNTVOFF (virtual Offset register)
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bx lr
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ASM_PFX(ArmWriteCntvOff):
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mcrr p15, 4, r0, r1, c14 @ Write to CNTVOFF (Virtual Offset register)
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bx lr
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ASM_FUNCTION_REMOVE_IF_UNREFERENCED
|
119
ArmPkg/Library/ArmLib/ArmV7/ArmV7ArchTimerSupport.asm
Normal file
119
ArmPkg/Library/ArmLib/ArmV7/ArmV7ArchTimerSupport.asm
Normal file
@@ -0,0 +1,119 @@
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//------------------------------------------------------------------------------
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//
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// Copyright (c) 2011, ARM Limited. All rights reserved.
|
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//
|
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// This program and the accompanying materials
|
||||
// are licensed and made available under the terms and conditions of the BSD License
|
||||
// which accompanies this distribution. The full text of the license may be found at
|
||||
// http://opensource.org/licenses/bsd-license.php
|
||||
//
|
||||
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
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//
|
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//------------------------------------------------------------------------------
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EXPORT ArmReadCntFrq
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EXPORT ArmWriteCntFrq
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EXPORT ArmReadCntPct
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EXPORT ArmReadCntkCtl
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EXPORT ArmWriteCntkCtl
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EXPORT ArmReadCntpTval
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EXPORT ArmWriteCntpTval
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EXPORT ArmReadCntpCtl
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EXPORT ArmWriteCntpCtl
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EXPORT ArmReadCntvTval
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EXPORT ArmWriteCntvTval
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EXPORT ArmReadCntvCtl
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EXPORT ArmWriteCntvCtl
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EXPORT ArmReadCntvCt
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EXPORT ArmReadCntpCval
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EXPORT ArmWriteCntpCval
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EXPORT ArmReadCntvCval
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EXPORT ArmWriteCntvCval
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EXPORT ArmReadCntvOff
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EXPORT ArmWriteCntvOff
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AREA ArmV7ArchTimerSupport, CODE, READONLY
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PRESERVE8
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ArmReadCntFrq
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mrc p15, 0, r0, c14, c0, 0 ; Read CNTFRQ
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bx lr
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ArmWriteCntFrq
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mcr p15, 0, r0, c14, c0, 0 ; Write to CNTFRQ
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bx lr
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ArmReadCntPct
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mrrc p15, 0, r0, r1, c14 ; Read CNTPT (Physical counter register)
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bx lr
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ArmReadCntkCtl
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mrc p15, 0, r0, c14, c1, 0 ; Read CNTK_CTL (Timer PL1 Control Register)
|
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bx lr
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|
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ArmWriteCntkCtl
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mcr p15, 0, r0, c14, c1, 0 ; Write to CNTK_CTL (Timer PL1 Control Register)
|
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bx lr
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|
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ArmReadCntpTval
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mrc p15, 0, r0, c14, c2, 0 ; Read CNTP_TVAL (PL1 physical timer value register)
|
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bx lr
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ArmWriteCntpTval
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mcr p15, 0, r0, c14, c2, 0 ; Write to CNTP_TVAL (PL1 physical timer value register)
|
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bx lr
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ArmReadCntpCtl
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mrc p15, 0, r0, c14, c2, 1 ; Read CNTP_CTL (PL1 Physical Timer Control Register)
|
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bx lr
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|
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ArmWriteCntpCtl
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mcr p15, 0, r0, c14, c2, 1 ; Write to CNTP_CTL (PL1 Physical Timer Control Register)
|
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bx lr
|
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|
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ArmReadCntvTval
|
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mrc p15, 0, r0, c14, c3, 0 ; Read CNTV_TVAL (Virtual Timer Value register)
|
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bx lr
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||||
|
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ArmWriteCntvTval
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mcr p15, 0, r0, c14, c3, 0 ; Write to CNTV_TVAL (Virtual Timer Value register)
|
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bx lr
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||||
|
||||
ArmReadCntvCtl
|
||||
mrc p15, 0, r0, c14, c3, 1 ; Read CNTV_CTL (Virtual Timer Control Register)
|
||||
bx lr
|
||||
|
||||
ArmWriteCntvCtl
|
||||
mcr p15, 0, r0, c14, c3, 1 ; Write to CNTV_CTL (Virtual Timer Control Register)
|
||||
bx lr
|
||||
|
||||
ArmReadCntvCt
|
||||
mrrc p15, 1, r0, r1, c14 ; Read CNTVCT (Virtual Count Register)
|
||||
bx lr
|
||||
|
||||
ArmReadCntpCval
|
||||
mrrc p15, 2, r0, r1, c14 ; Read CNTP_CTVAL (Physical Timer Compare Value Register)
|
||||
bx lr
|
||||
|
||||
ArmWriteCntpCval
|
||||
mcrr p15, 2, r0, r1, c14 ; Write to CNTP_CTVAL (Physical Timer Compare Value Register)
|
||||
bx lr
|
||||
|
||||
ArmReadCntvCval
|
||||
mrrc p15, 3, r0, r1, c14 ; Read CNTV_CTVAL (Virtual Timer Compare Value Register)
|
||||
bx lr
|
||||
|
||||
ArmWriteCntvCval
|
||||
mcrr p15, 3, r0, r1, c14 ; write to CNTV_CTVAL (Virtual Timer Compare Value Register)
|
||||
bx lr
|
||||
|
||||
ArmReadCntvOff
|
||||
mrrc p15, 4, r0, r1, c14 ; Read CNTVOFF (virtual Offset register)
|
||||
bx lr
|
||||
|
||||
ArmWriteCntvOff
|
||||
mcrr p15, 4, r0, r1, c14 ; Write to CNTVOFF (Virtual Offset register)
|
||||
bx lr
|
||||
|
||||
END
|
@@ -35,6 +35,10 @@
|
||||
ArmV7Lib.c
|
||||
ArmV7Mmu.c
|
||||
|
||||
ArmV7ArchTimer.c
|
||||
ArmV7ArchTimerSupport.S | GCC
|
||||
ArmV7ArchTimerSupport.asm | RVCT
|
||||
|
||||
[Packages]
|
||||
ArmPkg/ArmPkg.dec
|
||||
MdePkg/MdePkg.dec
|
||||
|
@@ -34,6 +34,10 @@
|
||||
|
||||
ArmV7Lib.c
|
||||
ArmV7Mmu.c
|
||||
|
||||
ArmV7ArchTimer.c
|
||||
ArmV7ArchTimerSupport.S | GCC
|
||||
ArmV7ArchTimerSupport.asm | RVCT
|
||||
|
||||
[Packages]
|
||||
ArmPkg/ArmPkg.dec
|
||||
|
@@ -31,6 +31,10 @@
|
||||
ArmV7Support.asm | RVCT
|
||||
|
||||
ArmV7Lib.c
|
||||
|
||||
ArmV7ArchTimer.c
|
||||
ArmV7ArchTimerSupport.S | GCC
|
||||
ArmV7ArchTimerSupport.asm | RVCT
|
||||
|
||||
[Packages]
|
||||
ArmPkg/ArmPkg.dec
|
||||
|
Reference in New Issue
Block a user