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OvmfPkg/LegacyRegion: Support legacy region manipulation of Q35

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Current implementation only supports legacy region of 440 chip.
When QEMU is launched in Q35 mode using CSM enabled OVMF image,
LegacyBios driver fails to start due to the legacy region
[0xC0000, 0xFFFFF] cannot be written.

v2:
 * just updates the comments.

v3:
 * uses PcdOvmfHostBridgePciDevId as Jordan suggested.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
Cc: Justen Jordan <jordan.l.justen@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
This commit is contained in:
Ruiyu Ni
2016-03-15 16:10:40 +08:00
committed by Jordan Justen
parent 89a811538e
commit db27e9f3d8
2 changed files with 87 additions and 39 deletions
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26
OvmfPkg/Csm/CsmSupportLib/LegacyRegion.h
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@@ -1,7 +1,7 @@
/** @file
Legacy Region Support
Copyright (c) 2008 - 2011, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2008 - 2016, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials are
licensed and made available under the terms and conditions of the BSD License
@@ -21,6 +21,8 @@
#include <Protocol/LegacyRegion2.h>
#include <IndustryStandard/Pci.h>
#include <IndustryStandard/Q35MchIch9.h>
#include <IndustryStandard/I440FxPiix4.h>
#include <Library/PciLib.h>
#include <Library/PcdLib.h>
@@ -32,13 +34,21 @@
#define PAM_PCI_DEV 0
#define PAM_PCI_FUNC 0
#define REG_PAM0_OFFSET 0x59 // Programmable Attribute Map 0
#define REG_PAM1_OFFSET 0x5a // Programmable Attribute Map 1
#define REG_PAM2_OFFSET 0x5b // Programmable Attribute Map 2
#define REG_PAM3_OFFSET 0x5c // Programmable Attribute Map 3
#define REG_PAM4_OFFSET 0x5d // Programmable Attribute Map 4
#define REG_PAM5_OFFSET 0x5e // Programmable Attribute Map 5
#define REG_PAM6_OFFSET 0x5f // Programmable Attribute Map 6
#define REG_PAM0_OFFSET_440 0x59 // Programmable Attribute Map 0
#define REG_PAM1_OFFSET_440 0x5a // Programmable Attribute Map 1
#define REG_PAM2_OFFSET_440 0x5b // Programmable Attribute Map 2
#define REG_PAM3_OFFSET_440 0x5c // Programmable Attribute Map 3
#define REG_PAM4_OFFSET_440 0x5d // Programmable Attribute Map 4
#define REG_PAM5_OFFSET_440 0x5e // Programmable Attribute Map 5
#define REG_PAM6_OFFSET_440 0x5f // Programmable Attribute Map 6
#define REG_PAM0_OFFSET_Q35 0x90 // Programmable Attribute Map 0
#define REG_PAM1_OFFSET_Q35 0x91 // Programmable Attribute Map 1
#define REG_PAM2_OFFSET_Q35 0x92 // Programmable Attribute Map 2
#define REG_PAM3_OFFSET_Q35 0x93 // Programmable Attribute Map 3
#define REG_PAM4_OFFSET_Q35 0x94 // Programmable Attribute Map 4
#define REG_PAM5_OFFSET_Q35 0x95 // Programmable Attribute Map 5
#define REG_PAM6_OFFSET_Q35 0x96 // Programmable Attribute Map 6
#define PAM_BASE_ADDRESS 0xc0000
#define PAM_LIMIT_ADDRESS BASE_1MB