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MdePkg/Baseib: Filter/trace MSR access for IA32/X64

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REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3246

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Signed-off-by: Dandan Bi <dandan.bi@intel.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
Acked-by: Ard Biesheuvel <ardb@kernel.org>
This commit is contained in:
Dandan Bi
2021-03-12 18:05:07 +08:00
committed by mergify[bot]
parent 38c8be123a
commit dc4d42302c
7 changed files with 129 additions and 43 deletions
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36
MdePkg/Library/BaseLib/Ia32/GccInlinePriv.c
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@@ -2,7 +2,7 @@
GCC inline implementation of BaseLib processor specific functions that use
privlidged instructions.
Copyright (c) 2006 - 2020, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.<BR>
Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -10,6 +10,7 @@
#include "BaseLibInternals.h"
#include <Library/RegisterFilterLib.h>
/**
Enables CPU interrupts.
@@ -63,12 +64,17 @@ AsmReadMsr64 (
)
{
UINT64 Data;
BOOLEAN Flag;
__asm__ __volatile__ (
"rdmsr"
: "=A" (Data) // %0
: "c" (Index) // %1
);
Flag = FilterBeforeMsrRead (Index, &Data);
if (Flag) {
__asm__ __volatile__ (
"rdmsr"
: "=A" (Data) // %0
: "c" (Index) // %1
);
}
FilterAfterMsrRead (Index, &Data);
return Data;
}
@@ -97,12 +103,18 @@ AsmWriteMsr64 (
IN UINT64 Value
)
{
__asm__ __volatile__ (
"wrmsr"
:
: "c" (Index),
"A" (Value)
);
BOOLEAN Flag;
Flag = FilterBeforeMsrWrite (Index, &Value);
if (Flag) {
__asm__ __volatile__ (
"wrmsr"
:
: "c" (Index),
"A" (Value)
);
}
FilterAfterMsrWrite (Index, &Value);
return Value;
}