MdePkg/Baseib: Filter/trace MSR access for IA32/X64

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3246

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Signed-off-by: Dandan Bi <dandan.bi@intel.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
Acked-by: Ard Biesheuvel <ardb@kernel.org>
This commit is contained in:
Dandan Bi
2021-03-12 18:05:07 +08:00
committed by mergify[bot]
parent 38c8be123a
commit dc4d42302c
7 changed files with 129 additions and 43 deletions

View File

@@ -2,7 +2,7 @@
GCC inline implementation of BaseLib processor specific functions that use
privlidged instructions.
Copyright (c) 2006 - 2020, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.<BR>
Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -10,6 +10,7 @@
#include "BaseLibInternals.h"
#include <Library/RegisterFilterLib.h>
/**
Enables CPU interrupts.
@@ -64,13 +65,20 @@ AsmReadMsr64 (
{
UINT32 LowData;
UINT32 HighData;
UINT64 Value;
BOOLEAN Flag;
__asm__ __volatile__ (
"rdmsr"
: "=a" (LowData), // %0
"=d" (HighData) // %1
: "c" (Index) // %2
);
Flag = FilterBeforeMsrRead (Index, &Value);
if (Flag) {
__asm__ __volatile__ (
"rdmsr"
: "=a" (LowData), // %0
"=d" (HighData) // %1
: "c" (Index) // %2
);
Value = (((UINT64)HighData) << 32) | LowData;
}
FilterAfterMsrRead (Index, &Value);
return (((UINT64)HighData) << 32) | LowData;
}
@@ -101,17 +109,22 @@ AsmWriteMsr64 (
{
UINT32 LowData;
UINT32 HighData;
BOOLEAN Flag;
LowData = (UINT32)(Value);
HighData = (UINT32)(Value >> 32);
__asm__ __volatile__ (
"wrmsr"
:
: "c" (Index),
"a" (LowData),
"d" (HighData)
);
Flag = FilterBeforeMsrWrite (Index, &Value);
if (Flag) {
__asm__ __volatile__ (
"wrmsr"
:
: "c" (Index),
"a" (LowData),
"d" (HighData)
);
}
FilterAfterMsrWrite (Index, &Value);
return Value;
}