UefiCpuPkg/CpuExceptionHandlerLib: Trim white space at end of line
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com>
This commit is contained in:
@@ -357,7 +357,7 @@ HasErrorCode:
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#
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# Put Vector Number on stack and restore ECX
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#
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xchgl (%esp), %ecx
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xchgl (%esp), %ecx
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ErrorCodeAndVectorOnStack:
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pushl %ebp
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@@ -384,13 +384,13 @@ ErrorCodeAndVectorOnStack:
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# Align stack to make sure that EFI_FX_SAVE_STATE_IA32 of EFI_SYSTEM_CONTEXT_IA32
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# is 16-byte aligned
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#
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andl $0x0fffffff0, %esp
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andl $0x0fffffff0, %esp
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subl $12, %esp
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subl $8, %esp
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pushl $0 # check EXCEPTION_HANDLER_CONTEXT.OldIdtHandler
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pushl $0 # check EXCEPTION_HANDLER_CONTEXT.ExceptionDataFlag
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#; UINT32 Edi, Esi, Ebp, Esp, Ebx, Edx, Ecx, Eax;
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pushl %eax
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pushl %ecx
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@@ -405,7 +405,7 @@ ErrorCodeAndVectorOnStack:
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#; UINT32 Gs, Fs, Es, Ds, Cs, Ss;
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movl %ss, %eax
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pushl %eax
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movzwl 16(%ebp), %eax
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movzwl 16(%ebp), %eax
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pushl %eax
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movl %ds, %eax
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pushl %eax
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@@ -425,14 +425,14 @@ ErrorCodeAndVectorOnStack:
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sidt (%esp)
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movl 2(%esp), %eax
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xchgl (%esp), %eax
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andl $0x0FFFF, %eax
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andl $0x0FFFF, %eax
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movl %eax, 4(%esp)
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subl $8, %esp
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sgdt (%esp)
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movl 2(%esp), %eax
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xchgl (%esp), %eax
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andl $0x0FFFF, %eax
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andl $0x0FFFF, %eax
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movl %eax, 4(%esp)
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#; UINT32 Ldtr, Tr;
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@@ -450,21 +450,21 @@ ErrorCodeAndVectorOnStack:
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## insure FXSAVE/FXRSTOR is enabled in CR4...
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## ... while we're at it, make sure DE is also enabled...
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mov $1, %eax
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pushl %ebx # temporarily save value of ebx on stack
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pushl %ebx # temporarily save value of ebx on stack
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cpuid # use CPUID to determine if FXSAVE/FXRESTOR
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# and DE are supported
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popl %ebx # retore value of ebx that was overwritten
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# by CPUID
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# by CPUID
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movl %cr4, %eax
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pushl %eax # push cr4 firstly
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testl $BIT24, %edx # Test for FXSAVE/FXRESTOR support
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jz L1
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orl $BIT9, %eax # Set CR4.OSFXSR
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L1:
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L1:
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testl $BIT2, %edx # Test for Debugging Extensions support
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jz L2
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orl $BIT3, %eax # Set CR4.DE
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L2:
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L2:
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movl %eax, %cr4
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movl %cr3, %eax
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pushl %eax
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@@ -492,11 +492,11 @@ L2:
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#; FX_SAVE_STATE_IA32 FxSaveState;
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subl $512, %esp
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movl %esp, %edi
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testl $BIT24, %edx # Test for FXSAVE/FXRESTOR support.
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testl $BIT24, %edx # Test for FXSAVE/FXRESTOR support.
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# edx still contains result from CPUID above
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jz L3
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.byte 0x0f, 0x0ae, 0x07 #fxsave [edi]
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L3:
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L3:
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#; UEFI calling convention for IA32 requires that Direction flag in EFLAGs is clear
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cld
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@@ -523,12 +523,12 @@ L3:
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#; FX_SAVE_STATE_IA32 FxSaveState;
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movl %esp, %esi
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movl $1, %eax
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cpuid # use CPUID to determine if FXSAVE/FXRESTOR
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cpuid # use CPUID to determine if FXSAVE/FXRESTOR
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# are supported
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testl $BIT24, %edx # Test for FXSAVE/FXRESTOR support
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jz L4
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.byte 0x0f, 0x0ae, 0x0e # fxrstor [esi]
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L4:
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L4:
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addl $512, %esp
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#; UINT32 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
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@@ -612,30 +612,30 @@ DoIret:
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#---------------------------------------;
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# _AsmGetTemplateAddressMap ;
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#---------------------------------------;
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#
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#
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# Protocol prototype
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# AsmGetTemplateAddressMap (
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# EXCEPTION_HANDLER_TEMPLATE_MAP *AddressMap
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# );
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#
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#
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# Routine Description:
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#
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#
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# Return address map of interrupt handler template so that C code can generate
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# interrupt table.
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#
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#
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# Arguments:
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#
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#
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# Returns:
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#
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#
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#
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# Returns:
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#
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# Nothing
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#
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#
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#
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# Input: [ebp][0] = Original ebp
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# [ebp][4] = Return address
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#
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#
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# Output: Nothing
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#
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#
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# Destroys: Nothing
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#-----------------------------------------------------------------------------;
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#-------------------------------------------------------------------------------------
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