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Import some basic libraries instances for Mde Packages.

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git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@2704 6f19259b-4bc3-4df7-8a09-765794883524
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vanjeff
2007-06-22 03:21:45 +00:00
parent e053747a04
commit e1f414b6a7
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101
MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf Normal file
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#/** @file
# Component description file for Base Cache Maintenance Library
#
# Cache Maintenance Library that uses Base Library services to maintain caches.
# This library assumes there are no chipset dependencies required to maintain caches.
# Copyright (c) 2007 - 2007, Intel Corporation
#
# All rights reserved. This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#
#**/
################################################################################
#
# Defines Section - statements that will be processed to create a Makefile.
#
################################################################################
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = BaseCacheMaintenanceLib
FILE_GUID = 123dd843-57c9-4158-8418-ce68b3944ce7
MODULE_TYPE = BASE
VERSION_STRING = 1.0
LIBRARY_CLASS = CacheMaintenanceLib
EDK_RELEASE_VERSION = 0x00020000
EFI_SPECIFICATION_VERSION = 0x00020000
#
# The following information is for reference only and not required by the build tools.
#
# VALID_ARCHITECTURES = IA32 X64 IPF EBC
#
################################################################################
#
# Sources Section - list of files that are required for the build to succeed.
#
################################################################################
[Sources.common]
CommonHeader.h
[Sources.Ia32]
x86Cache.c
[Sources.X64]
x86Cache.c
[Sources.IPF]
IpfCache.c
[Sources.EBC]
EbcCache.c
################################################################################
#
# Includes Section - list of Include locations that are required for
# this module.
#
################################################################################
[Includes]
$(WORKSPACE)/MdePkg\Include/Library
################################################################################
#
# Package Dependency Section - list of Package files that are required for
# this module.
#
################################################################################
[Packages]
MdePkg/MdePkg.dec
################################################################################
#
# Library Class Section - list of Library Classes that are required for
# this module.
#
################################################################################
[LibraryClasses]
DebugLib
[LibraryClasses.IA32]
BaseLib
[LibraryClasses.X64]
BaseLib
[LibraryClasses.IPF]
BaseLib

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MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.msa Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<ModuleSurfaceArea xmlns="http://www.TianoCore.org/2006/Edk2.0" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<MsaHeader>
<ModuleName>BaseCacheMaintenanceLib</ModuleName>
<ModuleType>BASE</ModuleType>
<GuidValue>123dd843-57c9-4158-8418-ce68b3944ce7</GuidValue>
<Version>1.0</Version>
<Abstract>Component description file for Base Cache Maintenance Library</Abstract>
<Description>Cache Maintenance Library that uses Base Library services to maintain caches.
This library assumes there are no chipset dependencies required to maintain caches.</Description>
<Copyright>Copyright (c) 2006 - 2007, Intel Corporation</Copyright>
<License>All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.</License>
<Specification>FRAMEWORK_BUILD_PACKAGING_SPECIFICATION 0x00000052</Specification>
</MsaHeader>
<ModuleDefinitions>
<SupportedArchitectures>IA32 X64 IPF EBC</SupportedArchitectures>
<BinaryModule>false</BinaryModule>
<OutputFileBasename>BaseCacheMaintenanceLib</OutputFileBasename>
</ModuleDefinitions>
<LibraryClassDefinitions>
<LibraryClass Usage="ALWAYS_PRODUCED">
<Keyword>CacheMaintenanceLib</Keyword>
</LibraryClass>
<LibraryClass Usage="ALWAYS_CONSUMED" SupArchList="IA32 X64 IPF">
<Keyword>BaseLib</Keyword>
</LibraryClass>
<LibraryClass Usage="ALWAYS_CONSUMED">
<Keyword>DebugLib</Keyword>
</LibraryClass>
</LibraryClassDefinitions>
<SourceFiles>
<Filename SupArchList="IA32">x86Cache.c</Filename>
<Filename SupArchList="X64">x86Cache.c</Filename>
<Filename SupArchList="EBC">EbcCache.c</Filename>
<Filename SupArchList="IPF">IpfCache.c</Filename>
</SourceFiles>
<PackageDependencies>
<Package PackageGuid="5e0e9358-46b6-4ae2-8218-4ab8b9bbdcec"/>
</PackageDependencies>
<Externs>
<Specification>EFI_SPECIFICATION_VERSION 0x00020000</Specification>
<Specification>EDK_RELEASE_VERSION 0x00020000</Specification>
</Externs>
</ModuleSurfaceArea>

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MdePkg/Library/BaseCacheMaintenanceLib/CommonHeader.h Normal file
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/**@file
Common header file shared by all source files.
This file includes package header files, library classes and protocol, PPI & GUID definitions.
Copyright (c) 2007 - 2007, Intel Corporation
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef __COMMON_HEADER_H_
#define __COMMON_HEADER_H_
//
// The package level header files this module uses
//
#include <Base.h>
//
// The protocols, PPI and GUID defintions for this module
//
//
// The Library classes this module consumes
//
#include <Library/CacheMaintenanceLib.h>
#include <Library/BaseLib.h>
#include <Library/DebugLib.h>
#endif

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MdePkg/Library/BaseCacheMaintenanceLib/EbcCache.c Normal file
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/** @file
Cache Maintenance Functions.
Copyright (c) 2006, Intel Corporation<BR>
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
//
// Include common header file for this module.
//
#include "CommonHeader.h"
/**
Invalidates the entire instruction cache in cache coherency domain of the
calling CPU.
Invalidates the entire instruction cache in cache coherency domain of the
calling CPU.
**/
VOID
EFIAPI
InvalidateInstructionCache (
VOID
)
{
}
/**
Invalidates a range of instruction cache lines in the cache coherency domain
of the calling CPU.
Invalidates the instruction cache lines specified by Address and Length. If
Address is not aligned on a cache line boundary, then entire instruction
cache line containing Address is invalidated. If Address + Length is not
aligned on a cache line boundary, then the entire instruction cache line
containing Address + Length -1 is invalidated. This function may choose to
invalidate the entire instruction cache if that is more efficient than
invalidating the specified range. If Length is 0, the no instruction cache
lines are invalidated. Address is returned.
If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
@param Address The base address of the instruction cache lines to
invalidate. If the CPU is in a physical addressing mode, then
Address is a physical address. If the CPU is in a virtual
addressing mode, then Address is a virtual address.
@param Length The number of bytes to invalidate from the instruction cache.
@return Address
**/
VOID *
EFIAPI
InvalidateInstructionCacheRange (
IN VOID *Address,
IN UINTN Length
)
{
ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);
return Address;
}
/**
Writes Back and Invalidates the entire data cache in cache coherency domain
of the calling CPU.
Writes Back and Invalidates the entire data cache in cache coherency domain
of the calling CPU. This function guarantees that all dirty cache lines are
written back to system memory, and also invalidates all the data cache lines
in the cache coherency domain of the calling CPU.
**/
VOID
EFIAPI
WriteBackInvalidateDataCache (
VOID
)
{
}
/**
Writes Back and Invalidates a range of data cache lines in the cache
coherency domain of the calling CPU.
Writes Back and Invalidate the data cache lines specified by Address and
Length. If Address is not aligned on a cache line boundary, then entire data
cache line containing Address is written back and invalidated. If Address +
Length is not aligned on a cache line boundary, then the entire data cache
line containing Address + Length -1 is written back and invalidated. This
function may choose to write back and invalidate the entire data cache if
that is more efficient than writing back and invalidating the specified
range. If Length is 0, the no data cache lines are written back and
invalidated. Address is returned.
If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
@param Address The base address of the data cache lines to write back and
invalidate. If the CPU is in a physical addressing mode, then
Address is a physical address. If the CPU is in a virtual
addressing mode, then Address is a virtual address.
@param Length The number of bytes to write back and invalidate from the
data cache.
@return Address
**/
VOID *
EFIAPI
WriteBackInvalidateDataCacheRange (
IN VOID *Address,
IN UINTN Length
)
{
ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);
return Address;
}
/**
Writes Back the entire data cache in cache coherency domain of the calling
CPU.
Writes Back the entire data cache in cache coherency domain of the calling
CPU. This function guarantees that all dirty cache lines are written back to
system memory. This function may also invalidate all the data cache lines in
the cache coherency domain of the calling CPU.
**/
VOID
EFIAPI
WriteBackDataCache (
VOID
)
{
}
/**
Writes Back a range of data cache lines in the cache coherency domain of the
calling CPU.
Writes Back the data cache lines specified by Address and Length. If Address
is not aligned on a cache line boundary, then entire data cache line
containing Address is written back. If Address + Length is not aligned on a
cache line boundary, then the entire data cache line containing Address +
Length -1 is written back. This function may choose to write back the entire
data cache if that is more efficient than writing back the specified range.
If Length is 0, the no data cache lines are written back. This function may
also invalidate all the data cache lines in the specified range of the cache
coherency domain of the calling CPU. Address is returned.
If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
@param Address The base address of the data cache lines to write back. If
the CPU is in a physical addressing mode, then Address is a
physical address. If the CPU is in a virtual addressing
mode, then Address is a virtual address.
@param Length The number of bytes to write back from the data cache.
@return Address
**/
VOID *
EFIAPI
WriteBackDataCacheRange (
IN VOID *Address,
IN UINTN Length
)
{
ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);
return Address;
}
/**
Invalidates the entire data cache in cache coherency domain of the calling
CPU.
Invalidates the entire data cache in cache coherency domain of the calling
CPU. This function must be used with care because dirty cache lines are not
written back to system memory. It is typically used for cache diagnostics. If
the CPU does not support invalidation of the entire data cache, then a write
back and invalidate operation should be performed on the entire data cache.
**/
VOID
EFIAPI
InvalidateDataCache (
VOID
)
{
}
/**
Invalidates a range of data cache lines in the cache coherency domain of the
calling CPU.
Invalidates the data cache lines specified by Address and Length. If Address
is not aligned on a cache line boundary, then entire data cache line
containing Address is invalidated. If Address + Length is not aligned on a
cache line boundary, then the entire data cache line containing Address +
Length -1 is invalidated. This function must never invalidate any cache lines
outside the specified range. If Length is 0, the no data cache lines are
invalidated. Address is returned. This function must be used with care
because dirty cache lines are not written back to system memory. It is
typically used for cache diagnostics. If the CPU does not support
invalidation of a data cache range, then a write back and invalidate
operation should be performed on the data cache range.
If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
@param Address The base address of the data cache lines to invalidate. If
the CPU is in a physical addressing mode, then Address is a
physical address. If the CPU is in a virtual addressing mode,
then Address is a virtual address.
@param Length The number of bytes to invalidate from the data cache.
@return Address
**/
VOID *
EFIAPI
InvalidateDataCacheRange (
IN VOID *Address,
IN UINTN Length
)
{
ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);
return Address;
}

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MdePkg/Library/BaseCacheMaintenanceLib/IpfCache.c Normal file
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/** @file
Cache Maintenance Functions.
Copyright (c) 2006, Intel Corporation<BR>
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
//
// Include common header file for this module.
//
#include "CommonHeader.h"
/**
Invalidates the entire instruction cache in cache coherency domain of the
calling CPU.
Invalidates the entire instruction cache in cache coherency domain of the
calling CPU.
**/
VOID
EFIAPI
InvalidateInstructionCache (
VOID
)
{
PalCallStatic (NULL, 1, 1, 1, 0);
}
/**
Invalidates a range of instruction cache lines in the cache coherency domain
of the calling CPU.
Invalidates the instruction cache lines specified by Address and Length. If
Address is not aligned on a cache line boundary, then entire instruction
cache line containing Address is invalidated. If Address + Length is not
aligned on a cache line boundary, then the entire instruction cache line
containing Address + Length -1 is invalidated. This function may choose to
invalidate the entire instruction cache if that is more efficient than
invalidating the specified range. If Length is 0, the no instruction cache
lines are invalidated. Address is returned.
If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
@param Address The base address of the instruction cache lines to
invalidate. If the CPU is in a physical addressing mode, then
Address is a physical address. If the CPU is in a virtual
addressing mode, then Address is a virtual address.
@param Length The number of bytes to invalidate from the instruction cache.
@return Address
**/
VOID *
EFIAPI
InvalidateInstructionCacheRange (
IN VOID *Address,
IN UINTN Length
)
{
return IpfFlushCacheRange (Address, Length);
}
/**
Writes Back and Invalidates the entire data cache in cache coherency domain
of the calling CPU.
Writes Back and Invalidates the entire data cache in cache coherency domain
of the calling CPU. This function guarantees that all dirty cache lines are
written back to system memory, and also invalidates all the data cache lines
in the cache coherency domain of the calling CPU.
**/
VOID
EFIAPI
WriteBackInvalidateDataCache (
VOID
)
{
PalCallStatic (NULL, 1, 2, 1, 0);
}
/**
Writes Back and Invalidates a range of data cache lines in the cache
coherency domain of the calling CPU.
Writes Back and Invalidate the data cache lines specified by Address and
Length. If Address is not aligned on a cache line boundary, then entire data
cache line containing Address is written back and invalidated. If Address +
Length is not aligned on a cache line boundary, then the entire data cache
line containing Address + Length -1 is written back and invalidated. This
function may choose to write back and invalidate the entire data cache if
that is more efficient than writing back and invalidating the specified
range. If Length is 0, the no data cache lines are written back and
invalidated. Address is returned.
If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
@param Address The base address of the data cache lines to write back and
invalidate. If the CPU is in a physical addressing mode, then
Address is a physical address. If the CPU is in a virtual
addressing mode, then Address is a virtual address.
@param Length The number of bytes to write back and invalidate from the
data cache.
@return Address
**/
VOID *
EFIAPI
WriteBackInvalidateDataCacheRange (
IN VOID *Address,
IN UINTN Length
)
{
ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);
return IpfFlushCacheRange (Address, Length);
}
/**
Writes Back the entire data cache in cache coherency domain of the calling
CPU.
Writes Back the entire data cache in cache coherency domain of the calling
CPU. This function guarantees that all dirty cache lines are written back to
system memory. This function may also invalidate all the data cache lines in
the cache coherency domain of the calling CPU.
**/
VOID
EFIAPI
WriteBackDataCache (
VOID
)
{
PalCallStatic (NULL, 1, 2, 0, 0);
}
/**
Writes Back a range of data cache lines in the cache coherency domain of the
calling CPU.
Writes Back the data cache lines specified by Address and Length. If Address
is not aligned on a cache line boundary, then entire data cache line
containing Address is written back. If Address + Length is not aligned on a
cache line boundary, then the entire data cache line containing Address +
Length -1 is written back. This function may choose to write back the entire
data cache if that is more efficient than writing back the specified range.
If Length is 0, the no data cache lines are written back. This function may
also invalidate all the data cache lines in the specified range of the cache
coherency domain of the calling CPU. Address is returned.
If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
@param Address The base address of the data cache lines to write back. If
the CPU is in a physical addressing mode, then Address is a
physical address. If the CPU is in a virtual addressing
mode, then Address is a virtual address.
@param Length The number of bytes to write back from the data cache.
@return Address
**/
VOID *
EFIAPI
WriteBackDataCacheRange (
IN VOID *Address,
IN UINTN Length
)
{
ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);
return IpfFlushCacheRange (Address, Length);
}
/**
Invalidates the entire data cache in cache coherency domain of the calling
CPU.
Invalidates the entire data cache in cache coherency domain of the calling
CPU. This function must be used with care because dirty cache lines are not
written back to system memory. It is typically used for cache diagnostics. If
the CPU does not support invalidation of the entire data cache, then a write
back and invalidate operation should be performed on the entire data cache.
**/
VOID
EFIAPI
InvalidateDataCache (
VOID
)
{
WriteBackInvalidateDataCache ();
}
/**
Invalidates a range of data cache lines in the cache coherency domain of the
calling CPU.
Invalidates the data cache lines specified by Address and Length. If Address
is not aligned on a cache line boundary, then entire data cache line
containing Address is invalidated. If Address + Length is not aligned on a
cache line boundary, then the entire data cache line containing Address +
Length -1 is invalidated. This function must never invalidate any cache lines
outside the specified range. If Length is 0, the no data cache lines are
invalidated. Address is returned. This function must be used with care
because dirty cache lines are not written back to system memory. It is
typically used for cache diagnostics. If the CPU does not support
invalidation of a data cache range, then a write back and invalidate
operation should be performed on the data cache range.
If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
@param Address The base address of the data cache lines to invalidate. If
the CPU is in a physical addressing mode, then Address is a
physical address. If the CPU is in a virtual addressing mode,
then Address is a virtual address.
@param Length The number of bytes to invalidate from the data cache.
@return Address
**/
VOID *
EFIAPI
InvalidateDataCacheRange (
IN VOID *Address,
IN UINTN Length
)
{
return IpfFlushCacheRange (Address, Length);
}

259
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/** @file
Cache Maintenance Functions.
Copyright (c) 2006, Intel Corporation<BR>
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
Module Name: x86Cache.c
**/
//
// Include common header file for this module.
//
#include "CommonHeader.h"
//
// This size must be at or below the smallest cache size possible among all
// supported processors
//
#define CACHE_LINE_SIZE 0x20
/**
Invalidates the entire instruction cache in cache coherency domain of the
calling CPU.
Invalidates the entire instruction cache in cache coherency domain of the
calling CPU.
**/
VOID
EFIAPI
InvalidateInstructionCache (
VOID
)
{
}
/**
Invalidates a range of instruction cache lines in the cache coherency domain
of the calling CPU.
Invalidates the instruction cache lines specified by Address and Length. If
Address is not aligned on a cache line boundary, then entire instruction
cache line containing Address is invalidated. If Address + Length is not
aligned on a cache line boundary, then the entire instruction cache line
containing Address + Length -1 is invalidated. This function may choose to
invalidate the entire instruction cache if that is more efficient than
invalidating the specified range. If Length is 0, the no instruction cache
lines are invalidated. Address is returned.
If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
@param Address The base address of the instruction cache lines to
invalidate. If the CPU is in a physical addressing mode, then
Address is a physical address. If the CPU is in a virtual
addressing mode, then Address is a virtual address.
@param Length The number of bytes to invalidate from the instruction cache.
@return Address
**/
VOID *
EFIAPI
InvalidateInstructionCacheRange (
IN VOID *Address,
IN UINTN Length
)
{
ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);
return Address;
}
/**
Writes Back and Invalidates the entire data cache in cache coherency domain
of the calling CPU.
Writes Back and Invalidates the entire data cache in cache coherency domain
of the calling CPU. This function guarantees that all dirty cache lines are
written back to system memory, and also invalidates all the data cache lines
in the cache coherency domain of the calling CPU.
**/
VOID
EFIAPI
WriteBackInvalidateDataCache (
VOID
)
{
AsmWbinvd ();
}
/**
Writes Back and Invalidates a range of data cache lines in the cache
coherency domain of the calling CPU.
Writes Back and Invalidate the data cache lines specified by Address and
Length. If Address is not aligned on a cache line boundary, then entire data
cache line containing Address is written back and invalidated. If Address +
Length is not aligned on a cache line boundary, then the entire data cache
line containing Address + Length -1 is written back and invalidated. This
function may choose to write back and invalidate the entire data cache if
that is more efficient than writing back and invalidating the specified
range. If Length is 0, the no data cache lines are written back and
invalidated. Address is returned.
If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
@param Address The base address of the data cache lines to write back and
invalidate. If the CPU is in a physical addressing mode, then
Address is a physical address. If the CPU is in a virtual
addressing mode, then Address is a virtual address.
@param Length The number of bytes to write back and invalidate from the
data cache.
@return Address
**/
VOID *
EFIAPI
WriteBackInvalidateDataCacheRange (
IN VOID *Address,
IN UINTN Length
)
{
UINTN Start, End;
ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);
if (Length == 0) {
return Address;
}
Start = (UINTN)Address;
End = (Start + Length + (CACHE_LINE_SIZE - 1)) & ~(CACHE_LINE_SIZE - 1);
Start &= ~(CACHE_LINE_SIZE - 1);
do {
Start = (UINTN)AsmFlushCacheLine ((VOID*)Start) + CACHE_LINE_SIZE;
} while (Start != End);
return Address;
}
/**
Writes Back the entire data cache in cache coherency domain of the calling
CPU.
Writes Back the entire data cache in cache coherency domain of the calling
CPU. This function guarantees that all dirty cache lines are written back to
system memory. This function may also invalidate all the data cache lines in
the cache coherency domain of the calling CPU.
**/
VOID
EFIAPI
WriteBackDataCache (
VOID
)
{
WriteBackInvalidateDataCache ();
}
/**
Writes Back a range of data cache lines in the cache coherency domain of the
calling CPU.
Writes Back the data cache lines specified by Address and Length. If Address
is not aligned on a cache line boundary, then entire data cache line
containing Address is written back. If Address + Length is not aligned on a
cache line boundary, then the entire data cache line containing Address +
Length -1 is written back. This function may choose to write back the entire
data cache if that is more efficient than writing back the specified range.
If Length is 0, the no data cache lines are written back. This function may
also invalidate all the data cache lines in the specified range of the cache
coherency domain of the calling CPU. Address is returned.
If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
@param Address The base address of the data cache lines to write back. If
the CPU is in a physical addressing mode, then Address is a
physical address. If the CPU is in a virtual addressing
mode, then Address is a virtual address.
@param Length The number of bytes to write back from the data cache.
@return Address
**/
VOID *
EFIAPI
WriteBackDataCacheRange (
IN VOID *Address,
IN UINTN Length
)
{
return WriteBackInvalidateDataCacheRange (Address, Length);
}
/**
Invalidates the entire data cache in cache coherency domain of the calling
CPU.
Invalidates the entire data cache in cache coherency domain of the calling
CPU. This function must be used with care because dirty cache lines are not
written back to system memory. It is typically used for cache diagnostics. If
the CPU does not support invalidation of the entire data cache, then a write
back and invalidate operation should be performed on the entire data cache.
**/
VOID
EFIAPI
InvalidateDataCache (
VOID
)
{
AsmInvd ();
}
/**
Invalidates a range of data cache lines in the cache coherency domain of the
calling CPU.
Invalidates the data cache lines specified by Address and Length. If Address
is not aligned on a cache line boundary, then entire data cache line
containing Address is invalidated. If Address + Length is not aligned on a
cache line boundary, then the entire data cache line containing Address +
Length -1 is invalidated. This function must never invalidate any cache lines
outside the specified range. If Length is 0, the no data cache lines are
invalidated. Address is returned. This function must be used with care
because dirty cache lines are not written back to system memory. It is
typically used for cache diagnostics. If the CPU does not support
invalidation of a data cache range, then a write back and invalidate
operation should be performed on the data cache range.
If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
@param Address The base address of the data cache lines to invalidate. If
the CPU is in a physical addressing mode, then Address is a
physical address. If the CPU is in a virtual addressing mode,
then Address is a virtual address.
@param Length The number of bytes to invalidate from the data cache.
@return Address
**/
VOID *
EFIAPI
InvalidateDataCacheRange (
IN VOID *Address,
IN UINTN Length
)
{
return WriteBackInvalidateDataCacheRange (Address, Length);
}

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#/** @file
# Component description file for NULL Debug Library
#
# Debug Library with empty functions.
# Copyright (c) 2007 - 2007, Intel Corporation.
#
# All rights reserved. This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#
#**/
################################################################################
#
# Defines Section - statements that will be processed to create a Makefile.
#
################################################################################
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = BaseDebugLibNull
FILE_GUID = 9ba1d976-0624-41a3-8650-28165e8d9ae8
MODULE_TYPE = BASE
VERSION_STRING = 1.0
LIBRARY_CLASS = DebugLib
EDK_RELEASE_VERSION = 0x00020000
EFI_SPECIFICATION_VERSION = 0x00020000
#
# The following information is for reference only and not required by the build tools.
#
# VALID_ARCHITECTURES = IA32 X64 IPF EBC
#
################################################################################
#
# Sources Section - list of files that are required for the build to succeed.
#
################################################################################
[Sources.common]
DebugLib.c
CommonHeader.h
################################################################################
#
# Includes Section - list of Include locations that are required for
# this module.
#
################################################################################
[Includes]
################################################################################
#
# Package Dependency Section - list of Package files that are required for
# this module.
#
################################################################################
[Packages]
MdePkg/MdePkg.dec

39
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<?xml version="1.0" encoding="UTF-8"?>
<ModuleSurfaceArea xmlns="http://www.TianoCore.org/2006/Edk2.0" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<MsaHeader>
<ModuleName>BaseDebugLibNull</ModuleName>
<ModuleType>BASE</ModuleType>
<GuidValue>9ba1d976-0624-41a3-8650-28165e8d9ae8</GuidValue>
<Version>1.0</Version>
<Abstract>Component description file for NULL Debug Library</Abstract>
<Description>Debug Library with empty functions.</Description>
<Copyright>Copyright (c) 2006 - 2007, Intel Corporation.</Copyright>
<License>All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.</License>
<Specification>FRAMEWORK_BUILD_PACKAGING_SPECIFICATION 0x00000052</Specification>
</MsaHeader>
<ModuleDefinitions>
<SupportedArchitectures>IA32 X64 IPF EBC</SupportedArchitectures>
<BinaryModule>false</BinaryModule>
<OutputFileBasename>BaseDebugLibNull</OutputFileBasename>
</ModuleDefinitions>
<LibraryClassDefinitions>
<LibraryClass Usage="ALWAYS_PRODUCED">
<Keyword>DebugLib</Keyword>
</LibraryClass>
</LibraryClassDefinitions>
<SourceFiles>
<Filename>DebugLib.c</Filename>
</SourceFiles>
<PackageDependencies>
<Package PackageGuid="5e0e9358-46b6-4ae2-8218-4ab8b9bbdcec"/>
</PackageDependencies>
<Externs>
<Specification>EFI_SPECIFICATION_VERSION 0x00020000</Specification>
<Specification>EDK_RELEASE_VERSION 0x00020000</Specification>
</Externs>
</ModuleSurfaceArea>

31
MdePkg/Library/BaseDebugLibNull/CommonHeader.h Normal file
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/**@file
Common header file shared by all source files.
This file includes package header files, library classes and protocol, PPI & GUID definitions.
Copyright (c) 2007 - 2007, Intel Corporation.
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef __COMMON_HEADER_H_
#define __COMMON_HEADER_H_
//
// The package level header files this module uses
//
#include <Base.h>
//
// The protocols, PPI and GUID defintions for this module
//
//
// The Library classes this module consumes
//
#include <Library/DebugLib.h>
#endif

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/** @file
Base Debug Library that uses PrintLib to print messages to a memory buffer.
Copyright (c) 2006, Intel Corporation
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
//
// Include common header file for this module.
//
#include "CommonHeader.h"
/**
Prints a debug message to the debug output device if the specified error level is enabled.
If any bit in ErrorLevel is also set in PcdDebugPrintErrorLevel, then print
the message specified by Format and the associated variable argument list to
the debug output device.
If Format is NULL, then ASSERT().
@param ErrorLevel The error level of the debug message.
@param Format Format string for the debug message to print.
**/
VOID
EFIAPI
DebugPrint (
IN UINTN ErrorLevel,
IN CONST CHAR8 *Format,
...
)
{
}
/**
Prints an assert message containing a filename, line number, and description.
This may be followed by a breakpoint or a dead loop.
Print a message of the form "ASSERT <FileName>(<LineNumber>): <Description>\n"
to the debug output device. If DEBUG_PROPERTY_ASSERT_BREAKPOINT_ENABLED bit of
PcdDebugProperyMask is set then CpuBreakpoint() is called. Otherwise, if
DEBUG_PROPERTY_ASSERT_DEADLOOP_ENABLED bit of PcdDebugProperyMask is set then
CpuDeadLoop() is called. If neither of these bits are set, then this function
returns immediately after the message is printed to the debug output device.
DebugAssert() must actively prevent recusrsion. If DebugAssert() is called while
processing another DebugAssert(), then DebugAssert() must return immediately.
If FileName is NULL, then a <FileName> string of "(NULL) Filename" is printed.
If Description is NULL, then a <Description> string of "(NULL) Description" is printed.
@param FileName Pointer to the name of the source file that generated the assert condition.
@param LineNumber The line number in the source file that generated the assert condition
@param Description Pointer to the description of the assert condition.
**/
VOID
EFIAPI
DebugAssert (
IN CONST CHAR8 *FileName,
IN UINTN LineNumber,
IN CONST CHAR8 *Description
)
{
}
/**
Fills a target buffer with PcdDebugClearMemoryValue, and returns the target buffer.
This function fills Length bytes of Buffer with the value specified by
PcdDebugClearMemoryValue, and returns Buffer.
If Buffer is NULL, then ASSERT().
If Length is greater than (MAX_ADDRESS ? Buffer + 1), then ASSERT().
@param Buffer Pointer to the target buffer to fill with PcdDebugClearMemoryValue.
@param Length Number of bytes in Buffer to fill with zeros PcdDebugClearMemoryValue.
@return Buffer
**/
VOID *
EFIAPI
DebugClearMemory (
OUT VOID *Buffer,
IN UINTN Length
)
{
return Buffer;
}
/**
Returns TRUE if ASSERT() macros are enabled.
This function returns TRUE if the DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED bit of
PcdDebugProperyMask is set. Otherwise FALSE is returned.
@retval TRUE The DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED bit of PcdDebugProperyMask is set.
@retval FALSE The DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED bit of PcdDebugProperyMask is clear.
**/
BOOLEAN
EFIAPI
DebugAssertEnabled (
VOID
)
{
return FALSE;
}
/**
Returns TRUE if DEBUG()macros are enabled.
This function returns TRUE if the DEBUG_PROPERTY_DEBUG_PRINT_ENABLED bit of
PcdDebugProperyMask is set. Otherwise FALSE is returned.
@retval TRUE The DEBUG_PROPERTY_DEBUG_PRINT_ENABLED bit of PcdDebugProperyMask is set.
@retval FALSE The DEBUG_PROPERTY_DEBUG_PRINT_ENABLED bit of PcdDebugProperyMask is clear.
**/
BOOLEAN
EFIAPI
DebugPrintEnabled (
VOID
)
{
return FALSE;
}
/**
Returns TRUE if DEBUG_CODE()macros are enabled.
This function returns TRUE if the DEBUG_PROPERTY_DEBUG_CODE_ENABLED bit of
PcdDebugProperyMask is set. Otherwise FALSE is returned.
@retval TRUE The DEBUG_PROPERTY_DEBUG_CODE_ENABLED bit of PcdDebugProperyMask is set.
@retval FALSE The DEBUG_PROPERTY_DEBUG_CODE_ENABLED bit of PcdDebugProperyMask is clear.
**/
BOOLEAN
EFIAPI
DebugCodeEnabled (
VOID
)
{
return FALSE;
}
/**
Returns TRUE if DEBUG_CLEAR_MEMORY()macro is enabled.
This function returns TRUE if the DEBUG_PROPERTY_DEBUG_CLEAR_MEMORY_ENABLED bit of
PcdDebugProperyMask is set. Otherwise FALSE is returned.
@retval TRUE The DEBUG_PROPERTY_DEBUG_CLEAR_MEMORY_ENABLED bit of PcdDebugProperyMask is set.
@retval FALSE The DEBUG_PROPERTY_DEBUG_CLEAR_MEMORY_ENABLED bit of PcdDebugProperyMask is clear.
**/
BOOLEAN
EFIAPI
DebugClearMemoryEnabled (
VOID
)
{
return FALSE;
}

111
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#/** @file
# Component description file for Intrinsic Base Io Library
#
# I/O Library that uses compiler intrinsics to perform IN and OUT instructions
# for IA-32 and x64. It also performs direct memory access for MMIO services.
# Copyright (c) 2007 - 2007, Intel Corporation.
#
# All rights reserved. This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#
#**/
################################################################################
#
# Defines Section - statements that will be processed to create a Makefile.
#
################################################################################
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = BaseIoLibIntrinsic
FILE_GUID = 926c9cd0-4bb8-479b-9ac4-8a2a23f85307
MODULE_TYPE = BASE
VERSION_STRING = 1.0
LIBRARY_CLASS = IoLib
EDK_RELEASE_VERSION = 0x00020000
EFI_SPECIFICATION_VERSION = 0x00020000
#
# The following information is for reference only and not required by the build tools.
#
# VALID_ARCHITECTURES = IA32 X64 IPF
#
################################################################################
#
# Sources Section - list of files that are required for the build to succeed.
#
################################################################################
[Sources.common]
IoLibMmioBuffer.c
CommonHeader.h
[Sources.Ia32]
IoHighLevel.c
IoLibGcc.c
IoLibMsc.c
IoLib.c
[Sources.X64]
IoHighLevel.c
IoLibGcc.c
IoLibMsc.c
IoLib.c
[Sources.IPF]
IoHighLevel.c
IoLibIpf.c
################################################################################
#
# Includes Section - list of Include locations that are required for
# this module.
#
################################################################################
[Includes]
$(WORKSPACE)/MdePkg\Include/Library
################################################################################
#
# Package Dependency Section - list of Package files that are required for
# this module.
#
################################################################################
[Packages]
MdePkg/MdePkg.dec
################################################################################
#
# Library Class Section - list of Library Classes that are required for
# this module.
#
################################################################################
[LibraryClasses]
DebugLib
BaseLib
[LibraryClasses.IPF]
PcdLib
################################################################################
#
# Pcd FIXED_AT_BUILD - list of PCDs that this module is coded for.
#
################################################################################
[PcdsFixedAtBuild.IPF]
PcdIoBlockBaseAddressForIpf|gEfiMdePkgTokenSpaceGuid

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<?xml version="1.0" encoding="UTF-8"?>
<ModuleSurfaceArea xmlns="http://www.TianoCore.org/2006/Edk2.0" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<MsaHeader>
<ModuleName>BaseIoLibIntrinsic</ModuleName>
<ModuleType>BASE</ModuleType>
<GuidValue>926c9cd0-4bb8-479b-9ac4-8a2a23f85307</GuidValue>
<Version>1.0</Version>
<Abstract>Component description file for Intrinsic Base Io Library</Abstract>
<Description>I/O Library that uses compiler intrinsics to perform IN and OUT instructions
for IA-32 and x64. It also performs direct memory access for MMIO services.</Description>
<Copyright>Copyright (c) 2006 - 2007, Intel Corporation.</Copyright>
<License>All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.</License>
<Specification>FRAMEWORK_BUILD_PACKAGING_SPECIFICATION 0x00000052</Specification>
</MsaHeader>
<ModuleDefinitions>
<SupportedArchitectures>IA32 X64 IPF</SupportedArchitectures>
<BinaryModule>false</BinaryModule>
<OutputFileBasename>BaseIoLibIntrinsic</OutputFileBasename>
</ModuleDefinitions>
<LibraryClassDefinitions>
<LibraryClass Usage="ALWAYS_PRODUCED">
<Keyword>IoLib</Keyword>
</LibraryClass>
<LibraryClass Usage="ALWAYS_CONSUMED">
<Keyword>BaseLib</Keyword>
</LibraryClass>
<LibraryClass Usage="ALWAYS_CONSUMED">
<Keyword>DebugLib</Keyword>
</LibraryClass>
<LibraryClass Usage="ALWAYS_CONSUMED" SupArchList="IPF">
<Keyword>PcdLib</Keyword>
</LibraryClass>
</LibraryClassDefinitions>
<SourceFiles>
<Filename>IoLibMmioBuffer.c</Filename>
<Filename SupArchList="IA32">IoLib.c</Filename>
<Filename SupArchList="IA32" ToolChainFamily="MSFT">IoLibMsc.c</Filename>
<Filename SupArchList="IA32" ToolChainFamily="GCC">IoLibGcc.c</Filename>
<Filename SupArchList="IA32">IoHighLevel.c</Filename>
<Filename SupArchList="X64">IoLib.c</Filename>
<Filename SupArchList="X64" ToolChainFamily="MSFT">IoLibMsc.c</Filename>
<Filename SupArchList="X64" ToolChainFamily="GCC">IoLibGcc.c</Filename>
<Filename SupArchList="X64">IoHighLevel.c</Filename>
<Filename SupArchList="IPF">IoLibIpf.c</Filename>
<Filename SupArchList="IPF">IoHighLevel.c</Filename>
</SourceFiles>
<PackageDependencies>
<Package PackageGuid="5e0e9358-46b6-4ae2-8218-4ab8b9bbdcec"/>
</PackageDependencies>
<Externs>
<Specification>EFI_SPECIFICATION_VERSION 0x00020000</Specification>
<Specification>EDK_RELEASE_VERSION 0x00020000</Specification>
</Externs>
<PcdCoded>
<PcdEntry PcdItemType="FIXED_AT_BUILD" Usage="ALWAYS_CONSUMED" SupArchList="IPF">
<C_Name>PcdIoBlockBaseAddressForIpf</C_Name>
<TokenSpaceGuidCName>gEfiMdePkgTokenSpaceGuid</TokenSpaceGuidCName>
<DefaultValue>0x0ffffc000000</DefaultValue>
<HelpText>The base address of IPF IO Block</HelpText>
</PcdEntry>
</PcdCoded>
</ModuleSurfaceArea>

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MdePkg/Library/BaseIoLibIntrinsic/CommonHeader.h Normal file
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/**@file
Common header file shared by all source files.
This file includes package header files, library classes and protocol, PPI & GUID definitions.
Copyright (c) 2007 - 2007, Intel Corporation.
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef __COMMON_HEADER_H_
#define __COMMON_HEADER_H_
//
// The package level header files this module uses
//
#include <Base.h>
//
// The protocols, PPI and GUID defintions for this module
//
//
// The Library classes this module consumes
//
#include <Library/IoLib.h>
#include <Library/BaseLib.h>
#include <Library/DebugLib.h>
#include <Library/PcdLib.h>
#endif

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71
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/** @file
Common I/O Library routines.
Copyright (c) 2006, Intel Corporation<BR>
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
Module Name: IoLib.c
**/
//
// Include common header file for this module.
//
#include "CommonHeader.h"
/**
Reads a 64-bit I/O port.
Reads the 64-bit I/O port specified by Port. The 64-bit read value is returned.
This function must guarantee that all I/O read and write operations are
serialized.
If 64-bit I/O port operations are not supported, then ASSERT().
@param Port The I/O port to read.
@return The value read.
**/
UINT64
EFIAPI
IoRead64 (
IN UINTN Port
)
{
ASSERT (FALSE);
return 0;
}
/**
Writes a 64-bit I/O port.
Writes the 64-bit I/O port specified by Port with the value specified by Value
and returns Value. This function must guarantee that all I/O read and write
operations are serialized.
If 64-bit I/O port operations are not supported, then ASSERT().
@param Port The I/O port to write.
@param Value The value to write to the I/O port.
@return The value written the I/O port.
**/
UINT64
EFIAPI
IoWrite64 (
IN UINTN Port,
IN UINT64 Value
)
{
ASSERT (FALSE);
return 0;
}

388
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/** @file
I/O Library. This file has compiler specifics for GCC as there is no
ANSI C standard for doing IO.
GCC - uses EFIAPI assembler. __asm__ calls GAS. __volatile__ makes sure the
compiler puts the assembler in this exact location. The complex GNUC
operations are not optimzed. It would be possible to also write these
with EFIAPI assembler.
We don't advocate putting compiler specifics in libraries or drivers but there
is no other way to make this work.
Copyright (c) 2006 - 2007, Intel Corporation<BR>
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
Module Name: IoLibGcc.c
**/
//
// Include common header file for this module.
//
#include "CommonHeader.h"
/**
Reads an 8-bit MMIO register.
Reads the 8-bit MMIO register specified by Address. The 8-bit read value is
returned. This function must guarantee that all MMIO read and write
operations are serialized.
If 8-bit MMIO register operations are not supported, then ASSERT().
@param Address The MMIO register to read.
@return The value read.
**/
UINT8
EFIAPI
MmioRead8 (
IN UINTN Address
)
{
return *(volatile UINT8*)Address;
}
/**
Writes an 8-bit MMIO register.
Writes the 8-bit MMIO register specified by Address with the value specified
by Value and returns Value. This function must guarantee that all MMIO read
and write operations are serialized.
If 8-bit MMIO register operations are not supported, then ASSERT().
@param Address The MMIO register to write.
@param Value The value to write to the MMIO register.
**/
UINT8
EFIAPI
MmioWrite8 (
IN UINTN Address,
IN UINT8 Value
)
{
return *(volatile UINT8*)Address = Value;
}
/**
Reads a 16-bit MMIO register.
Reads the 16-bit MMIO register specified by Address. The 16-bit read value is
returned. This function must guarantee that all MMIO read and write
operations are serialized.
If 16-bit MMIO register operations are not supported, then ASSERT().
@param Address The MMIO register to read.
@return The value read.
**/
UINT16
EFIAPI
MmioRead16 (
IN UINTN Address
)
{
ASSERT ((Address & 1) == 0);
return *(volatile UINT16*)Address;
}
/**
Writes a 16-bit MMIO register.
Writes the 16-bit MMIO register specified by Address with the value specified
by Value and returns Value. This function must guarantee that all MMIO read
and write operations are serialized.
If 16-bit MMIO register operations are not supported, then ASSERT().
@param Address The MMIO register to write.
@param Value The value to write to the MMIO register.
**/
UINT16
EFIAPI
MmioWrite16 (
IN UINTN Address,
IN UINT16 Value
)
{
ASSERT ((Address & 1) == 0);
return *(volatile UINT16*)Address = Value;
}
/**
Reads a 32-bit MMIO register.
Reads the 32-bit MMIO register specified by Address. The 32-bit read value is
returned. This function must guarantee that all MMIO read and write
operations are serialized.
If 32-bit MMIO register operations are not supported, then ASSERT().
@param Address The MMIO register to read.
@return The value read.
**/
UINT32
EFIAPI
MmioRead32 (
IN UINTN Address
)
{
ASSERT ((Address & 3) == 0);
return *(volatile UINT32*)Address;
}
/**
Writes a 32-bit MMIO register.
Writes the 32-bit MMIO register specified by Address with the value specified
by Value and returns Value. This function must guarantee that all MMIO read
and write operations are serialized.
If 32-bit MMIO register operations are not supported, then ASSERT().
@param Address The MMIO register to write.
@param Value The value to write to the MMIO register.
**/
UINT32
EFIAPI
MmioWrite32 (
IN UINTN Address,
IN UINT32 Value
)
{
ASSERT ((Address & 3) == 0);
return *(volatile UINT32*)Address = Value;
}
/**
Reads a 64-bit MMIO register.
Reads the 64-bit MMIO register specified by Address. The 64-bit read value is
returned. This function must guarantee that all MMIO read and write
operations are serialized.
If 64-bit MMIO register operations are not supported, then ASSERT().
@param Address The MMIO register to read.
@return The value read.
**/
UINT64
EFIAPI
MmioRead64 (
IN UINTN Address
)
{
ASSERT ((Address & 7) == 0);
return *(volatile UINT64*)Address;
}
/**
Writes a 64-bit MMIO register.
Writes the 64-bit MMIO register specified by Address with the value specified
by Value and returns Value. This function must guarantee that all MMIO read
and write operations are serialized.
If 64-bit MMIO register operations are not supported, then ASSERT().
@param Address The MMIO register to write.
@param Value The value to write to the MMIO register.
**/
UINT64
EFIAPI
MmioWrite64 (
IN UINTN Address,
IN UINT64 Value
)
{
ASSERT ((Address & 7) == 0);
return *(volatile UINT64*)Address = Value;
}
/**
Reads an 8-bit I/O port.
Reads the 8-bit I/O port specified by Port. The 8-bit read value is returned.
This function must guarantee that all I/O read and write operations are
serialized.
If 8-bit I/O port operations are not supported, then ASSERT().
@param Port The I/O port to read.
@return The value read.
**/
__inline__
UINT8
EFIAPI
IoRead8 (
IN UINTN Port
)
{
UINT8 Data;
__asm__ __volatile__ ("inb %w1,%b0" : "=a" (Data) : "d" ((UINT16)Port));
return Data;
}
/**
Writes an 8-bit I/O port.
Writes the 8-bit I/O port specified by Port with the value specified by Value
and returns Value. This function must guarantee that all I/O read and write
operations are serialized.
If 8-bit I/O port operations are not supported, then ASSERT().
@param Port The I/O port to write.
@param Value The value to write to the I/O port.
@return The value written the I/O port.
**/
__inline__
UINT8
EFIAPI
IoWrite8 (
IN UINTN Port,
IN UINT8 Value
)
{
__asm__ __volatile__ ("outb %b0,%w1" : : "a" (Value), "d" ((UINT16)Port));
return Value;;
}
/**
Reads a 16-bit I/O port.
Reads the 16-bit I/O port specified by Port. The 16-bit read value is returned.
This function must guarantee that all I/O read and write operations are
serialized.
If 16-bit I/O port operations are not supported, then ASSERT().
@param Port The I/O port to read.
@return The value read.
**/
__inline__
UINT16
EFIAPI
IoRead16 (
IN UINTN Port
)
{
UINT16 Data;
ASSERT ((Port & 1) == 0);
__asm__ __volatile__ ("inw %w1,%w0" : "=a" (Data) : "d" ((UINT16)Port));
return Data;
}
/**
Writes a 16-bit I/O port.
Writes the 16-bit I/O port specified by Port with the value specified by Value
and returns Value. This function must guarantee that all I/O read and write
operations are serialized.
If 16-bit I/O port operations are not supported, then ASSERT().
@param Port The I/O port to write.
@param Value The value to write to the I/O port.
@return The value written the I/O port.
**/
__inline__
UINT16
EFIAPI
IoWrite16 (
IN UINTN Port,
IN UINT16 Value
)
{
ASSERT ((Port & 1) == 0);
__asm__ __volatile__ ("outw %w0,%w1" : : "a" (Value), "d" ((UINT16)Port));
return Value;;
}
/**
Reads a 32-bit I/O port.
Reads the 32-bit I/O port specified by Port. The 32-bit read value is returned.
This function must guarantee that all I/O read and write operations are
serialized.
If 32-bit I/O port operations are not supported, then ASSERT().
@param Port The I/O port to read.
@return The value read.
**/
__inline__
UINT32
EFIAPI
IoRead32 (
IN UINTN Port
)
{
UINT32 Data;
ASSERT ((Port & 3) == 0);
__asm__ __volatile__ ("inl %w1,%0" : "=a" (Data) : "d" ((UINT16)Port));
return Data;
}
/**
Writes a 32-bit I/O port.
Writes the 32-bit I/O port specified by Port with the value specified by Value
and returns Value. This function must guarantee that all I/O read and write
operations are serialized.
If 32-bit I/O port operations are not supported, then ASSERT().
@param Port The I/O port to write.
@param Value The value to write to the I/O port.
@return The value written the I/O port.
**/
__inline__
UINT32
EFIAPI
IoWrite32 (
IN UINTN Port,
IN UINT32 Value
)
{
ASSERT ((Port & 3) == 0);
__asm__ __volatile__ ("outl %0,%w1" : : "a" (Value), "d" ((UINT16)Port));
return Value;
}

486
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/** @file
Common I/O Library routines.
Copyright (c) 2006 - 2007, Intel Corporation<BR>
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
Module Name: IoLibIpf.c
**/
//
// Include common header file for this module.
//
#include "CommonHeader.h"
#define MAP_PORT_BASE_TO_MEM(_Port) \
((((_Port) & 0xfffc) << 10) | ((_Port) & 0x0fff))
/**
Reads a 8-bit I/O port.
Reads the 8-bit I/O port specified by Port. The 8-bit read value is returned.
This function must guarantee that all I/O read and write operations are
serialized.
@param Port The I/O port to read.
@return The value read.
**/
UINT8
EFIAPI
IoRead8 (
IN UINT64 Port
)
{
UINT64 Address;
//
// Add the 64MB aligned IO Port space to the IO address
//
Address = MAP_PORT_BASE_TO_MEM (Port);
Address += PcdGet64(PcdIoBlockBaseAddressForIpf);
return MmioRead8 (Address);
}
/**
Reads a 16-bit I/O port.
Reads the 16-bit I/O port specified by Port. The 16-bit read value is returned.
This function must guarantee that all I/O read and write operations are
serialized.
@param Port The I/O port to read.
@return The value read.
**/
UINT16
EFIAPI
IoRead16 (
IN UINT64 Port
)
{
UINT64 Address;
//
// Add the 64MB aligned IO Port space to the IO address
//
Address = MAP_PORT_BASE_TO_MEM (Port);
Address += PcdGet64(PcdIoBlockBaseAddressForIpf);
return MmioRead16 (Address);
}
/**
Reads a 32-bit I/O port.
Reads the 32-bit I/O port specified by Port. The 32-bit read value is returned.
This function must guarantee that all I/O read and write operations are
serialized.
@param Port The I/O port to read.
@return The value read.
**/
UINT32
EFIAPI
IoRead32 (
IN UINT64 Port
)
{
UINT64 Address;
//
// Add the 64MB aligned IO Port space to the IO address
//
Address = MAP_PORT_BASE_TO_MEM (Port);
Address += PcdGet64(PcdIoBlockBaseAddressForIpf);
return MmioRead32 (Address);
}
/**
Reads a 64-bit I/O port.
Reads the 64-bit I/O port specified by Port. The 64-bit read value is returned.
This function must guarantee that all I/O read and write operations are
serialized.
If 64-bit I/O port operations are not supported, then ASSERT().
@param Port The I/O port to read.
@return The value read.
**/
UINT64
EFIAPI
IoRead64 (
IN UINTN Port
)
{
ASSERT (FALSE);
return 0;
}
/**
Writes a 8-bit I/O port.
Writes the 8-bit I/O port specified by Port with the value specified by Value
and returns Value. This function must guarantee that all I/O read and write
operations are serialized.
@param Port The I/O port to write.
@param Value The value to write to the I/O port.
@return The value written the I/O port.
**/
UINT8
EFIAPI
IoWrite8 (
IN UINT64 Port,
IN UINT8 Data
)
{
UINT64 Address;
//
// Add the 64MB aligned IO Port space to the IO address
//
Address = MAP_PORT_BASE_TO_MEM (Port);
Address += PcdGet64(PcdIoBlockBaseAddressForIpf);
return MmioWrite8 (Address, Data);
}
/**
Writes a 16-bit I/O port.
Writes the 16-bit I/O port specified by Port with the value specified by Value
and returns Value. This function must guarantee that all I/O read and write
operations are serialized.
@param Port The I/O port to write.
@param Value The value to write to the I/O port.
@return The value written the I/O port.
**/
UINT16
EFIAPI
IoWrite16 (
IN UINT64 Port,
IN UINT16 Data
)
{
UINT64 Address;
//
// Add the 64MB aligned IO Port space to the IO address
//
Address = MAP_PORT_BASE_TO_MEM (Port);
Address += PcdGet64(PcdIoBlockBaseAddressForIpf);
return MmioWrite16 (Address, Data);
}
/**
Writes a 32-bit I/O port.
Writes the 32-bit I/O port specified by Port with the value specified by Value
and returns Value. This function must guarantee that all I/O read and write
operations are serialized.
@param Port The I/O port to write.
@param Value The value to write to the I/O port.
@return The value written the I/O port.
**/
UINT32
EFIAPI
IoWrite32 (
IN UINT64 Port,
IN UINT32 Data
)
{
UINT64 Address;
//
// Add the 64MB aligned IO Port space to the IO address
//
Address = MAP_PORT_BASE_TO_MEM (Port);
Address += PcdGet64(PcdIoBlockBaseAddressForIpf);
return MmioWrite32 (Address, Data);
}
/**
Writes a 64-bit I/O port.
Writes the 64-bit I/O port specified by Port with the value specified by Value
and returns Value. This function must guarantee that all I/O read and write
operations are serialized.
If 64-bit I/O port operations are not supported, then ASSERT().
@param Port The I/O port to write.
@param Value The value to write to the I/O port.
@return The value written the I/O port.
**/
UINT64
EFIAPI
IoWrite64 (
IN UINTN Port,
IN UINT64 Value
)
{
ASSERT (FALSE);
return 0;
}
/**
Reads a 8-bit MMIO register.
Reads the 8-bit MMIO register specified by Address. The 8-bit read value is
returned. This function must guarantee that all MMIO read and write
operations are serialized.
@param Address The MMIO register to read.
@return The value read.
**/
UINT8
EFIAPI
MmioRead8 (
IN UINT64 Address
)
{
UINT8 Data;
Address |= BIT63;
MemoryFence ();
Data = *((volatile UINT8 *) Address);
MemoryFence ();
return Data;
}
/**
Reads a 16-bit MMIO register.
Reads the 16-bit MMIO register specified by Address. The 16-bit read value is
returned. This function must guarantee that all MMIO read and write
operations are serialized.
@param Address The MMIO register to read.
@return The value read.
**/
UINT16
EFIAPI
MmioRead16 (
IN UINT64 Address
)
{
UINT16 Data;
Address |= BIT63;
MemoryFence ();
Data = *((volatile UINT16 *) Address);
MemoryFence ();
return Data;
}
/**
Reads a 32-bit MMIO register.
Reads the 32-bit MMIO register specified by Address. The 32-bit read value is
returned. This function must guarantee that all MMIO read and write
operations are serialized.
@param Address The MMIO register to read.
@return The value read.
**/
UINT32
EFIAPI
MmioRead32 (
IN UINT64 Address
)
{
UINT32 Data;
Address |= BIT63;
MemoryFence ();
Data = *((volatile UINT32 *) Address);
MemoryFence ();
return Data;
}
/**
Reads a 64-bit MMIO register.
Reads the 64-bit MMIO register specified by Address. The 64-bit read value is
returned. This function must guarantee that all MMIO read and write
operations are serialized.
@param Address The MMIO register to read.
@return The value read.
**/
UINT64
EFIAPI
MmioRead64 (
IN UINT64 Address
)
{
UINT64 Data;
Address |= BIT63;
MemoryFence ();
Data = *((volatile UINT64 *) Address);
MemoryFence ();
return Data;
}
/**
Writes a 8-bit MMIO register.
Writes the 8-bit MMIO register specified by Address with the value specified
by Value and returns Value. This function must guarantee that all MMIO read
and write operations are serialized.
@param Address The MMIO register to write.
@param Data The value to write to the MMIO register.
@return The value written the memory address.
**/
UINT8
EFIAPI
MmioWrite8 (
IN UINT64 Address,
IN UINT8 Data
)
{
Address |= BIT63;
MemoryFence ();
*((volatile UINT8 *) Address) = Data;
MemoryFence ();
return Data;
}
/**
Writes a 16-bit MMIO register.
Writes the 16-bit MMIO register specified by Address with the value specified
by Value and returns Value. This function must guarantee that all MMIO read
and write operations are serialized.
@param Address The MMIO register to write.
@param Data The value to write to the MMIO register.
@return The value written the memory address.
**/
UINT16
EFIAPI
MmioWrite16 (
IN UINT64 Address,
IN UINT16 Data
)
{
Address |= BIT63;
MemoryFence ();
*((volatile UINT16 *) Address) = Data;
MemoryFence ();
return Data;
}
/**
Writes a 32-bit MMIO register.
Writes the 32-bit MMIO register specified by Address with the value specified
by Value and returns Value. This function must guarantee that all MMIO read
and write operations are serialized.
@param Address The MMIO register to write.
@param Data The value to write to the MMIO register.
@return The value written the memory address.
**/
UINT32
EFIAPI
MmioWrite32 (
IN UINT64 Address,
IN UINT32 Data
)
{
Address |= BIT63;
MemoryFence ();
*((volatile UINT32 *) Address) = Data;
MemoryFence ();
return Data;
}
/**
Writes a 64-bit MMIO register.
Writes the 64-bit MMIO register specified by Address with the value specified
by Value and returns Value. This function must guarantee that all MMIO read
and write operations are serialized.
@param Address The MMIO register to write.
@param Data The value to write to the MMIO register.
@return The value written the memory address.
**/
UINT64
EFIAPI
MmioWrite64 (
IN UINT64 Address,
IN UINT64 Data
)
{
Address |= BIT63;
MemoryFence ();
*((volatile UINT64 *) Address) = Data;
MemoryFence ();
return Data;
}

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/** @file
I/O Library MMIO Buffer Functions.
Copyright (c) 2007, Intel Corporation<BR>
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
//
// Include common header file for this module.
//
#include "CommonHeader.h"
/**
Copy data from MMIO region to system memory by using 8-bit access.
Copy data from MMIO region specified by starting address StartAddress
to system memory specified by Buffer by using 8-bit access. The total
number of byte to be copied is specified by Length. Buffer is returned.
If Length is greater than (MAX_ADDRESS - StartAddress + 1), then ASSERT().
If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT().
@param StartAddress Starting address for the MMIO region to be copied from.
@param Length Size in bytes of the copy.
@param Buffer Pointer to a system memory buffer receiving the data read.
@return Buffer
**/
UINT8 *
EFIAPI
MmioReadBuffer8 (
IN UINTN StartAddress,
IN UINTN Length,
OUT UINT8 *Buffer
)
{
UINT8 *ReturnBuffer;
ASSERT ((Length - 1) <= (MAX_ADDRESS - StartAddress));
ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN) Buffer));
ReturnBuffer = Buffer;
while (Length--) {
*(Buffer++) = MmioRead8 (StartAddress++);
}
return ReturnBuffer;
}
/**
Copy data from MMIO region to system memory by using 16-bit access.
Copy data from MMIO region specified by starting address StartAddress
to system memory specified by Buffer by using 16-bit access. The total
number of byte to be copied is specified by Length. Buffer is returned.
If StartAddress is not aligned on a 16-bit boundary, then ASSERT().
If Length is greater than (MAX_ADDRESS - StartAddress + 1), then ASSERT().
If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT().
If Length is not aligned on a 16-bit boundary, then ASSERT().
If Buffer is not aligned on a 16-bit boundary, then ASSERT().
@param StartAddress Starting address for the MMIO region to be copied from.
@param Length Size in bytes of the copy.
@param Buffer Pointer to a system memory buffer receiving the data read.
@return Buffer
**/
UINT16 *
EFIAPI
MmioReadBuffer16 (
IN UINTN StartAddress,
IN UINTN Length,
OUT UINT16 *Buffer
)
{
UINT16 *ReturnBuffer;
ASSERT ((StartAddress & (sizeof (UINT16) - 1)) == 0);
ASSERT ((Length - 1) <= (MAX_ADDRESS - StartAddress));
ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN) Buffer));
ASSERT ((Length & (sizeof (UINT16) - 1)) == 0);
ASSERT (((UINTN) Buffer & (sizeof (UINT16) - 1)) == 0);
ReturnBuffer = Buffer;
while (Length) {
*(Buffer++) = MmioRead16 (StartAddress);
StartAddress += sizeof (UINT16);
Length -= sizeof (UINT16);
}
return ReturnBuffer;
}
/**
Copy data from MMIO region to system memory by using 32-bit access.
Copy data from MMIO region specified by starting address StartAddress
to system memory specified by Buffer by using 32-bit access. The total
number of byte to be copied is specified by Length. Buffer is returned.
If StartAddress is not aligned on a 32-bit boundary, then ASSERT().
If Length is greater than (MAX_ADDRESS - StartAddress + 1), then ASSERT().
If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT().
If Length is not aligned on a 32-bit boundary, then ASSERT().
If Buffer is not aligned on a 32-bit boundary, then ASSERT().
@param StartAddress Starting address for the MMIO region to be copied from.
@param Length Size in bytes of the copy.
@param Buffer Pointer to a system memory buffer receiving the data read.
@return Buffer
**/
UINT32 *
EFIAPI
MmioReadBuffer32 (
IN UINTN StartAddress,
IN UINTN Length,
OUT UINT32 *Buffer
)
{
UINT32 *ReturnBuffer;
ASSERT ((StartAddress & (sizeof (UINT32) - 1)) == 0);
ASSERT ((Length - 1) <= (MAX_ADDRESS - StartAddress));
ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN) Buffer));
ASSERT ((Length & (sizeof (UINT32) - 1)) == 0);
ASSERT (((UINTN) Buffer & (sizeof (UINT32) - 1)) == 0);
ReturnBuffer = Buffer;
while (Length) {
*(Buffer++) = MmioRead32 (StartAddress);
StartAddress += sizeof (UINT32);
Length -= sizeof (UINT32);
}
return ReturnBuffer;
}
/**
Copy data from MMIO region to system memory by using 64-bit access.
Copy data from MMIO region specified by starting address StartAddress
to system memory specified by Buffer by using 64-bit access. The total
number of byte to be copied is specified by Length. Buffer is returned.
If StartAddress is not aligned on a 64-bit boundary, then ASSERT().
If Length is greater than (MAX_ADDRESS - StartAddress + 1), then ASSERT().
If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT().
If Length is not aligned on a 64-bit boundary, then ASSERT().
If Buffer is not aligned on a 64-bit boundary, then ASSERT().
@param StartAddress Starting address for the MMIO region to be copied from.
@param Length Size in bytes of the copy.
@param Buffer Pointer to a system memory buffer receiving the data read.
@return Buffer
**/
UINT64 *
EFIAPI
MmioReadBuffer64 (
IN UINTN StartAddress,
IN UINTN Length,
OUT UINT64 *Buffer
)
{
UINT64 *ReturnBuffer;
ASSERT ((StartAddress & (sizeof (UINT64) - 1)) == 0);
ASSERT ((Length - 1) <= (MAX_ADDRESS - StartAddress));
ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN) Buffer));
ASSERT ((Length & (sizeof (UINT64) - 1)) == 0);
ASSERT (((UINTN) Buffer & (sizeof (UINT64) - 1)) == 0);
ReturnBuffer = Buffer;
while (Length) {
*(Buffer++) = MmioRead64 (StartAddress);
StartAddress += sizeof (UINT64);
Length -= sizeof (UINT64);
}
return ReturnBuffer;
}
/**
Copy data from system memory to MMIO region by using 8-bit access.
Copy data from system memory specified by Buffer to MMIO region specified
by starting address StartAddress by using 8-bit access. The total number
of byte to be copied is specified by Length. Buffer is returned.
If Length is greater than (MAX_ADDRESS - StartAddress + 1), then ASSERT().
If Length is greater than (MAX_ADDRESS -Buffer + 1), then ASSERT().
@param StartAddress Starting address for the MMIO region to be copied to.
@param Length Size in bytes of the copy.
@param Buffer Pointer to a system memory buffer containing the data to write.
@return Size in bytes of the copy.
**/
UINT8 *
EFIAPI
MmioWriteBuffer8 (
IN UINTN StartAddress,
IN UINTN Length,
IN CONST UINT8 *Buffer
)
{
VOID* ReturnBuffer;
ASSERT ((Length - 1) <= (MAX_ADDRESS - StartAddress));
ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN) Buffer));
ReturnBuffer = (UINT8 *) Buffer;
while (Length--) {
MmioWrite8 (StartAddress++, *(Buffer++));
}
return ReturnBuffer;
}
/**
Copy data from system memory to MMIO region by using 16-bit access.
Copy data from system memory specified by Buffer to MMIO region specified
by starting address StartAddress by using 16-bit access. The total number
of byte to be copied is specified by Length. Length is returned.
If StartAddress is not aligned on a 16-bit boundary, then ASSERT().
If Length is greater than (MAX_ADDRESS - StartAddress + 1), then ASSERT().
If Length is greater than (MAX_ADDRESS -Buffer + 1), then ASSERT().
If Length is not aligned on a 16-bit boundary, then ASSERT().
If Buffer is not aligned on a 16-bit boundary, then ASSERT().
@param StartAddress Starting address for the MMIO region to be copied to.
@param Length Size in bytes of the copy.
@param Buffer Pointer to a system memory buffer containing the data to write.
@return Size in bytes of the copy.
**/
UINT16 *
EFIAPI
MmioWriteBuffer16 (
IN UINTN StartAddress,
IN UINTN Length,
IN CONST UINT16 *Buffer
)
{
UINT16 *ReturnBuffer;
ASSERT ((StartAddress & (sizeof (UINT16) - 1)) == 0);
ASSERT ((Length - 1) <= (MAX_ADDRESS - StartAddress));
ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN) Buffer));
ASSERT ((Length & (sizeof (UINT16) - 1)) == 0);
ASSERT (((UINTN) Buffer & (sizeof (UINT16) - 1)) == 0);
ReturnBuffer = (UINT16 *) Buffer;
while (Length) {
MmioWrite16 (StartAddress, *(Buffer++));
StartAddress += sizeof (UINT16);
Length -= sizeof (UINT16);
}
return ReturnBuffer;
}
/**
Copy data from system memory to MMIO region by using 32-bit access.
Copy data from system memory specified by Buffer to MMIO region specified
by starting address StartAddress by using 32-bit access. The total number
of byte to be copied is specified by Length. Length is returned.
If StartAddress is not aligned on a 32-bit boundary, then ASSERT().
If Length is greater than (MAX_ADDRESS - StartAddress + 1), then ASSERT().
If Length is greater than (MAX_ADDRESS -Buffer + 1), then ASSERT().
If Length is not aligned on a 32-bit boundary, then ASSERT().
If Buffer is not aligned on a 32-bit boundary, then ASSERT().
@param StartAddress Starting address for the MMIO region to be copied to.
@param Length Size in bytes of the copy.
@param Buffer Pointer to a system memory buffer containing the data to write.
@return Size in bytes of the copy.
**/
UINT32 *
EFIAPI
MmioWriteBuffer32 (
IN UINTN StartAddress,
IN UINTN Length,
IN CONST UINT32 *Buffer
)
{
UINT32 *ReturnBuffer;
ASSERT ((StartAddress & (sizeof (UINT32) - 1)) == 0);
ASSERT ((Length - 1) <= (MAX_ADDRESS - StartAddress));
ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN) Buffer));
ASSERT ((Length & (sizeof (UINT32) - 1)) == 0);
ASSERT (((UINTN) Buffer & (sizeof (UINT32) - 1)) == 0);
ReturnBuffer = (UINT32 *) Buffer;
while (Length) {
MmioWrite32 (StartAddress, *(Buffer++));
StartAddress += sizeof (UINT32);
Length -= sizeof (UINT32);
}
return ReturnBuffer;
}
/**
Copy data from system memory to MMIO region by using 64-bit access.
Copy data from system memory specified by Buffer to MMIO region specified
by starting address StartAddress by using 64-bit access. The total number
of byte to be copied is specified by Length. Length is returned.
If StartAddress is not aligned on a 64-bit boundary, then ASSERT().
If Length is greater than (MAX_ADDRESS - StartAddress + 1), then ASSERT().
If Length is greater than (MAX_ADDRESS -Buffer + 1), then ASSERT().
If Length is not aligned on a 64-bit boundary, then ASSERT().
If Buffer is not aligned on a 64-bit boundary, then ASSERT().
@param StartAddress Starting address for the MMIO region to be copied to.
@param Length Size in bytes of the copy.
@param Buffer Pointer to a system memory buffer containing the data to write.
@return Size in bytes of the copy.
**/
UINT64 *
EFIAPI
MmioWriteBuffer64 (
IN UINTN StartAddress,
IN UINTN Length,
IN CONST UINT64 *Buffer
)
{
UINT64 *ReturnBuffer;
ASSERT ((StartAddress & (sizeof (UINT64) - 1)) == 0);
ASSERT ((Length - 1) <= (MAX_ADDRESS - StartAddress));
ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN) Buffer));
ASSERT ((Length & (sizeof (UINT64) - 1)) == 0);
ASSERT (((UINTN) Buffer & (sizeof (UINT64) - 1)) == 0);
ReturnBuffer = (UINT64 *) Buffer;
while (Length) {
MmioWrite64 (StartAddress, *(Buffer++));
StartAddress += sizeof (UINT64);
Length -= sizeof (UINT64);
}
return ReturnBuffer;
}

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MdePkg/Library/BaseIoLibIntrinsic/IoLibMsc.c Normal file
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/** @file
I/O Library. This file has compiler specifics for Microsft C as there is no
ANSI C standard for doing IO.
MSC - uses intrinsic functions and the optimize will remove the function call
overhead.
We don't advocate putting compiler specifics in libraries or drivers but there
is no other way to make this work.
Copyright (c) 2006 - 2007, Intel Corporation<BR>
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
Module Name: IoLibMsc.c
**/
//
// Include common header file for this module.
//
#include "CommonHeader.h"
//
// Microsoft Visual Studio 7.1 Function Prototypes for I/O Intrinsics
//
int _inp (unsigned short port);
unsigned short _inpw (unsigned short port);
unsigned long _inpd (unsigned short port);
int _outp (unsigned short port, int databyte );
unsigned short _outpw (unsigned short port, unsigned short dataword );
unsigned long _outpd (unsigned short port, unsigned long dataword );
void _ReadWriteBarrier (void);
#pragma intrinsic(_inp)
#pragma intrinsic(_inpw)
#pragma intrinsic(_inpd)
#pragma intrinsic(_outp)
#pragma intrinsic(_outpw)
#pragma intrinsic(_outpd)
#pragma intrinsic(_ReadWriteBarrier)
//
// _ReadWriteBarrier() forces memory reads and writes to complete at the point
// in the call. This is only a hint to the compiler and does emit code.
// In past versions of the compiler, _ReadWriteBarrier was enforced only
// locally and did not affect functions up the call tree. In Visual C++
// 2005, _ReadWriteBarrier is enforced all the way up the call tree.
//
/**
Reads an 8-bit I/O port.
Reads the 8-bit I/O port specified by Port. The 8-bit read value is returned.
This function must guarantee that all I/O read and write operations are
serialized.
If 8-bit I/O port operations are not supported, then ASSERT().
@param Port The I/O port to read.
@return The value read.
**/
UINT8
EFIAPI
IoRead8 (
IN UINTN Port
)
{
UINT8 Value;
_ReadWriteBarrier ();
Value = (UINT8)_inp ((UINT16)Port);
_ReadWriteBarrier ();
return Value;
}
/**
Writes an 8-bit I/O port.
Writes the 8-bit I/O port specified by Port with the value specified by Value
and returns Value. This function must guarantee that all I/O read and write
operations are serialized.
If 8-bit I/O port operations are not supported, then ASSERT().
@param Port The I/O port to write.
@param Value The value to write to the I/O port.
@return The value written the I/O port.
**/
UINT8
EFIAPI
IoWrite8 (
IN UINTN Port,
IN UINT8 Value
)
{
_ReadWriteBarrier ();
(UINT8)_outp ((UINT16)Port, Value);
_ReadWriteBarrier ();
return Value;
}
/**
Reads a 16-bit I/O port.
Reads the 16-bit I/O port specified by Port. The 16-bit read value is returned.
This function must guarantee that all I/O read and write operations are
serialized.
If 16-bit I/O port operations are not supported, then ASSERT().
@param Port The I/O port to read.
@return The value read.
**/
UINT16
EFIAPI
IoRead16 (
IN UINTN Port
)
{
UINT16 Value;
ASSERT ((Port & 1) == 0);
_ReadWriteBarrier ();
Value = _inpw ((UINT16)Port);
_ReadWriteBarrier ();
return Value;
}
/**
Writes a 16-bit I/O port.
Writes the 16-bit I/O port specified by Port with the value specified by Value
and returns Value. This function must guarantee that all I/O read and write
operations are serialized.
If 16-bit I/O port operations are not supported, then ASSERT().
@param Port The I/O port to write.
@param Value The value to write to the I/O port.
@return The value written the I/O port.
**/
UINT16
EFIAPI
IoWrite16 (
IN UINTN Port,
IN UINT16 Value
)
{
ASSERT ((Port & 1) == 0);
_ReadWriteBarrier ();
_outpw ((UINT16)Port, Value);
_ReadWriteBarrier ();
return Value;
}
/**
Reads a 32-bit I/O port.
Reads the 32-bit I/O port specified by Port. The 32-bit read value is returned.
This function must guarantee that all I/O read and write operations are
serialized.
If 32-bit I/O port operations are not supported, then ASSERT().
@param Port The I/O port to read.
@return The value read.
**/
UINT32
EFIAPI
IoRead32 (
IN UINTN Port
)
{
UINT32 Value;
ASSERT ((Port & 3) == 0);
_ReadWriteBarrier ();
Value = _inpd ((UINT16)Port);
_ReadWriteBarrier ();
return Value;
}
/**
Writes a 32-bit I/O port.
Writes the 32-bit I/O port specified by Port with the value specified by Value
and returns Value. This function must guarantee that all I/O read and write
operations are serialized.
If 32-bit I/O port operations are not supported, then ASSERT().
@param Port The I/O port to write.
@param Value The value to write to the I/O port.
@return The value written the I/O port.
**/
UINT32
EFIAPI
IoWrite32 (
IN UINTN Port,
IN UINT32 Value
)
{
ASSERT ((Port & 3) == 0);
_ReadWriteBarrier ();
_outpd ((UINT16)Port, Value);
_ReadWriteBarrier ();
return Value;
}
/**
Reads an 8-bit MMIO register.
Reads the 8-bit MMIO register specified by Address. The 8-bit read value is
returned. This function must guarantee that all MMIO read and write
operations are serialized.
If 8-bit MMIO register operations are not supported, then ASSERT().
@param Address The MMIO register to read.
@return The value read.
**/
UINT8
EFIAPI
MmioRead8 (
IN UINTN Address
)
{
UINT8 Value;
Value = *(volatile UINT8*)Address;
return Value;
}
/**
Writes an 8-bit MMIO register.
Writes the 8-bit MMIO register specified by Address with the value specified
by Value and returns Value. This function must guarantee that all MMIO read
and write operations are serialized.
If 8-bit MMIO register operations are not supported, then ASSERT().
@param Address The MMIO register to write.
@param Value The value to write to the MMIO register.
**/
UINT8
EFIAPI
MmioWrite8 (
IN UINTN Address,
IN UINT8 Value
)
{
return *(volatile UINT8*)Address = Value;
}
/**
Reads a 16-bit MMIO register.
Reads the 16-bit MMIO register specified by Address. The 16-bit read value is
returned. This function must guarantee that all MMIO read and write
operations are serialized.
If 16-bit MMIO register operations are not supported, then ASSERT().
@param Address The MMIO register to read.
@return The value read.
**/
UINT16
EFIAPI
MmioRead16 (
IN UINTN Address
)
{
UINT16 Value;
ASSERT ((Address & 1) == 0);
Value = *(volatile UINT16*)Address;
return Value;
}
/**
Writes a 16-bit MMIO register.
Writes the 16-bit MMIO register specified by Address with the value specified
by Value and returns Value. This function must guarantee that all MMIO read
and write operations are serialized.
If 16-bit MMIO register operations are not supported, then ASSERT().
@param Address The MMIO register to write.
@param Value The value to write to the MMIO register.
**/
UINT16
EFIAPI
MmioWrite16 (
IN UINTN Address,
IN UINT16 Value
)
{
ASSERT ((Address & 1) == 0);
return *(volatile UINT16*)Address = Value;
}
/**
Reads a 32-bit MMIO register.
Reads the 32-bit MMIO register specified by Address. The 32-bit read value is
returned. This function must guarantee that all MMIO read and write
operations are serialized.
If 32-bit MMIO register operations are not supported, then ASSERT().
@param Address The MMIO register to read.
@return The value read.
**/
UINT32
EFIAPI
MmioRead32 (
IN UINTN Address
)
{
UINT32 Value;
ASSERT ((Address & 3) == 0);
Value = *(volatile UINT32*)Address;
return Value;
}
/**
Writes a 32-bit MMIO register.
Writes the 32-bit MMIO register specified by Address with the value specified
by Value and returns Value. This function must guarantee that all MMIO read
and write operations are serialized.
If 32-bit MMIO register operations are not supported, then ASSERT().
@param Address The MMIO register to write.
@param Value The value to write to the MMIO register.
**/
UINT32
EFIAPI
MmioWrite32 (
IN UINTN Address,
IN UINT32 Value
)
{
ASSERT ((Address & 3) == 0);
return *(volatile UINT32*)Address = Value;
}
/**
Reads a 64-bit MMIO register.
Reads the 64-bit MMIO register specified by Address. The 64-bit read value is
returned. This function must guarantee that all MMIO read and write
operations are serialized.
If 64-bit MMIO register operations are not supported, then ASSERT().
@param Address The MMIO register to read.
@return The value read.
**/
UINT64
EFIAPI
MmioRead64 (
IN UINTN Address
)
{
UINT64 Value;
ASSERT ((Address & 7) == 0);
Value = *(volatile UINT64*)Address;
return Value;
}
/**
Writes a 64-bit MMIO register.
Writes the 64-bit MMIO register specified by Address with the value specified
by Value and returns Value. This function must guarantee that all MMIO read
and write operations are serialized.
If 64-bit MMIO register operations are not supported, then ASSERT().
@param Address The MMIO register to write.
@param Value The value to write to the MMIO register.
**/
UINT64
EFIAPI
MmioWrite64 (
IN UINTN Address,
IN UINT64 Value
)
{
ASSERT ((Address & 7) == 0);
return *(volatile UINT64*)Address = Value;
}

46
MdePkg/Library/BaseLib/ARShiftU64.c Normal file
View File

@ -0,0 +1,46 @@
/** @file
Math worker functions.
Copyright (c) 2006, Intel Corporation<BR>
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
//
// Include common header file for this module.
//
#include "CommonHeader.h"
#include "BaseLibInternals.h"
/**
Shifts a 64-bit integer right between 0 and 63 bits. The high bits are filled
with original integer's bit 63. The shifted value is returned.
This function shifts the 64-bit value Operand to the right by Count bits. The
high Count bits are set to bit 63 of Operand. The shifted value is returned.
If Count is greater than 63, then ASSERT().
@param Operand The 64-bit operand to shift right.
@param Count The number of bits to shift right.
@return Operand arithmetically shifted right by Count
**/
UINT64
EFIAPI
ARShiftU64 (
IN UINT64 Operand,
IN UINTN Count
)
{
ASSERT (Count < sizeof (Operand) * 8);
return InternalMathARShiftU64 (Operand, Count);
}

575
MdePkg/Library/BaseLib/BaseLib.inf Normal file
View File

@ -0,0 +1,575 @@
#/** @file
# Component description file for Base Library
#
# Base Library implementation.
# Copyright (c) 2007 - 2007, Intel Corporation.
#
# All rights reserved. This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#
#**/
################################################################################
#
# Defines Section - statements that will be processed to create a Makefile.
#
################################################################################
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = BaseLib
FILE_GUID = 27d67720-ea68-48ae-93da-a3a074c90e30
MODULE_TYPE = BASE
VERSION_STRING = 1.0
LIBRARY_CLASS = BaseLib
EDK_RELEASE_VERSION = 0x00020000
EFI_SPECIFICATION_VERSION = 0x00020000
#
# The following information is for reference only and not required by the build tools.
#
# VALID_ARCHITECTURES = IA32 X64 IPF EBC
#
################################################################################
#
# Sources Section - list of files that are required for the build to succeed.
#
################################################################################
[Sources.common]
CheckSum.c
SwitchStack.c
SwapBytes64.c
SwapBytes32.c
SwapBytes16.c
LongJump.c
SetJump.c
RShiftU64.c
RRotU64.c
RRotU32.c
MultU64x64.c
MultU64x32.c
MultS64x64.c
ModU64x32.c
LShiftU64.c
LRotU64.c
LRotU32.c
LowBitSet64.c
LowBitSet32.c
HighBitSet64.c
HighBitSet32.c
GetPowerOfTwo64.c
GetPowerOfTwo32.c
DivU64x64Remainder.c
DivU64x32Remainder.c
DivU64x32.c
DivS64x64Remainder.c
ARShiftU64.c
BitField.c
CpuDeadLoop.c
Cpu.c
LinkedList.c
String.c
BaseLibInternals.h
CommonHeader.h
[Sources.Ia32]
Ia32/Wbinvd.c
Ia32/WriteMm7.c
Ia32/WriteMm6.c
Ia32/WriteMm5.c
Ia32/WriteMm4.c
Ia32/WriteMm3.c
Ia32/WriteMm2.c
Ia32/WriteMm1.c
Ia32/WriteMm0.c
Ia32/WriteLdtr.c
Ia32/WriteIdtr.c
Ia32/WriteGdtr.c
Ia32/WriteDr7.c
Ia32/WriteDr6.c
Ia32/WriteDr5.c
Ia32/WriteDr4.c
Ia32/WriteDr3.c
Ia32/WriteDr2.c
Ia32/WriteDr1.c
Ia32/WriteDr0.c
Ia32/WriteCr4.c
Ia32/WriteCr3.c
Ia32/WriteCr2.c
Ia32/WriteCr0.c
Ia32/WriteMsr64.c
Ia32/Thunk16.asm
Ia32/SwapBytes64.c
Ia32/SetJump.c
Ia32/RRotU64.c
Ia32/RShiftU64.c
Ia32/ReadPmc.c
Ia32/ReadTsc.c
Ia32/ReadLdtr.c
Ia32/ReadIdtr.c
Ia32/ReadGdtr.c
Ia32/ReadTr.c
Ia32/ReadSs.c
Ia32/ReadGs.c
Ia32/ReadFs.c
Ia32/ReadEs.c
Ia32/ReadDs.c
Ia32/ReadCs.c
Ia32/ReadMsr64.c
Ia32/ReadMm7.c
Ia32/ReadMm6.c
Ia32/ReadMm5.c
Ia32/ReadMm4.c
Ia32/ReadMm3.c
Ia32/ReadMm2.c
Ia32/ReadMm1.c
Ia32/ReadMm0.c
Ia32/ReadEflags.c
Ia32/ReadDr7.c
Ia32/ReadDr6.c
Ia32/ReadDr5.c
Ia32/ReadDr4.c
Ia32/ReadDr3.c
Ia32/ReadDr2.c
Ia32/ReadDr1.c
Ia32/ReadDr0.c
Ia32/ReadCr4.c
Ia32/ReadCr3.c
Ia32/ReadCr2.c
Ia32/ReadCr0.c
Ia32/Mwait.c
Ia32/Monitor.c
Ia32/ModU64x32.c
Ia32/MultU64x64.c
Ia32/MultU64x32.c
Ia32/LShiftU64.c
Ia32/LRotU64.c
Ia32/LongJump.c
Ia32/Invd.c
Ia32/InterlockedCompareExchange64.c
Ia32/InterlockedCompareExchange32.c
Ia32/InterlockedDecrement.c
Ia32/InterlockedIncrement.c
Ia32/FxRestore.c
Ia32/FxSave.c
Ia32/FlushCacheLine.c
Ia32/EnablePaging64.asm
Ia32/EnablePaging32.c
Ia32/EnableInterrupts.c
Ia32/EnableDisableInterrupts.c
Ia32/DivU64x64Remainder.c
Ia32/DivU64x32Remainder.c
Ia32/DivU64x32.c
Ia32/DisablePaging32.c
Ia32/DisableInterrupts.c
Ia32/CpuPause.c
Ia32/CpuIdEx.c
Ia32/CpuId.c
Ia32/CpuSleep.c
Ia32/CpuFlushTlb.c
Ia32/CpuBreakpoint.c
Ia32/ARShiftU64.c
Ia32/Thunk16.S
Ia32/CpuFlushTlb.S
Ia32/CpuBreakpoint.S
Ia32/CpuPause.S
Ia32/CpuSleep.S
Ia32/EnableDisableInterrupts.S
Ia32/DisableInterrupts.S
Ia32/EnableInterrupts.S
Ia32/InterlockedCompareExchange64.S
Ia32/InterlockedCompareExchange32.S
Ia32/InterlockedDecrement.S
Ia32/InterlockedIncrement.S
Ia32/FlushCacheLine.S
Ia32/Invd.S
Ia32/Wbinvd.S
Ia32/EnablePaging64.S
Ia32/DisablePaging32.S
Ia32/EnablePaging32.S
Ia32/Mwait.S
Ia32/Monitor.S
Ia32/ReadPmc.S
Ia32/ReadTsc.S
Ia32/WriteMm7.S
Ia32/WriteMm6.S
Ia32/WriteMm5.S
Ia32/WriteMm4.S
Ia32/WriteMm3.S
Ia32/WriteMm2.S
Ia32/WriteMm1.S
Ia32/WriteMm0.S
Ia32/ReadMm7.S
Ia32/ReadMm6.S
Ia32/ReadMm5.S
Ia32/ReadMm4.S
Ia32/ReadMm3.S
Ia32/ReadMm2.S
Ia32/ReadMm1.S
Ia32/ReadMm0.S
Ia32/FxRestore.S
Ia32/FxSave.S
Ia32/WriteLdtr.S
Ia32/ReadLdtr.S
Ia32/WriteIdtr.S
Ia32/ReadIdtr.S
Ia32/WriteGdtr.S
Ia32/ReadGdtr.S
Ia32/ReadTr.S
Ia32/ReadSs.S
Ia32/ReadGs.S
Ia32/ReadFs.S
Ia32/ReadEs.S
Ia32/ReadDs.S
Ia32/ReadCs.S
Ia32/WriteDr7.S
Ia32/WriteDr6.S
Ia32/WriteDr5.S
Ia32/WriteDr4.S
Ia32/WriteDr3.S
Ia32/WriteDr2.S
Ia32/WriteDr1.S
Ia32/WriteDr0.S
Ia32/ReadDr7.S
Ia32/ReadDr6.S
Ia32/ReadDr5.S
Ia32/ReadDr4.S
Ia32/ReadDr3.S
Ia32/ReadDr2.S
Ia32/ReadDr1.S
Ia32/ReadDr0.S
Ia32/WriteCr4.S
Ia32/WriteCr3.S
Ia32/WriteCr2.S
Ia32/WriteCr0.S
Ia32/ReadCr4.S
Ia32/ReadCr3.S
Ia32/ReadCr2.S
Ia32/ReadCr0.S
Ia32/WriteMsr64.S
Ia32/ReadMsr64.S
Ia32/ReadEflags.S
Ia32/CpuIdEx.S
Ia32/CpuId.S
Ia32/LongJump.S
Ia32/SetJump.S
Ia32/SwapBytes64.S
Ia32/DivU64x64Remainder.S
Ia32/DivU64x32Remainder.S
Ia32/ModU64x32.S
Ia32/DivU64x32.S
Ia32/MultU64x64.S
Ia32/MultU64x32.S
Ia32/RRotU64.S
Ia32/LRotU64.S
Ia32/ARShiftU64.S
Ia32/RShiftU64.S
Ia32/LShiftU64.S
Ia32/DivS64x64Remainder.c
Ia32/InternalSwitchStack.c
Ia32/Non-existing.c
Unaligned.c
x86WriteIdtr.c
x86WriteGdtr.c
x86Thunk.c
x86ReadIdtr.c
x86ReadGdtr.c
x86Msr.c
x86MemoryFence.c
x86GetInterruptState.c
x86FxSave.c
x86FxRestore.c
x86EnablePaging64.c
x86EnablePaging32.c
x86DisablePaging64.c
x86DisablePaging32.c
Synchronization.c
SynchronizationMsc.c
SynchronizationGcc.c
[Sources.X64]
X64/Thunk16.asm
X64/CpuFlushTlb.asm
X64/CpuBreakpoint.c
X64/CpuPause.asm
X64/CpuSleep.asm
X64/EnableDisableInterrupts.asm
X64/DisableInterrupts.asm
X64/EnableInterrupts.asm
X64/InterlockedCompareExchange64.asm
X64/InterlockedCompareExchange32.asm
X64/InterlockedDecrement.c
X64/InterlockedIncrement.c
X64/FlushCacheLine.asm
X64/Invd.asm
X64/Wbinvd.asm
X64/DisablePaging64.asm
X64/EnablePaging64.asm
X64/Mwait.asm
X64/Monitor.asm
X64/ReadPmc.asm
X64/ReadTsc.asm
X64/WriteMm7.asm
X64/WriteMm6.asm
X64/WriteMm5.asm
X64/WriteMm4.asm
X64/WriteMm3.asm
X64/WriteMm2.asm
X64/WriteMm1.asm
X64/WriteMm0.asm
X64/ReadMm7.asm
X64/ReadMm6.asm
X64/ReadMm5.asm
X64/ReadMm4.asm
X64/ReadMm3.asm
X64/ReadMm2.asm
X64/ReadMm1.asm
X64/ReadMm0.asm
X64/FxRestore.asm
X64/FxSave.asm
X64/WriteLdtr.asm
X64/ReadLdtr.asm
X64/WriteIdtr.asm
X64/ReadIdtr.asm
X64/WriteGdtr.asm
X64/ReadGdtr.asm
X64/ReadTr.asm
X64/ReadSs.asm
X64/ReadGs.asm
X64/ReadFs.asm
X64/ReadEs.asm
X64/ReadDs.asm
X64/ReadCs.asm
X64/WriteDr7.asm
X64/WriteDr6.asm
X64/WriteDr5.asm
X64/WriteDr4.asm
X64/WriteDr3.asm
X64/WriteDr2.asm
X64/WriteDr1.asm
X64/WriteDr0.asm
X64/ReadDr7.asm
X64/ReadDr6.asm
X64/ReadDr5.asm
X64/ReadDr4.asm
X64/ReadDr3.asm
X64/ReadDr2.asm
X64/ReadDr1.asm
X64/ReadDr0.asm
X64/WriteCr4.asm
X64/WriteCr3.asm
X64/WriteCr2.asm
X64/WriteCr0.asm
X64/ReadCr4.asm
X64/ReadCr3.asm
X64/ReadCr2.asm
X64/ReadCr0.asm
X64/WriteMsr64.c
X64/ReadMsr64.c
X64/ReadEflags.asm
X64/CpuIdEx.asm
X64/CpuId.asm
X64/LongJump.asm
X64/SetJump.asm
X64/SwitchStack.asm
X64/Non-existing.c
Math64.c
Unaligned.c
x86WriteIdtr.c
x86WriteGdtr.c
x86Thunk.c
x86ReadIdtr.c
x86ReadGdtr.c
x86Msr.c
x86MemoryFence.c
x86GetInterruptState.c
x86FxSave.c
x86FxRestore.c
x86EnablePaging64.c
x86EnablePaging32.c
x86DisablePaging64.c
x86DisablePaging32.c
X64/WriteMsr64.S
X64/WriteMm7.S
X64/WriteMm6.S
X64/WriteMm5.S
X64/WriteMm4.S
X64/WriteMm3.S
X64/WriteMm2.S
X64/WriteMm1.S
X64/WriteMm0.S
X64/WriteLdtr.S
X64/WriteIdtr.S
X64/WriteGdtr.S
X64/WriteDr7.S
X64/WriteDr6.S
X64/WriteDr5.S
X64/WriteDr4.S
X64/WriteDr3.S
X64/WriteDr2.S
X64/WriteDr1.S
X64/WriteDr0.S
X64/WriteCr4.S
X64/WriteCr3.S
X64/WriteCr2.S
X64/WriteCr0.S
X64/Wbinvd.S
X64/Thunk16.S
X64/SwitchStack.S
X64/SetJump.S
X64/ReadTsc.S
X64/ReadTr.S
X64/ReadSs.S
X64/ReadPmc.S
X64/ReadMsr64.S
X64/ReadMm7.S
X64/ReadMm6.S
X64/ReadMm5.S
X64/ReadMm4.S
X64/ReadMm3.S
X64/ReadMm2.S
X64/ReadMm1.S
X64/ReadMm0.S
X64/ReadLdtr.S
X64/ReadIdtr.S
X64/ReadGs.S
X64/ReadGdtr.S
X64/ReadFs.S
X64/ReadEs.S
X64/ReadEflags.S
X64/ReadDs.S
X64/ReadDr7.S
X64/ReadDr6.S
X64/ReadDr5.S
X64/ReadDr4.S
X64/ReadDr3.S
X64/ReadDr2.S
X64/ReadDr1.S
X64/ReadDr0.S
X64/ReadCs.S
X64/ReadCr4.S
X64/ReadCr3.S
X64/ReadCr2.S
X64/ReadCr0.S
X64/Mwait.S
X64/Monitor.S
X64/LongJump.S
X64/Invd.S
X64/InterlockedIncrement.S
X64/InterlockedDecrement.S
X64/InterlockedCompareExchange64.S
X64/InterlockedCompareExchange32.S
X64/FxSave.S
X64/FxRestore.S
X64/FlushCacheLine.S
X64/EnablePaging64.S
X64/EnableInterrupts.S
X64/EnableDisableInterrupts.S
X64/DisablePaging64.S
X64/DisableInterrupts.S
X64/CpuSleep.S
X64/CpuPause.S
X64/CpuId.S
X64/CpuIdEx.S
X64/CpuFlushTlb.S
X64/CpuBreakpoint.S
Synchronization.c
SynchronizationMsc.c
SynchronizationGcc.c
[Sources.IPF]
Ipf/AccessGp.s
Ipf/ReadCpuid.s
Ipf/ExecFc.s
Ipf/AsmPalCall.s
Ipf/AccessPsr.s
Ipf/AccessPmr.s
Ipf/AccessKr.s
Ipf/AccessGcr.s
Ipf/AccessEicr.s
Ipf/AccessDbr.s
Ipf/FlushCacheRange.s
Ipf/InternalSwitchStack.c
Ipf/GetInterruptState.s
Ipf/CpuFlushTlb.s
Ipf/CpuPause.s
Ipf/Synchronization.c
Ipf/InterlockedCompareExchange64.s
Ipf/InterlockedCompareExchange32.s
Ipf/CpuBreakpoint.c
Ipf/Unaligned.c
Ipf/SwitchStack.s
Ipf/longjmp.s
Ipf/setjmp.s
Ipf/PalCallStatic.s
Ipf/ia_64gen.h
Ipf/asm.h
Math64.c
Synchronization.c
SynchronizationMsc.c
SynchronizationGcc.c
[Sources.EBC]
Synchronization.c
Ebc/Synchronization.c
Ebc/CpuBreakpoint.c
Ebc/SetJumpLongJump.c
Ebc/SwitchStack.c
Unaligned.c
Math64.c
################################################################################
#
# Includes Section - list of Include locations that are required for
# this module.
#
################################################################################
[Includes]
$(WORKSPACE)/MdePkg\Include/Library
################################################################################
#
# Package Dependency Section - list of Package files that are required for
# this module.
#
################################################################################
[Packages]
MdePkg/MdePkg.dec
################################################################################
#
# Library Class Section - list of Library Classes that are required for
# this module.
#
################################################################################
[LibraryClasses]
PcdLib
TimerLib
DebugLib
BaseMemoryLib
################################################################################
#
# Pcd FIXED_AT_BUILD - list of PCDs that this module is coded for.
#
################################################################################
[PcdsFixedAtBuild.common]
PcdSpinLockTimeout|gEfiMdePkgTokenSpaceGuid
PcdMaximumLinkedListLength|gEfiMdePkgTokenSpaceGuid
PcdMaximumAsciiStringLength|gEfiMdePkgTokenSpaceGuid
PcdMaximumUnicodeStringLength|gEfiMdePkgTokenSpaceGuid

660
MdePkg/Library/BaseLib/BaseLib.msa Normal file
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@ -0,0 +1,660 @@
<?xml version="1.0" encoding="UTF-8"?>
<ModuleSurfaceArea xmlns="http://www.TianoCore.org/2006/Edk2.0">
<MsaHeader>
<ModuleName>BaseLib</ModuleName>
<ModuleType>BASE</ModuleType>
<GuidValue>27d67720-ea68-48ae-93da-a3a074c90e30</GuidValue>
<Version>1.0</Version>
<Abstract>Component description file for Base Library</Abstract>
<Description>Base Library implementation.</Description>
<Copyright>Copyright (c) 2006 - 2007, Intel Corporation.</Copyright>
<License>All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.</License>
<Specification>FRAMEWORK_BUILD_PACKAGING_SPECIFICATION 0x00000052</Specification>
</MsaHeader>
<ModuleDefinitions>
<SupportedArchitectures>IA32 X64 IPF EBC</SupportedArchitectures>
<BinaryModule>false</BinaryModule>
<OutputFileBasename>BaseLib</OutputFileBasename>
</ModuleDefinitions>
<LibraryClassDefinitions>
<LibraryClass Usage="ALWAYS_PRODUCED">
<Keyword>BaseLib</Keyword>
</LibraryClass>
<LibraryClass Usage="ALWAYS_CONSUMED">
<Keyword>BaseMemoryLib</Keyword>
</LibraryClass>
<LibraryClass Usage="ALWAYS_CONSUMED">
<Keyword>DebugLib</Keyword>
</LibraryClass>
<LibraryClass Usage="ALWAYS_CONSUMED">
<Keyword>TimerLib</Keyword>
</LibraryClass>
<LibraryClass Usage="ALWAYS_CONSUMED">
<Keyword>PcdLib</Keyword>
</LibraryClass>
</LibraryClassDefinitions>
<SourceFiles>
<Filename>BaseLibInternals.h</Filename>
<Filename>String.c</Filename>
<Filename>LinkedList.c</Filename>
<Filename>Cpu.c</Filename>
<Filename>CpuDeadLoop.c</Filename>
<Filename>BitField.c</Filename>
<Filename>ARShiftU64.c</Filename>
<Filename>DivS64x64Remainder.c</Filename>
<Filename>DivU64x32.c</Filename>
<Filename>DivU64x32Remainder.c</Filename>
<Filename>DivU64x64Remainder.c</Filename>
<Filename>GetPowerOfTwo32.c</Filename>
<Filename>GetPowerOfTwo64.c</Filename>
<Filename>HighBitSet32.c</Filename>
<Filename>HighBitSet64.c</Filename>
<Filename>LowBitSet32.c</Filename>
<Filename>LowBitSet64.c</Filename>
<Filename>LRotU32.c</Filename>
<Filename>LRotU64.c</Filename>
<Filename>LShiftU64.c</Filename>
<Filename>ModU64x32.c</Filename>
<Filename>MultS64x64.c</Filename>
<Filename>MultU64x32.c</Filename>
<Filename>MultU64x64.c</Filename>
<Filename>RRotU32.c</Filename>
<Filename>RRotU64.c</Filename>
<Filename>RShiftU64.c</Filename>
<Filename>SetJump.c</Filename>
<Filename>LongJump.c</Filename>
<Filename>SwapBytes16.c</Filename>
<Filename>SwapBytes32.c</Filename>
<Filename>SwapBytes64.c</Filename>
<Filename>SwitchStack.c</Filename>
<Filename>CheckSum.c</Filename>
<Filename SupArchList="IA32 X64 IPF" ToolChainFamily="GCC">SynchronizationGcc.c</Filename>
<Filename SupArchList="IA32 X64 IPF" ToolChainFamily="MSFT">SynchronizationMsc.c</Filename>
<Filename SupArchList="IA32 X64 IPF" ToolChainFamily="INTEL">Synchronization.c</Filename>
<Filename SupArchList="IA32">x86DisablePaging32.c</Filename>
<Filename SupArchList="IA32">x86DisablePaging64.c</Filename>
<Filename SupArchList="IA32">x86EnablePaging32.c</Filename>
<Filename SupArchList="IA32">x86EnablePaging64.c</Filename>
<Filename SupArchList="IA32">x86FxRestore.c</Filename>
<Filename SupArchList="IA32">x86FxSave.c</Filename>
<Filename SupArchList="IA32">x86GetInterruptState.c</Filename>
<Filename SupArchList="IA32">x86MemoryFence.c</Filename>
<Filename SupArchList="IA32">x86Msr.c</Filename>
<Filename SupArchList="IA32">x86ReadGdtr.c</Filename>
<Filename SupArchList="IA32">x86ReadIdtr.c</Filename>
<Filename SupArchList="IA32">x86Thunk.c</Filename>
<Filename SupArchList="IA32">x86WriteGdtr.c</Filename>
<Filename SupArchList="IA32">x86WriteIdtr.c</Filename>
<Filename SupArchList="IA32">Unaligned.c</Filename>
<Filename SupArchList="IA32">Ia32/Non-existing.c</Filename>
<Filename SupArchList="IA32">Ia32/InternalSwitchStack.c</Filename>
<Filename SupArchList="IA32">Ia32/DivS64x64Remainder.c</Filename>
<!-- GCC assembly code is with .S extension -->
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<Filename SupArchList="IA32" ToolChainFamily="GCC">Ia32/DivU64x64Remainder.S</Filename>
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<Filename SupArchList="IA32" ToolChainFamily="MSFT">Ia32/ReadDr1.c</Filename>
<Filename SupArchList="IA32" ToolChainFamily="MSFT">Ia32/ReadDr2.c</Filename>
<Filename SupArchList="IA32" ToolChainFamily="MSFT">Ia32/ReadDr3.c</Filename>
<Filename SupArchList="IA32" ToolChainFamily="MSFT">Ia32/ReadDr4.c</Filename>
<Filename SupArchList="IA32" ToolChainFamily="MSFT">Ia32/ReadDr5.c</Filename>
<Filename SupArchList="IA32" ToolChainFamily="MSFT">Ia32/ReadDr6.c</Filename>
<Filename SupArchList="IA32" ToolChainFamily="MSFT">Ia32/ReadDr7.c</Filename>
<Filename SupArchList="IA32" ToolChainFamily="MSFT">Ia32/ReadEflags.c</Filename>
<Filename SupArchList="IA32" ToolChainFamily="MSFT">Ia32/ReadMm0.c</Filename>
<Filename SupArchList="IA32" ToolChainFamily="MSFT">Ia32/ReadMm1.c</Filename>
<Filename SupArchList="IA32" ToolChainFamily="MSFT">Ia32/ReadMm2.c</Filename>
<Filename SupArchList="IA32" ToolChainFamily="MSFT">Ia32/ReadMm3.c</Filename>
<Filename SupArchList="IA32" ToolChainFamily="MSFT">Ia32/ReadMm4.c</Filename>
<Filename SupArchList="IA32" ToolChainFamily="MSFT">Ia32/ReadMm5.c</Filename>
<Filename SupArchList="IA32" ToolChainFamily="MSFT">Ia32/ReadMm6.c</Filename>
<Filename SupArchList="IA32" ToolChainFamily="MSFT">Ia32/ReadMm7.c</Filename>
<Filename SupArchList="IA32" ToolChainFamily="MSFT">Ia32/ReadMsr64.c</Filename>
<Filename SupArchList="IA32" ToolChainFamily="MSFT">Ia32/ReadCs.c</Filename>
<Filename SupArchList="IA32" ToolChainFamily="MSFT">Ia32/ReadDs.c</Filename>
<Filename SupArchList="IA32" ToolChainFamily="MSFT">Ia32/ReadEs.c</Filename>
<Filename SupArchList="IA32" ToolChainFamily="MSFT">Ia32/ReadFs.c</Filename>
<Filename SupArchList="IA32" ToolChainFamily="MSFT">Ia32/ReadGs.c</Filename>
<Filename SupArchList="IA32" ToolChainFamily="MSFT">Ia32/ReadSs.c</Filename>
<Filename SupArchList="IA32" ToolChainFamily="MSFT">Ia32/ReadTr.c</Filename>
<Filename SupArchList="IA32" ToolChainFamily="MSFT">Ia32/ReadGdtr.c</Filename>
<Filename SupArchList="IA32" ToolChainFamily="MSFT">Ia32/ReadIdtr.c</Filename>
<Filename SupArchList="IA32" ToolChainFamily="MSFT">Ia32/ReadLdtr.c</Filename>
<Filename SupArchList="IA32" ToolChainFamily="MSFT">Ia32/ReadTsc.c</Filename>
<Filename SupArchList="IA32" ToolChainFamily="MSFT">Ia32/ReadPmc.c</Filename>
<Filename SupArchList="IA32" ToolChainFamily="MSFT">Ia32/RShiftU64.c</Filename>
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<Filename SupArchList="IA32" ToolChainFamily="MSFT">Ia32/WriteCr0.c</Filename>
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<Filename SupArchList="IA32" ToolChainFamily="MSFT">Ia32/WriteDr4.c</Filename>
<Filename SupArchList="IA32" ToolChainFamily="MSFT">Ia32/WriteDr5.c</Filename>
<Filename SupArchList="IA32" ToolChainFamily="MSFT">Ia32/WriteDr6.c</Filename>
<Filename SupArchList="IA32" ToolChainFamily="MSFT">Ia32/WriteDr7.c</Filename>
<Filename SupArchList="IA32" ToolChainFamily="MSFT">Ia32/WriteGdtr.c</Filename>
<Filename SupArchList="IA32" ToolChainFamily="MSFT">Ia32/WriteIdtr.c</Filename>
<Filename SupArchList="IA32" ToolChainFamily="MSFT">Ia32/WriteLdtr.c</Filename>
<Filename SupArchList="IA32" ToolChainFamily="MSFT">Ia32/WriteMm0.c</Filename>
<Filename SupArchList="IA32" ToolChainFamily="MSFT">Ia32/WriteMm1.c</Filename>
<Filename SupArchList="IA32" ToolChainFamily="MSFT">Ia32/WriteMm2.c</Filename>
<Filename SupArchList="IA32" ToolChainFamily="MSFT">Ia32/WriteMm3.c</Filename>
<Filename SupArchList="IA32" ToolChainFamily="MSFT">Ia32/WriteMm4.c</Filename>
<Filename SupArchList="IA32" ToolChainFamily="MSFT">Ia32/WriteMm5.c</Filename>
<Filename SupArchList="IA32" ToolChainFamily="MSFT">Ia32/WriteMm6.c</Filename>
<Filename SupArchList="IA32" ToolChainFamily="MSFT">Ia32/WriteMm7.c</Filename>
<Filename SupArchList="IA32" ToolChainFamily="MSFT">Ia32/Wbinvd.c</Filename>
<Filename SupArchList="X64">x86DisablePaging32.c</Filename>
<Filename SupArchList="X64">x86DisablePaging64.c</Filename>
<Filename SupArchList="X64">x86EnablePaging32.c</Filename>
<Filename SupArchList="X64">x86EnablePaging64.c</Filename>
<Filename SupArchList="X64">x86FxRestore.c</Filename>
<Filename SupArchList="X64">x86FxSave.c</Filename>
<Filename SupArchList="X64">x86GetInterruptState.c</Filename>
<Filename SupArchList="X64">x86MemoryFence.c</Filename>
<Filename SupArchList="X64">x86Msr.c</Filename>
<Filename SupArchList="X64">x86ReadGdtr.c</Filename>
<Filename SupArchList="X64">x86ReadIdtr.c</Filename>
<Filename SupArchList="X64">x86Thunk.c</Filename>
<Filename SupArchList="X64">x86WriteGdtr.c</Filename>
<Filename SupArchList="X64">x86WriteIdtr.c</Filename>
<Filename SupArchList="X64">Unaligned.c</Filename>
<Filename SupArchList="X64">Math64.c</Filename>
<Filename SupArchList="X64">X64/Non-existing.c</Filename>
<Filename SupArchList="X64">X64/SwitchStack.asm</Filename>
<Filename SupArchList="X64">X64/SetJump.asm</Filename>
<Filename SupArchList="X64">X64/LongJump.asm</Filename>
<Filename SupArchList="X64">X64/CpuId.asm</Filename>
<Filename SupArchList="X64">X64/CpuIdEx.asm</Filename>
<Filename SupArchList="X64">X64/ReadEflags.asm</Filename>
<Filename SupArchList="X64" ToolChainFamily="MSFT">X64/ReadMsr64.c</Filename>
<Filename SupArchList="X64" ToolChainFamily="MSFT">X64/WriteMsr64.c</Filename>
<Filename SupArchList="X64">X64/ReadCr0.asm</Filename>
<Filename SupArchList="X64">X64/ReadCr2.asm</Filename>
<Filename SupArchList="X64">X64/ReadCr3.asm</Filename>
<Filename SupArchList="X64">X64/ReadCr4.asm</Filename>
<Filename SupArchList="X64">X64/WriteCr0.asm</Filename>
<Filename SupArchList="X64">X64/WriteCr2.asm</Filename>
<Filename SupArchList="X64">X64/WriteCr3.asm</Filename>
<Filename SupArchList="X64">X64/WriteCr4.asm</Filename>
<Filename SupArchList="X64">X64/ReadDr0.asm</Filename>
<Filename SupArchList="X64">X64/ReadDr1.asm</Filename>
<Filename SupArchList="X64">X64/ReadDr2.asm</Filename>
<Filename SupArchList="X64">X64/ReadDr3.asm</Filename>
<Filename SupArchList="X64">X64/ReadDr4.asm</Filename>
<Filename SupArchList="X64">X64/ReadDr5.asm</Filename>
<Filename SupArchList="X64">X64/ReadDr6.asm</Filename>
<Filename SupArchList="X64">X64/ReadDr7.asm</Filename>
<Filename SupArchList="X64">X64/WriteDr0.asm</Filename>
<Filename SupArchList="X64">X64/WriteDr1.asm</Filename>
<Filename SupArchList="X64">X64/WriteDr2.asm</Filename>
<Filename SupArchList="X64">X64/WriteDr3.asm</Filename>
<Filename SupArchList="X64">X64/WriteDr4.asm</Filename>
<Filename SupArchList="X64">X64/WriteDr5.asm</Filename>
<Filename SupArchList="X64">X64/WriteDr6.asm</Filename>
<Filename SupArchList="X64">X64/WriteDr7.asm</Filename>
<Filename SupArchList="X64">X64/ReadCs.asm</Filename>
<Filename SupArchList="X64">X64/ReadDs.asm</Filename>
<Filename SupArchList="X64">X64/ReadEs.asm</Filename>
<Filename SupArchList="X64">X64/ReadFs.asm</Filename>
<Filename SupArchList="X64">X64/ReadGs.asm</Filename>
<Filename SupArchList="X64">X64/ReadSs.asm</Filename>
<Filename SupArchList="X64">X64/ReadTr.asm</Filename>
<Filename SupArchList="X64">X64/ReadGdtr.asm</Filename>
<Filename SupArchList="X64">X64/WriteGdtr.asm</Filename>
<Filename SupArchList="X64">X64/ReadIdtr.asm</Filename>
<Filename SupArchList="X64">X64/WriteIdtr.asm</Filename>
<Filename SupArchList="X64">X64/ReadLdtr.asm</Filename>
<Filename SupArchList="X64">X64/WriteLdtr.asm</Filename>
<Filename SupArchList="X64">X64/FxSave.asm</Filename>
<Filename SupArchList="X64">X64/FxRestore.asm</Filename>
<Filename SupArchList="X64">X64/ReadMm0.asm</Filename>
<Filename SupArchList="X64">X64/ReadMm1.asm</Filename>
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<Filename SupArchList="X64">X64/Invd.asm</Filename>
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<Filename SupArchList="X64" ToolChainFamily="MSFT">X64/InterlockedIncrement.c</Filename>
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<Filename SupArchList="X64">X64/EnableDisableInterrupts.asm</Filename>
<Filename SupArchList="X64">X64/CpuSleep.asm</Filename>
<Filename SupArchList="X64">X64/CpuPause.asm</Filename>
<Filename SupArchList="X64" ToolChainFamily="MSFT">X64/CpuBreakpoint.c</Filename>
<Filename SupArchList="X64">X64/CpuFlushTlb.asm</Filename>
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<Filename SupArchList="EBC">Ebc/Synchronization.c</Filename>
<Filename SupArchList="EBC">Synchronization.c</Filename>
</SourceFiles>
<NonProcessedFiles>
<Filename>Ia32/ARShiftU64.asm</Filename>
<Filename>Ia32/CpuBreakpoint.asm</Filename>
<Filename>Ia32/CpuFlushTlb.asm</Filename>
<Filename>Ia32/CpuId.asm</Filename>
<Filename>Ia32/CpuIdEx.asm</Filename>
<Filename>Ia32/CpuPause.asm</Filename>
<Filename>Ia32/CpuSleep.asm</Filename>
<Filename>Ia32/DisableInterrupts.asm</Filename>
<Filename>Ia32/DisablePaging32.asm</Filename>
<Filename>Ia32/DivU64x32.asm</Filename>
<Filename>Ia32/DivU64x32Remainder.asm</Filename>
<Filename>Ia32/DivU64x64Remainder.asm</Filename>
<Filename>Ia32/EnableDisableInterrupts.asm</Filename>
<Filename>Ia32/EnableInterrupts.asm</Filename>
<Filename>Ia32/EnablePaging32.asm</Filename>
<Filename>Ia32/EnablePaging64.asm</Filename>
<Filename>Ia32/FlushCacheLine.asm</Filename>
<Filename>Ia32/FxRestore.asm</Filename>
<Filename>Ia32/FxSave.asm</Filename>
<Filename>Ia32/InterlockedCompareExchange32.asm</Filename>
<Filename>Ia32/InterlockedCompareExchange64.asm</Filename>
<Filename>Ia32/InterlockedDecrement.asm</Filename>
<Filename>Ia32/InterlockedIncrement.asm</Filename>
<Filename>Ia32/Invd.asm</Filename>
<Filename>Ia32/LongJump.asm</Filename>
<Filename>Ia32/LRotU64.asm</Filename>
<Filename>Ia32/LShiftU64.asm</Filename>
<Filename>Ia32/ModU64x32.asm</Filename>
<Filename>Ia32/Monitor.asm</Filename>
<Filename>Ia32/MultU64x32.asm</Filename>
<Filename>Ia32/MultU64x64.asm</Filename>
<Filename>Ia32/Mwait.asm</Filename>
<Filename>Ia32/ReadCr0.asm</Filename>
<Filename>Ia32/ReadCr2.asm</Filename>
<Filename>Ia32/ReadCr3.asm</Filename>
<Filename>Ia32/ReadCr4.asm</Filename>
<Filename>Ia32/ReadCs.asm</Filename>
<Filename>Ia32/ReadDr0.asm</Filename>
<Filename>Ia32/ReadDr1.asm</Filename>
<Filename>Ia32/ReadDr2.asm</Filename>
<Filename>Ia32/ReadDr3.asm</Filename>
<Filename>Ia32/ReadDr4.asm</Filename>
<Filename>Ia32/ReadDr5.asm</Filename>
<Filename>Ia32/ReadDr6.asm</Filename>
<Filename>Ia32/ReadDr7.asm</Filename>
<Filename>Ia32/ReadDs.asm</Filename>
<Filename>Ia32/ReadEflags.asm</Filename>
<Filename>Ia32/ReadEs.asm</Filename>
<Filename>Ia32/ReadFs.asm</Filename>
<Filename>Ia32/ReadGdtr.asm</Filename>
<Filename>Ia32/ReadGs.asm</Filename>
<Filename>Ia32/ReadIdtr.asm</Filename>
<Filename>Ia32/ReadLdtr.asm</Filename>
<Filename>Ia32/ReadMm0.asm</Filename>
<Filename>Ia32/ReadMm1.asm</Filename>
<Filename>Ia32/ReadMm2.asm</Filename>
<Filename>Ia32/ReadMm3.asm</Filename>
<Filename>Ia32/ReadMm4.asm</Filename>
<Filename>Ia32/ReadMm5.asm</Filename>
<Filename>Ia32/ReadMm6.asm</Filename>
<Filename>Ia32/ReadMm7.asm</Filename>
<Filename>Ia32/ReadMsr64.asm</Filename>
<Filename>Ia32/ReadPmc.asm</Filename>
<Filename>Ia32/ReadSs.asm</Filename>
<Filename>Ia32/ReadTr.asm</Filename>
<Filename>Ia32/ReadTsc.asm</Filename>
<Filename>Ia32/RRotU64.asm</Filename>
<Filename>Ia32/RShiftU64.asm</Filename>
<Filename>Ia32/SetJump.asm</Filename>
<Filename>Ia32/SwapBytes64.asm</Filename>
<Filename>Ia32/Thunk16.asm</Filename>
<Filename>Ia32/Wbinvd.asm</Filename>
<Filename>Ia32/WriteCr0.asm</Filename>
<Filename>Ia32/WriteCr2.asm</Filename>
<Filename>Ia32/WriteCr3.asm</Filename>
<Filename>Ia32/WriteCr4.asm</Filename>
<Filename>Ia32/WriteDr0.asm</Filename>
<Filename>Ia32/WriteDr1.asm</Filename>
<Filename>Ia32/WriteDr2.asm</Filename>
<Filename>Ia32/WriteDr3.asm</Filename>
<Filename>Ia32/WriteDr4.asm</Filename>
<Filename>Ia32/WriteDr5.asm</Filename>
<Filename>Ia32/WriteDr6.asm</Filename>
<Filename>Ia32/WriteDr7.asm</Filename>
<Filename>Ia32/WriteGdtr.asm</Filename>
<Filename>Ia32/WriteIdtr.asm</Filename>
<Filename>Ia32/WriteLdtr.asm</Filename>
<Filename>Ia32/WriteMm0.asm</Filename>
<Filename>Ia32/WriteMm1.asm</Filename>
<Filename>Ia32/WriteMm2.asm</Filename>
<Filename>Ia32/WriteMm3.asm</Filename>
<Filename>Ia32/WriteMm4.asm</Filename>
<Filename>Ia32/WriteMm5.asm</Filename>
<Filename>Ia32/WriteMm6.asm</Filename>
<Filename>Ia32/WriteMm7.asm</Filename>
<Filename>Ia32/WriteMsr64.asm</Filename>
</NonProcessedFiles>
<PackageDependencies>
<Package PackageGuid="5e0e9358-46b6-4ae2-8218-4ab8b9bbdcec"/>
</PackageDependencies>
<Externs>
<Specification>EFI_SPECIFICATION_VERSION 0x00020000</Specification>
<Specification>EDK_RELEASE_VERSION 0x00020000</Specification>
</Externs>
<PcdCoded>
<PcdEntry PcdItemType="FIXED_AT_BUILD">
<C_Name>PcdMaximumUnicodeStringLength</C_Name>
<TokenSpaceGuidCName>gEfiMdePkgTokenSpaceGuid</TokenSpaceGuidCName>
<HelpText>If PcdMaximumUnicodeStringLength is not zero, the maximum
number of characters (not counting the NULL-terminator) in a
Unicode string cannot exceed it.</HelpText>
</PcdEntry>
<PcdEntry PcdItemType="FIXED_AT_BUILD">
<C_Name>PcdMaximumAsciiStringLength</C_Name>
<TokenSpaceGuidCName>gEfiMdePkgTokenSpaceGuid</TokenSpaceGuidCName>
<HelpText>If PcdMaximumAsciiStringLength is not zero, the maximum number
of characters (not counting the NULL-terminator) in an ASCII
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</PcdEntry>
<PcdEntry PcdItemType="FIXED_AT_BUILD">
<C_Name>PcdMaximumLinkedListLength</C_Name>
<TokenSpaceGuidCName>gEfiMdePkgTokenSpaceGuid</TokenSpaceGuidCName>
<HelpText>If PcdMaximumLinkedListLength is not zero, the maximum number
of nodes (not counting the list header) in a linked list
cannot exceed it.</HelpText>
</PcdEntry>
<PcdEntry PcdItemType="FIXED_AT_BUILD">
<C_Name>PcdSpinLockTimeout</C_Name>
<TokenSpaceGuidCName>gEfiMdePkgTokenSpaceGuid</TokenSpaceGuidCName>
<HelpText>If PcdSpinLockTimeout is not zero, it stands for the timeout
value (unit: millisecond) for spin lock.</HelpText>
</PcdEntry>
</PcdCoded>
</ModuleSurfaceArea>

872
MdePkg/Library/BaseLib/BaseLibInternals.h Normal file
View File

@ -0,0 +1,872 @@
/** @file
Declaration of internal functions in BaseLib.
Copyright (c) 2006 - 2007, Intel Corporation<BR>
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
Module Name: BaseLibInternals.h
**/
#ifndef __BASE_LIB_INTERNALS__
#define __BASE_LIB_INTERNALS__
//
// Include common header file for this module.
//
#include "CommonHeader.h"
#define QUIENT_MAX_UINTN_DIVIDED_BY_10 ((UINTN) -1 / 10)
#define REMINDER_MAX_UINTN_DIVIDED_BY_10 ((UINTN) -1 % 10)
#define QUIENT_MAX_UINTN_DIVIDED_BY_16 ((UINTN) -1 / 16)
#define REMINDER_MAX_UINTN_DIVIDED_BY_16 ((UINTN) -1 % 16)
#define QUIENT_MAX_UINT64_DIVIDED_BY_10 ((UINT64) -1 / 10)
#define REMINDER_MAX_UINT64_DIVIDED_BY_10 ((UINT64) -1 % 10)
#define QUIENT_MAX_UINT64_DIVIDED_BY_16 ((UINT64) -1 / 16)
#define REMINDER_MAX_UINT64_DIVIDED_BY_16 ((UINT64) -1 % 16)
//
// Math functions
//
/**
Shifts a 64-bit integer left between 0 and 63 bits. The low bits
are filled with zeros. The shifted value is returned.
This function shifts the 64-bit value Operand to the left by Count bits. The
low Count bits are set to zero. The shifted value is returned.
@param Operand The 64-bit operand to shift left.
@param Count The number of bits to shift left.
@return Operand << Count
**/
UINT64
EFIAPI
InternalMathLShiftU64 (
IN UINT64 Operand,
IN UINTN Count
);
/**
Shifts a 64-bit integer right between 0 and 63 bits. This high bits
are filled with zeros. The shifted value is returned.
This function shifts the 64-bit value Operand to the right by Count bits. The
high Count bits are set to zero. The shifted value is returned.
@param Operand The 64-bit operand to shift right.
@param Count The number of bits to shift right.
@return Operand >> Count
**/
UINT64
EFIAPI
InternalMathRShiftU64 (
IN UINT64 Operand,
IN UINTN Count
);
/**
Shifts a 64-bit integer right between 0 and 63 bits. The high bits
are filled with original integer's bit 63. The shifted value is returned.
This function shifts the 64-bit value Operand to the right by Count bits. The
high Count bits are set to bit 63 of Operand. The shifted value is returned.
@param Operand The 64-bit operand to shift right.
@param Count The number of bits to shift right.
@return Operand arithmetically shifted right by Count
**/
UINT64
EFIAPI
InternalMathARShiftU64 (
IN UINT64 Operand,
IN UINTN Count
);
/**
Rotates a 64-bit integer left between 0 and 63 bits, filling
the low bits with the high bits that were rotated.
This function rotates the 64-bit value Operand to the left by Count bits. The
low Count bits are fill with the high Count bits of Operand. The rotated
value is returned.
@param Operand The 64-bit operand to rotate left.
@param Count The number of bits to rotate left.
@return Operand <<< Count
**/
UINT64
EFIAPI
InternalMathLRotU64 (
IN UINT64 Operand,
IN UINTN Count
);
/**
Rotates a 64-bit integer right between 0 and 63 bits, filling
the high bits with the high low bits that were rotated.
This function rotates the 64-bit value Operand to the right by Count bits.
The high Count bits are fill with the low Count bits of Operand. The rotated
value is returned.
@param Operand The 64-bit operand to rotate right.
@param Count The number of bits to rotate right.
@return Operand >>> Count
**/
UINT64
EFIAPI
InternalMathRRotU64 (
IN UINT64 Operand,
IN UINTN Count
);
/**
Switches the endianess of a 64-bit integer.
This function swaps the bytes in a 64-bit unsigned value to switch the value
from little endian to big endian or vice versa. The byte swapped value is
returned.
@param Operand A 64-bit unsigned value.
@return The byte swaped Operand.
**/
UINT64
EFIAPI
InternalMathSwapBytes64 (
IN UINT64 Operand
);
/**
Multiples a 64-bit unsigned integer by a 32-bit unsigned integer
and generates a 64-bit unsigned result.
This function multiples the 64-bit unsigned value Multiplicand by the 32-bit
unsigned value Multiplier and generates a 64-bit unsigned result. This 64-
bit unsigned result is returned.
@param Multiplicand A 64-bit unsigned value.
@param Multiplier A 32-bit unsigned value.
@return Multiplicand * Multiplier
**/
UINT64
EFIAPI
InternalMathMultU64x32 (
IN UINT64 Multiplicand,
IN UINT32 Multiplier
);
/**
Multiples a 64-bit unsigned integer by a 64-bit unsigned integer
and generates a 64-bit unsigned result.
This function multiples the 64-bit unsigned value Multiplicand by the 64-bit
unsigned value Multiplier and generates a 64-bit unsigned result. This 64-
bit unsigned result is returned.
@param Multiplicand A 64-bit unsigned value.
@param Multiplier A 64-bit unsigned value.
@return Multiplicand * Multiplier
**/
UINT64
EFIAPI
InternalMathMultU64x64 (
IN UINT64 Multiplicand,
IN UINT64 Multiplier
);
/**
Divides a 64-bit unsigned integer by a 32-bit unsigned integer and
generates a 64-bit unsigned result.
This function divides the 64-bit unsigned value Dividend by the 32-bit
unsigned value Divisor and generates a 64-bit unsigned quotient. This
function returns the 64-bit unsigned quotient.
@param Dividend A 64-bit unsigned value.
@param Divisor A 32-bit unsigned value.
@return Dividend / Divisor
**/
UINT64
EFIAPI
InternalMathDivU64x32 (
IN UINT64 Dividend,
IN UINT32 Divisor
);
/**
Divides a 64-bit unsigned integer by a 32-bit unsigned integer and
generates a 32-bit unsigned remainder.
This function divides the 64-bit unsigned value Dividend by the 32-bit
unsigned value Divisor and generates a 32-bit remainder. This function
returns the 32-bit unsigned remainder.
@param Dividend A 64-bit unsigned value.
@param Divisor A 32-bit unsigned value.
@return Dividend % Divisor
**/
UINT32
EFIAPI
InternalMathModU64x32 (
IN UINT64 Dividend,
IN UINT32 Divisor
);
/**
Divides a 64-bit unsigned integer by a 32-bit unsigned integer and
generates a 64-bit unsigned result and an optional 32-bit unsigned remainder.
This function divides the 64-bit unsigned value Dividend by the 32-bit
unsigned value Divisor and generates a 64-bit unsigned quotient. If Remainder
is not NULL, then the 32-bit unsigned remainder is returned in Remainder.
This function returns the 64-bit unsigned quotient.
@param Dividend A 64-bit unsigned value.
@param Divisor A 32-bit unsigned value.
@param Remainder A pointer to a 32-bit unsigned value. This parameter is
optional and may be NULL.
@return Dividend / Divisor
**/
UINT64
EFIAPI
InternalMathDivRemU64x32 (
IN UINT64 Dividend,
IN UINT32 Divisor,
OUT UINT32 *Remainder
);
/**
Divides a 64-bit unsigned integer by a 64-bit unsigned integer and
generates a 64-bit unsigned result and an optional 64-bit unsigned remainder.
This function divides the 64-bit unsigned value Dividend by the 64-bit
unsigned value Divisor and generates a 64-bit unsigned quotient. If Remainder
is not NULL, then the 64-bit unsigned remainder is returned in Remainder.
This function returns the 64-bit unsigned quotient.
@param Dividend A 64-bit unsigned value.
@param Divisor A 64-bit unsigned value.
@param Remainder A pointer to a 64-bit unsigned value. This parameter is
optional and may be NULL.
@return Dividend / Divisor
**/
UINT64
EFIAPI
InternalMathDivRemU64x64 (
IN UINT64 Dividend,
IN UINT64 Divisor,
OUT UINT64 *Remainder
);
/**
Divides a 64-bit signed integer by a 64-bit signed integer and
generates a 64-bit signed result and a optional 64-bit signed remainder.
This function divides the 64-bit unsigned value Dividend by the 64-bit
unsigned value Divisor and generates a 64-bit unsigned quotient. If Remainder
is not NULL, then the 64-bit unsigned remainder is returned in Remainder.
This function returns the 64-bit unsigned quotient.
@param Dividend A 64-bit signed value.
@param Divisor A 64-bit signed value.
@param Remainder A pointer to a 64-bit signed value. This parameter is
optional and may be NULL.
@return Dividend / Divisor
**/
INT64
InternalMathDivRemS64x64 (
IN INT64 Dividend,
IN INT64 Divisor,
OUT INT64 *Remainder OPTIONAL
);
/**
Transfers control to a function starting with a new stack.
Transfers control to the function specified by EntryPoint using the
new stack specified by NewStack and passing in the parameters specified
by Context1 and Context2. Context1 and Context2 are optional and may
be NULL. The function EntryPoint must never return.
Marker will be ignored on IA-32, x64, and EBC.
IPF CPUs expect one additional parameter of type VOID * that specifies
the new backing store pointer.
If EntryPoint is NULL, then ASSERT().
If NewStack is NULL, then ASSERT().
@param EntryPoint A pointer to function to call with the new stack.
@param Context1 A pointer to the context to pass into the EntryPoint
function.
@param Context2 A pointer to the context to pass into the EntryPoint
function.
@param NewStack A pointer to the new stack to use for the EntryPoint
function.
@param Marker VA_LIST marker for the variable argument list.
**/
VOID
EFIAPI
InternalSwitchStack (
IN SWITCH_STACK_ENTRY_POINT EntryPoint,
IN VOID *Context1, OPTIONAL
IN VOID *Context2, OPTIONAL
IN VOID *NewStack,
IN VA_LIST Marker
);
/**
Worker function that locates the Node in the List
By searching the List, finds the location of the Node in List. At the same time,
verifies the validity of this list.
If List is NULL, then ASSERT().
If List->ForwardLink is NULL, then ASSERT().
If List->backLink is NULL, then ASSERT().
If Node is NULL, then ASSERT();
If PcdMaximumLinkedListLenth is not zero, and prior to insertion the number
of nodes in ListHead, including the ListHead node, is greater than or
equal to PcdMaximumLinkedListLength, then ASSERT().
@param List A pointer to a node in a linked list.
@param Node A pointer to one nod.
@retval TRUE Node is in List
@retval FALSE Node isn't in List, or List is invalid
**/
BOOLEAN
IsNodeInList (
IN CONST LIST_ENTRY *List,
IN CONST LIST_ENTRY *Node
);
/**
Performs an atomic increment of an 32-bit unsigned integer.
Performs an atomic increment of the 32-bit unsigned integer specified by
Value and returns the incremented value. The increment operation must be
performed using MP safe mechanisms. The state of the return value is not
guaranteed to be MP safe.
@param Value A pointer to the 32-bit value to increment.
@return The incremented value.
**/
UINT32
EFIAPI
InternalSyncIncrement (
IN volatile UINT32 *Value
);
/**
Performs an atomic decrement of an 32-bit unsigned integer.
Performs an atomic decrement of the 32-bit unsigned integer specified by
Value and returns the decrement value. The decrement operation must be
performed using MP safe mechanisms. The state of the return value is not
guaranteed to be MP safe.
@param Value A pointer to the 32-bit value to decrement.
@return The decrement value.
**/
UINT32
EFIAPI
InternalSyncDecrement (
IN volatile UINT32 *Value
);
/**
Performs an atomic compare exchange operation on a 32-bit unsigned integer.
Performs an atomic compare exchange operation on the 32-bit unsigned integer
specified by Value. If Value is equal to CompareValue, then Value is set to
ExchangeValue and CompareValue is returned. If Value is not equal to CompareValue,
then Value is returned. The compare exchange operation must be performed using
MP safe mechanisms.
@param Value A pointer to the 32-bit value for the compare exchange
operation.
@param CompareValue 32-bit value used in compare operation.
@param ExchangeValue 32-bit value used in exchange operation.
@return The original *Value before exchange.
**/
UINT32
EFIAPI
InternalSyncCompareExchange32 (
IN volatile UINT32 *Value,
IN UINT32 CompareValue,
IN UINT32 ExchangeValue
);
/**
Performs an atomic compare exchange operation on a 64-bit unsigned integer.
Performs an atomic compare exchange operation on the 64-bit unsigned integer specified
by Value. If Value is equal to CompareValue, then Value is set to ExchangeValue and
CompareValue is returned. If Value is not equal to CompareValue, then Value is returned.
The compare exchange operation must be performed using MP safe mechanisms.
@param Value A pointer to the 64-bit value for the compare exchange
operation.
@param CompareValue 64-bit value used in compare operation.
@param ExchangeValue 64-bit value used in exchange operation.
@return The original *Value before exchange.
**/
UINT64
EFIAPI
InternalSyncCompareExchange64 (
IN volatile UINT64 *Value,
IN UINT64 CompareValue,
IN UINT64 ExchangeValue
);
/**
Worker function that returns a bit field from Operand
Returns the bitfield specified by the StartBit and the EndBit from Operand.
@param Operand Operand on which to perform the bitfield operation.
@param StartBit The ordinal of the least significant bit in the bit field.
@param EndBit The ordinal of the most significant bit in the bit field.
@return The bit field read.
**/
unsigned int
BitFieldReadUint (
IN unsigned int Operand,
IN UINTN StartBit,
IN UINTN EndBit
);
/**
Worker function that reads a bit field from Operand, performs a bitwise OR,
and returns the result.
Performs a bitwise OR between the bit field specified by StartBit and EndBit
in Operand and the value specified by AndData. All other bits in Operand are
preserved. The new value is returned.
@param Operand Operand on which to perform the bitfield operation.
@param StartBit The ordinal of the least significant bit in the bit field.
@param EndBit The ordinal of the most significant bit in the bit field.
@param OrData The value to OR with the read value from the value
@return The new value.
**/
unsigned int
BitFieldOrUint (
IN unsigned int Operand,
IN UINTN StartBit,
IN UINTN EndBit,
IN unsigned int OrData
);
/**
Worker function that reads a bit field from Operand, performs a bitwise AND,
and returns the result.
Performs a bitwise AND between the bit field specified by StartBit and EndBit
in Operand and the value specified by AndData. All other bits in Operand are
preserved. The new value is returned.
@param Operand Operand on which to perform the bitfield operation.
@param StartBit The ordinal of the least significant bit in the bit field.
@param EndBit The ordinal of the most significant bit in the bit field.
@param AndData The value to And with the read value from the value
@return The new value.
**/
unsigned int
BitFieldAndUint (
IN unsigned int Operand,
IN UINTN StartBit,
IN UINTN EndBit,
IN unsigned int AndData
);
/**
Worker function that checks ASSERT condition for JumpBuffer
Checks ASSERT condition for JumpBuffer.
If JumpBuffer is NULL, then ASSERT().
For IPF CPUs, if JumpBuffer is not aligned on a 16-byte boundary, then ASSERT().
@param JumpBuffer A pointer to CPU context buffer.
**/
VOID
InternalAssertJumpBuffer (
IN BASE_LIBRARY_JUMP_BUFFER *JumpBuffer
);
/**
Restores the CPU context that was saved with SetJump().
Restores the CPU context from the buffer specified by JumpBuffer.
This function never returns to the caller.
Instead is resumes execution based on the state of JumpBuffer.
@param JumpBuffer A pointer to CPU context buffer.
@param Value The value to return when the SetJump() context is restored.
**/
VOID
EFIAPI
InternalLongJump (
IN BASE_LIBRARY_JUMP_BUFFER *JumpBuffer,
IN UINTN Value
);
//
// Ia32 and x64 specific functions
//
#if defined (MDE_CPU_IA32) || defined (MDE_CPU_X64)
/**
Reads the current Global Descriptor Table Register(GDTR) descriptor.
Reads and returns the current GDTR descriptor and returns it in Gdtr. This
function is only available on IA-32 and X64.
@param Gdtr Pointer to a GDTR descriptor.
**/
VOID
EFIAPI
InternalX86ReadGdtr (
OUT IA32_DESCRIPTOR *Gdtr
);
/**
Writes the current Global Descriptor Table Register (GDTR) descriptor.
Writes and the current GDTR descriptor specified by Gdtr. This function is
only available on IA-32 and X64.
@param Gdtr Pointer to a GDTR descriptor.
**/
VOID
EFIAPI
InternalX86WriteGdtr (
IN CONST IA32_DESCRIPTOR *Gdtr
);
/**
Reads the current Interrupt Descriptor Table Register(GDTR) descriptor.
Reads and returns the current IDTR descriptor and returns it in Idtr. This
function is only available on IA-32 and X64.
@param Idtr Pointer to a IDTR descriptor.
**/
VOID
EFIAPI
InternalX86ReadIdtr (
OUT IA32_DESCRIPTOR *Idtr
);
/**
Writes the current Interrupt Descriptor Table Register(GDTR) descriptor.
Writes the current IDTR descriptor and returns it in Idtr. This function is
only available on IA-32 and X64.
@param Idtr Pointer to a IDTR descriptor.
**/
VOID
EFIAPI
InternalX86WriteIdtr (
IN CONST IA32_DESCRIPTOR *Idtr
);
/**
Save the current floating point/SSE/SSE2 context to a buffer.
Saves the current floating point/SSE/SSE2 state to the buffer specified by
Buffer. Buffer must be aligned on a 16-byte boundary. This function is only
available on IA-32 and X64.
@param Buffer Pointer to a buffer to save the floating point/SSE/SSE2 context.
**/
VOID
EFIAPI
InternalX86FxSave (
OUT IA32_FX_BUFFER *Buffer
);
/**
Restores the current floating point/SSE/SSE2 context from a buffer.
Restores the current floating point/SSE/SSE2 state from the buffer specified
by Buffer. Buffer must be aligned on a 16-byte boundary. This function is
only available on IA-32 and X64.
@param Buffer Pointer to a buffer to save the floating point/SSE/SSE2 context.
**/
VOID
EFIAPI
InternalX86FxRestore (
IN CONST IA32_FX_BUFFER *Buffer
);
/**
Enables the 32-bit paging mode on the CPU.
Enables the 32-bit paging mode on the CPU. CR0, CR3, CR4, and the page tables
must be properly initialized prior to calling this service. This function
assumes the current execution mode is 32-bit protected mode. This function is
only available on IA-32. After the 32-bit paging mode is enabled, control is
transferred to the function specified by EntryPoint using the new stack
specified by NewStack and passing in the parameters specified by Context1 and
Context2. Context1 and Context2 are optional and may be NULL. The function
EntryPoint must never return.
There are a number of constraints that must be followed before calling this
function:
1) Interrupts must be disabled.
2) The caller must be in 32-bit protected mode with flat descriptors. This
means all descriptors must have a base of 0 and a limit of 4GB.
3) CR0 and CR4 must be compatible with 32-bit protected mode with flat
descriptors.
4) CR3 must point to valid page tables that will be used once the transition
is complete, and those page tables must guarantee that the pages for this
function and the stack are identity mapped.
@param EntryPoint A pointer to function to call with the new stack after
paging is enabled.
@param Context1 A pointer to the context to pass into the EntryPoint
function as the first parameter after paging is enabled.
@param Context2 A pointer to the context to pass into the EntryPoint
function as the second parameter after paging is enabled.
@param NewStack A pointer to the new stack to use for the EntryPoint
function after paging is enabled.
**/
VOID
EFIAPI
InternalX86EnablePaging32 (
IN SWITCH_STACK_ENTRY_POINT EntryPoint,
IN VOID *Context1, OPTIONAL
IN VOID *Context2, OPTIONAL
IN VOID *NewStack
);
/**
Disables the 32-bit paging mode on the CPU.
Disables the 32-bit paging mode on the CPU and returns to 32-bit protected
mode. This function assumes the current execution mode is 32-paged protected
mode. This function is only available on IA-32. After the 32-bit paging mode
is disabled, control is transferred to the function specified by EntryPoint
using the new stack specified by NewStack and passing in the parameters
specified by Context1 and Context2. Context1 and Context2 are optional and
may be NULL. The function EntryPoint must never return.
There are a number of constraints that must be followed before calling this
function:
1) Interrupts must be disabled.
2) The caller must be in 32-bit paged mode.
3) CR0, CR3, and CR4 must be compatible with 32-bit paged mode.
4) CR3 must point to valid page tables that guarantee that the pages for
this function and the stack are identity mapped.
@param EntryPoint A pointer to function to call with the new stack after
paging is disabled.
@param Context1 A pointer to the context to pass into the EntryPoint
function as the first parameter after paging is disabled.
@param Context2 A pointer to the context to pass into the EntryPoint
function as the second parameter after paging is
disabled.
@param NewStack A pointer to the new stack to use for the EntryPoint
function after paging is disabled.
**/
VOID
EFIAPI
InternalX86DisablePaging32 (
IN SWITCH_STACK_ENTRY_POINT EntryPoint,
IN VOID *Context1, OPTIONAL
IN VOID *Context2, OPTIONAL
IN VOID *NewStack
);
/**
Enables the 64-bit paging mode on the CPU.
Enables the 64-bit paging mode on the CPU. CR0, CR3, CR4, and the page tables
must be properly initialized prior to calling this service. This function
assumes the current execution mode is 32-bit protected mode with flat
descriptors. This function is only available on IA-32. After the 64-bit
paging mode is enabled, control is transferred to the function specified by
EntryPoint using the new stack specified by NewStack and passing in the
parameters specified by Context1 and Context2. Context1 and Context2 are
optional and may be 0. The function EntryPoint must never return.
@param Cs The 16-bit selector to load in the CS before EntryPoint
is called. The descriptor in the GDT that this selector
references must be setup for long mode.
@param EntryPoint The 64-bit virtual address of the function to call with
the new stack after paging is enabled.
@param Context1 The 64-bit virtual address of the context to pass into
the EntryPoint function as the first parameter after
paging is enabled.
@param Context2 The 64-bit virtual address of the context to pass into
the EntryPoint function as the second parameter after
paging is enabled.
@param NewStack The 64-bit virtual address of the new stack to use for
the EntryPoint function after paging is enabled.
**/
VOID
EFIAPI
InternalX86EnablePaging64 (
IN UINT16 Cs,
IN UINT64 EntryPoint,
IN UINT64 Context1, OPTIONAL
IN UINT64 Context2, OPTIONAL
IN UINT64 NewStack
);
/**
Disables the 64-bit paging mode on the CPU.
Disables the 64-bit paging mode on the CPU and returns to 32-bit protected
mode. This function assumes the current execution mode is 64-paging mode.
This function is only available on X64. After the 64-bit paging mode is
disabled, control is transferred to the function specified by EntryPoint
using the new stack specified by NewStack and passing in the parameters
specified by Context1 and Context2. Context1 and Context2 are optional and
may be 0. The function EntryPoint must never return.
@param Cs The 16-bit selector to load in the CS before EntryPoint
is called. The descriptor in the GDT that this selector
references must be setup for 32-bit protected mode.
@param EntryPoint The 64-bit virtual address of the function to call with
the new stack after paging is disabled.
@param Context1 The 64-bit virtual address of the context to pass into
the EntryPoint function as the first parameter after
paging is disabled.
@param Context2 The 64-bit virtual address of the context to pass into
the EntryPoint function as the second parameter after
paging is disabled.
@param NewStack The 64-bit virtual address of the new stack to use for
the EntryPoint function after paging is disabled.
**/
VOID
EFIAPI
InternalX86DisablePaging64 (
IN UINT16 Cs,
IN UINT32 EntryPoint,
IN UINT32 Context1, OPTIONAL
IN UINT32 Context2, OPTIONAL
IN UINT32 NewStack
);
#elif defined (MDE_CPU_IPF)
//
//
// IPF specific functions
//
/**
Transfers control to a function starting with a new stack.
Transfers control to the function specified by EntryPoint using the new stack
specified by NewStack and passing in the parameters specified by Context1 and
Context2. Context1 and Context2 are optional and may be NULL. The function
EntryPoint must never return.
If EntryPoint is NULL, then ASSERT().
If NewStack is NULL, then ASSERT().
@param EntryPoint A pointer to function to call with the new stack.
@param Context1 A pointer to the context to pass into the EntryPoint
function.
@param Context2 A pointer to the context to pass into the EntryPoint
function.
@param NewStack A pointer to the new stack to use for the EntryPoint
function.
@param NewBsp A pointer to the new memory location for RSE backing
store.
**/
VOID
EFIAPI
AsmSwitchStackAndBackingStore (
IN SWITCH_STACK_ENTRY_POINT EntryPoint,
IN VOID *Context1, OPTIONAL
IN VOID *Context2, OPTIONAL
IN VOID *NewStack,
IN VOID *NewBsp
);
#else
#endif
#endif

872
MdePkg/Library/BaseLib/BitField.c Normal file
View File

@ -0,0 +1,872 @@
/** @file
Bit field functions of BaseLib.
Copyright (c) 2006, Intel Corporation<BR>
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
Module Name: BitField.c
**/
//
// Include common header file for this module.
//
#include "CommonHeader.h"
#include "BaseLibInternals.h"
/**
Worker function that returns a bit field from Operand
Returns the bitfield specified by the StartBit and the EndBit from Operand.
@param Operand Operand on which to perform the bitfield operation.
@param StartBit The ordinal of the least significant bit in the bit field.
@param EndBit The ordinal of the most significant bit in the bit field.
@return The bit field read.
**/
unsigned int
BitFieldReadUint (
IN unsigned int Operand,
IN UINTN StartBit,
IN UINTN EndBit
)
{
//
// ~((unsigned int)-2 << EndBit) is a mask in which bit[0] thru bit[EndBit]
// are 1's while bit[EndBit + 1] thru the most significant bit are 0's.
//
return (Operand & ~((unsigned int)-2 << EndBit)) >> StartBit;
}
/**
Worker function that reads a bit field from Operand, performs a bitwise OR,
and returns the result.
Performs a bitwise OR between the bit field specified by StartBit and EndBit
in Operand and the value specified by AndData. All other bits in Operand are
preserved. The new value is returned.
@param Operand Operand on which to perform the bitfield operation.
@param StartBit The ordinal of the least significant bit in the bit field.
@param EndBit The ordinal of the most significant bit in the bit field.
@param OrData The value to OR with the read value from the value
@return The new value.
**/
unsigned int
BitFieldOrUint (
IN unsigned int Operand,
IN UINTN StartBit,
IN UINTN EndBit,
IN unsigned int OrData
)
{
//
// ~((unsigned int)-2 << EndBit) is a mask in which bit[0] thru bit[EndBit]
// are 1's while bit[EndBit + 1] thru the most significant bit are 0's.
//
return Operand | ((OrData << StartBit) & ~((unsigned int) -2 << EndBit));
}
/**
Worker function that reads a bit field from Operand, performs a bitwise AND,
and returns the result.
Performs a bitwise AND between the bit field specified by StartBit and EndBit
in Operand and the value specified by AndData. All other bits in Operand are
preserved. The new value is returned.
@param Operand Operand on which to perform the bitfield operation.
@param StartBit The ordinal of the least significant bit in the bit field.
@param EndBit The ordinal of the most significant bit in the bit field.
@param AndData The value to And with the read value from the value
@return The new value.
**/
unsigned int
BitFieldAndUint (
IN unsigned int Operand,
IN UINTN StartBit,
IN UINTN EndBit,
IN unsigned int AndData
)
{
//
// ~((unsigned int)-2 << EndBit) is a mask in which bit[0] thru bit[EndBit]
// are 1's while bit[EndBit + 1] thru the most significant bit are 0's.
//
return Operand & ~((~AndData << StartBit) & ~((unsigned int) -2 << EndBit));
}
/**
Returns a bit field from an 8-bit value.
Returns the bitfield specified by the StartBit and the EndBit from Operand.
If 8-bit operations are not supported, then ASSERT().
If StartBit is greater than 7, then ASSERT().
If EndBit is greater than 7, then ASSERT().
If EndBit is less than StartBit, then ASSERT().
@param Operand Operand on which to perform the bitfield operation.
@param StartBit The ordinal of the least significant bit in the bit field.
Range 0..7.
@param EndBit The ordinal of the most significant bit in the bit field.
Range 0..7.
@return The bit field read.
**/
UINT8
EFIAPI
BitFieldRead8 (
IN UINT8 Operand,
IN UINTN StartBit,
IN UINTN EndBit
)
{
ASSERT (EndBit < sizeof (Operand) * 8);
ASSERT (StartBit <= EndBit);
return (UINT8)BitFieldReadUint (Operand, StartBit, EndBit);
}
/**
Writes a bit field to an 8-bit value, and returns the result.
Writes Value to the bit field specified by the StartBit and the EndBit in
Operand. All other bits in Operand are preserved. The new 8-bit value is
returned.
If 8-bit operations are not supported, then ASSERT().
If StartBit is greater than 7, then ASSERT().
If EndBit is greater than 7, then ASSERT().
If EndBit is less than StartBit, then ASSERT().
@param Operand Operand on which to perform the bitfield operation.
@param StartBit The ordinal of the least significant bit in the bit field.
Range 0..7.
@param EndBit The ordinal of the most significant bit in the bit field.
Range 0..7.
@param Value New value of the bit field.
@return The new 8-bit value.
**/
UINT8
EFIAPI
BitFieldWrite8 (
IN UINT8 Operand,
IN UINTN StartBit,
IN UINTN EndBit,
IN UINT8 Value
)
{
ASSERT (EndBit < sizeof (Operand) * 8);
ASSERT (StartBit <= EndBit);
return BitFieldAndThenOr8 (Operand, StartBit, EndBit, 0, Value);
}
/**
Reads a bit field from an 8-bit value, performs a bitwise OR, and returns the
result.
Performs a bitwise inclusive OR between the bit field specified by StartBit
and EndBit in Operand and the value specified by OrData. All other bits in
Operand are preserved. The new 8-bit value is returned.
If 8-bit operations are not supported, then ASSERT().
If StartBit is greater than 7, then ASSERT().
If EndBit is greater than 7, then ASSERT().
If EndBit is less than StartBit, then ASSERT().
@param Operand Operand on which to perform the bitfield operation.
@param StartBit The ordinal of the least significant bit in the bit field.
Range 0..7.
@param EndBit The ordinal of the most significant bit in the bit field.
Range 0..7.
@param OrData The value to OR with the read value from the value
@return The new 8-bit value.
**/
UINT8
EFIAPI
BitFieldOr8 (
IN UINT8 Operand,
IN UINTN StartBit,
IN UINTN EndBit,
IN UINT8 OrData
)
{
ASSERT (EndBit < sizeof (Operand) * 8);
ASSERT (StartBit <= EndBit);
return (UINT8)BitFieldOrUint (Operand, StartBit, EndBit, OrData);
}
/**
Reads a bit field from an 8-bit value, performs a bitwise AND, and returns
the result.
Performs a bitwise AND between the bit field specified by StartBit and EndBit
in Operand and the value specified by AndData. All other bits in Operand are
preserved. The new 8-bit value is returned.
If 8-bit operations are not supported, then ASSERT().
If StartBit is greater than 7, then ASSERT().
If EndBit is greater than 7, then ASSERT().
If EndBit is less than StartBit, then ASSERT().
@param Operand Operand on which to perform the bitfield operation.
@param StartBit The ordinal of the least significant bit in the bit field.
Range 0..7.
@param EndBit The ordinal of the most significant bit in the bit field.
Range 0..7.
@param AndData The value to AND with the read value from the value.
@return The new 8-bit value.
**/
UINT8
EFIAPI
BitFieldAnd8 (
IN UINT8 Operand,
IN UINTN StartBit,
IN UINTN EndBit,
IN UINT8 AndData
)
{
ASSERT (EndBit < sizeof (Operand) * 8);
ASSERT (StartBit <= EndBit);
return (UINT8)BitFieldAndUint (Operand, StartBit, EndBit, AndData);
}
/**
Reads a bit field from an 8-bit value, performs a bitwise AND followed by a
bitwise OR, and returns the result.
Performs a bitwise AND between the bit field specified by StartBit and EndBit
in Operand and the value specified by AndData, followed by a bitwise
inclusive OR with value specified by OrData. All other bits in Operand are
preserved. The new 8-bit value is returned.
If 8-bit operations are not supported, then ASSERT().
If StartBit is greater than 7, then ASSERT().
If EndBit is greater than 7, then ASSERT().
If EndBit is less than StartBit, then ASSERT().
@param Operand Operand on which to perform the bitfield operation.
@param StartBit The ordinal of the least significant bit in the bit field.
Range 0..7.
@param EndBit The ordinal of the most significant bit in the bit field.
Range 0..7.
@param AndData The value to AND with the read value from the value.
@param OrData The value to OR with the result of the AND operation.
@return The new 8-bit value.
**/
UINT8
EFIAPI
BitFieldAndThenOr8 (
IN UINT8 Operand,
IN UINTN StartBit,
IN UINTN EndBit,
IN UINT8 AndData,
IN UINT8 OrData
)
{
ASSERT (EndBit < sizeof (Operand) * 8);
ASSERT (StartBit <= EndBit);
return BitFieldOr8 (
BitFieldAnd8 (Operand, StartBit, EndBit, AndData),
StartBit,
EndBit,
OrData
);
}
/**
Returns a bit field from a 16-bit value.
Returns the bitfield specified by the StartBit and the EndBit from Operand.
If 16-bit operations are not supported, then ASSERT().
If StartBit is greater than 15, then ASSERT().
If EndBit is greater than 15, then ASSERT().
If EndBit is less than StartBit, then ASSERT().
@param Operand Operand on which to perform the bitfield operation.
@param StartBit The ordinal of the least significant bit in the bit field.
Range 0..15.
@param EndBit The ordinal of the most significant bit in the bit field.
Range 0..15.
@return The bit field read.
**/
UINT16
EFIAPI
BitFieldRead16 (
IN UINT16 Operand,
IN UINTN StartBit,
IN UINTN EndBit
)
{
ASSERT (EndBit < sizeof (Operand) * 8);
ASSERT (StartBit <= EndBit);
return (UINT16)BitFieldReadUint (Operand, StartBit, EndBit);
}
/**
Writes a bit field to a 16-bit value, and returns the result.
Writes Value to the bit field specified by the StartBit and the EndBit in
Operand. All other bits in Operand are preserved. The new 16-bit value is
returned.
If 16-bit operations are not supported, then ASSERT().
If StartBit is greater than 15, then ASSERT().
If EndBit is greater than 15, then ASSERT().
If EndBit is less than StartBit, then ASSERT().
@param Operand Operand on which to perform the bitfield operation.
@param StartBit The ordinal of the least significant bit in the bit field.
Range 0..15.
@param EndBit The ordinal of the most significant bit in the bit field.
Range 0..15.
@param Value New value of the bit field.
@return The new 16-bit value.
**/
UINT16
EFIAPI
BitFieldWrite16 (
IN UINT16 Operand,
IN UINTN StartBit,
IN UINTN EndBit,
IN UINT16 Value
)
{
ASSERT (EndBit < sizeof (Operand) * 8);
ASSERT (StartBit <= EndBit);
return BitFieldAndThenOr16 (Operand, StartBit, EndBit, 0, Value);
}
/**
Reads a bit field from a 16-bit value, performs a bitwise OR, and returns the
result.
Performs a bitwise inclusive OR between the bit field specified by StartBit
and EndBit in Operand and the value specified by OrData. All other bits in
Operand are preserved. The new 16-bit value is returned.
If 16-bit operations are not supported, then ASSERT().
If StartBit is greater than 15, then ASSERT().
If EndBit is greater than 15, then ASSERT().
If EndBit is less than StartBit, then ASSERT().
@param Operand Operand on which to perform the bitfield operation.
@param StartBit The ordinal of the least significant bit in the bit field.
Range 0..15.
@param EndBit The ordinal of the most significant bit in the bit field.
Range 0..15.
@param OrData The value to OR with the read value from the value
@return The new 16-bit value.
**/
UINT16
EFIAPI
BitFieldOr16 (
IN UINT16 Operand,
IN UINTN StartBit,
IN UINTN EndBit,
IN UINT16 OrData
)
{
ASSERT (EndBit < sizeof (Operand) * 8);
ASSERT (StartBit <= EndBit);
return (UINT16)BitFieldOrUint (Operand, StartBit, EndBit, OrData);
}
/**
Reads a bit field from a 16-bit value, performs a bitwise AND, and returns
the result.
Performs a bitwise AND between the bit field specified by StartBit and EndBit
in Operand and the value specified by AndData. All other bits in Operand are
preserved. The new 16-bit value is returned.
If 16-bit operations are not supported, then ASSERT().
If StartBit is greater than 15, then ASSERT().
If EndBit is greater than 15, then ASSERT().
If EndBit is less than StartBit, then ASSERT().
@param Operand Operand on which to perform the bitfield operation.
@param StartBit The ordinal of the least significant bit in the bit field.
Range 0..15.
@param EndBit The ordinal of the most significant bit in the bit field.
Range 0..15.
@param AndData The value to AND with the read value from the value
@return The new 16-bit value.
**/
UINT16
EFIAPI
BitFieldAnd16 (
IN UINT16 Operand,
IN UINTN StartBit,
IN UINTN EndBit,
IN UINT16 AndData
)
{
ASSERT (EndBit < sizeof (Operand) * 8);
ASSERT (StartBit <= EndBit);
return (UINT16)BitFieldAndUint (Operand, StartBit, EndBit, AndData);
}
/**
Reads a bit field from a 16-bit value, performs a bitwise AND followed by a
bitwise OR, and returns the result.
Performs a bitwise AND between the bit field specified by StartBit and EndBit
in Operand and the value specified by AndData, followed by a bitwise
inclusive OR with value specified by OrData. All other bits in Operand are
preserved. The new 16-bit value is returned.
If 16-bit operations are not supported, then ASSERT().
If StartBit is greater than 15, then ASSERT().
If EndBit is greater than 15, then ASSERT().
If EndBit is less than StartBit, then ASSERT().
@param Operand Operand on which to perform the bitfield operation.
@param StartBit The ordinal of the least significant bit in the bit field.
Range 0..15.
@param EndBit The ordinal of the most significant bit in the bit field.
Range 0..15.
@param AndData The value to AND with the read value from the value.
@param OrData The value to OR with the result of the AND operation.
@return The new 16-bit value.
**/
UINT16
EFIAPI
BitFieldAndThenOr16 (
IN UINT16 Operand,
IN UINTN StartBit,
IN UINTN EndBit,
IN UINT16 AndData,
IN UINT16 OrData
)
{
ASSERT (EndBit < sizeof (Operand) * 8);
ASSERT (StartBit <= EndBit);
return BitFieldOr16 (
BitFieldAnd16 (Operand, StartBit, EndBit, AndData),
StartBit,
EndBit,
OrData
);
}
/**
Returns a bit field from a 32-bit value.
Returns the bitfield specified by the StartBit and the EndBit from Operand.
If 32-bit operations are not supported, then ASSERT().
If StartBit is greater than 31, then ASSERT().
If EndBit is greater than 31, then ASSERT().
If EndBit is less than StartBit, then ASSERT().
@param Operand Operand on which to perform the bitfield operation.
@param StartBit The ordinal of the least significant bit in the bit field.
Range 0..31.
@param EndBit The ordinal of the most significant bit in the bit field.
Range 0..31.
@return The bit field read.
**/
UINT32
EFIAPI
BitFieldRead32 (
IN UINT32 Operand,
IN UINTN StartBit,
IN UINTN EndBit
)
{
ASSERT (EndBit < sizeof (Operand) * 8);
ASSERT (StartBit <= EndBit);
return (UINT32)BitFieldReadUint (Operand, StartBit, EndBit);
}
/**
Writes a bit field to a 32-bit value, and returns the result.
Writes Value to the bit field specified by the StartBit and the EndBit in
Operand. All other bits in Operand are preserved. The new 32-bit value is
returned.
If 32-bit operations are not supported, then ASSERT().
If StartBit is greater than 31, then ASSERT().
If EndBit is greater than 31, then ASSERT().
If EndBit is less than StartBit, then ASSERT().
@param Operand Operand on which to perform the bitfield operation.
@param StartBit The ordinal of the least significant bit in the bit field.
Range 0..31.
@param EndBit The ordinal of the most significant bit in the bit field.
Range 0..31.
@param Value New value of the bit field.
@return The new 32-bit value.
**/
UINT32
EFIAPI
BitFieldWrite32 (
IN UINT32 Operand,
IN UINTN StartBit,
IN UINTN EndBit,
IN UINT32 Value
)
{
ASSERT (EndBit < sizeof (Operand) * 8);
ASSERT (StartBit <= EndBit);
return BitFieldAndThenOr32 (Operand, StartBit, EndBit, 0, Value);
}
/**
Reads a bit field from a 32-bit value, performs a bitwise OR, and returns the
result.
Performs a bitwise inclusive OR between the bit field specified by StartBit
and EndBit in Operand and the value specified by OrData. All other bits in
Operand are preserved. The new 32-bit value is returned.
If 32-bit operations are not supported, then ASSERT().
If StartBit is greater than 31, then ASSERT().
If EndBit is greater than 31, then ASSERT().
If EndBit is less than StartBit, then ASSERT().
@param Operand Operand on which to perform the bitfield operation.
@param StartBit The ordinal of the least significant bit in the bit field.
Range 0..31.
@param EndBit The ordinal of the most significant bit in the bit field.
Range 0..31.
@param OrData The value to OR with the read value from the value
@return The new 32-bit value.
**/
UINT32
EFIAPI
BitFieldOr32 (
IN UINT32 Operand,
IN UINTN StartBit,
IN UINTN EndBit,
IN UINT32 OrData
)
{
ASSERT (EndBit < sizeof (Operand) * 8);
ASSERT (StartBit <= EndBit);
return (UINT32)BitFieldOrUint (Operand, StartBit, EndBit, OrData);
}
/**
Reads a bit field from a 32-bit value, performs a bitwise AND, and returns
the result.
Performs a bitwise AND between the bit field specified by StartBit and EndBit
in Operand and the value specified by AndData. All other bits in Operand are
preserved. The new 32-bit value is returned.
If 32-bit operations are not supported, then ASSERT().
If StartBit is greater than 31, then ASSERT().
If EndBit is greater than 31, then ASSERT().
If EndBit is less than StartBit, then ASSERT().
@param Operand Operand on which to perform the bitfield operation.
@param StartBit The ordinal of the least significant bit in the bit field.
Range 0..31.
@param EndBit The ordinal of the most significant bit in the bit field.
Range 0..31.
@param AndData The value to AND with the read value from the value
@return The new 32-bit value.
**/
UINT32
EFIAPI
BitFieldAnd32 (
IN UINT32 Operand,
IN UINTN StartBit,
IN UINTN EndBit,
IN UINT32 AndData
)
{
ASSERT (EndBit < sizeof (Operand) * 8);
ASSERT (StartBit <= EndBit);
return (UINT32)BitFieldAndUint (Operand, StartBit, EndBit, AndData);
}
/**
Reads a bit field from a 32-bit value, performs a bitwise AND followed by a
bitwise OR, and returns the result.
Performs a bitwise AND between the bit field specified by StartBit and EndBit
in Operand and the value specified by AndData, followed by a bitwise
inclusive OR with value specified by OrData. All other bits in Operand are
preserved. The new 32-bit value is returned.
If 32-bit operations are not supported, then ASSERT().
If StartBit is greater than 31, then ASSERT().
If EndBit is greater than 31, then ASSERT().
If EndBit is less than StartBit, then ASSERT().
@param Operand Operand on which to perform the bitfield operation.
@param StartBit The ordinal of the least significant bit in the bit field.
Range 0..31.
@param EndBit The ordinal of the most significant bit in the bit field.
Range 0..31.
@param AndData The value to AND with the read value from the value.
@param OrData The value to OR with the result of the AND operation.
@return The new 32-bit value.
**/
UINT32
EFIAPI
BitFieldAndThenOr32 (
IN UINT32 Operand,
IN UINTN StartBit,
IN UINTN EndBit,
IN UINT32 AndData,
IN UINT32 OrData
)
{
ASSERT (EndBit < sizeof (Operand) * 8);
ASSERT (StartBit <= EndBit);
return BitFieldOr32 (
BitFieldAnd32 (Operand, StartBit, EndBit, AndData),
StartBit,
EndBit,
OrData
);
}
/**
Returns a bit field from a 64-bit value.
Returns the bitfield specified by the StartBit and the EndBit from Operand.
If 64-bit operations are not supported, then ASSERT().
If StartBit is greater than 63, then ASSERT().
If EndBit is greater than 63, then ASSERT().
If EndBit is less than StartBit, then ASSERT().
@param Operand Operand on which to perform the bitfield operation.
@param StartBit The ordinal of the least significant bit in the bit field.
Range 0..63.
@param EndBit The ordinal of the most significant bit in the bit field.
Range 0..63.
@return The bit field read.
**/
UINT64
EFIAPI
BitFieldRead64 (
IN UINT64 Operand,
IN UINTN StartBit,
IN UINTN EndBit
)
{
ASSERT (EndBit < sizeof (Operand) * 8);
ASSERT (StartBit <= EndBit);
return RShiftU64 (Operand & ~LShiftU64 ((UINT64)-2, EndBit), StartBit);
}
/**
Writes a bit field to a 64-bit value, and returns the result.
Writes Value to the bit field specified by the StartBit and the EndBit in
Operand. All other bits in Operand are preserved. The new 64-bit value is
returned.
If 64-bit operations are not supported, then ASSERT().
If StartBit is greater than 63, then ASSERT().
If EndBit is greater than 63, then ASSERT().
If EndBit is less than StartBit, then ASSERT().
@param Operand Operand on which to perform the bitfield operation.
@param StartBit The ordinal of the least significant bit in the bit field.
Range 0..63.
@param EndBit The ordinal of the most significant bit in the bit field.
Range 0..63.
@param Value New value of the bit field.
@return The new 64-bit value.
**/
UINT64
EFIAPI
BitFieldWrite64 (
IN UINT64 Operand,
IN UINTN StartBit,
IN UINTN EndBit,
IN UINT64 Value
)
{
ASSERT (EndBit < sizeof (Operand) * 8);
ASSERT (StartBit <= EndBit);
return BitFieldAndThenOr64 (Operand, StartBit, EndBit, 0, Value);
}
/**
Reads a bit field from a 64-bit value, performs a bitwise OR, and returns the
result.
Performs a bitwise inclusive OR between the bit field specified by StartBit
and EndBit in Operand and the value specified by OrData. All other bits in
Operand are preserved. The new 64-bit value is returned.
If 64-bit operations are not supported, then ASSERT().
If StartBit is greater than 63, then ASSERT().
If EndBit is greater than 63, then ASSERT().
If EndBit is less than StartBit, then ASSERT().
@param Operand Operand on which to perform the bitfield operation.
@param StartBit The ordinal of the least significant bit in the bit field.
Range 0..63.
@param EndBit The ordinal of the most significant bit in the bit field.
Range 0..63.
@param OrData The value to OR with the read value from the value
@return The new 64-bit value.
**/
UINT64
EFIAPI
BitFieldOr64 (
IN UINT64 Operand,
IN UINTN StartBit,
IN UINTN EndBit,
IN UINT64 OrData
)
{
UINT64 Value1;
UINT64 Value2;
ASSERT (EndBit < sizeof (Operand) * 8);
ASSERT (StartBit <= EndBit);
Value1 = LShiftU64 (OrData, StartBit);
Value2 = LShiftU64 ((UINT64) - 2, EndBit);
return Operand | (Value1 & ~Value2);
}
/**
Reads a bit field from a 64-bit value, performs a bitwise AND, and returns
the result.
Performs a bitwise AND between the bit field specified by StartBit and EndBit
in Operand and the value specified by AndData. All other bits in Operand are
preserved. The new 64-bit value is returned.
If 64-bit operations are not supported, then ASSERT().
If StartBit is greater than 63, then ASSERT().
If EndBit is greater than 63, then ASSERT().
If EndBit is less than StartBit, then ASSERT().
@param Operand Operand on which to perform the bitfield operation.
@param StartBit The ordinal of the least significant bit in the bit field.
Range 0..63.
@param EndBit The ordinal of the most significant bit in the bit field.
Range 0..63.
@param AndData The value to AND with the read value from the value
@return The new 64-bit value.
**/
UINT64
EFIAPI
BitFieldAnd64 (
IN UINT64 Operand,
IN UINTN StartBit,
IN UINTN EndBit,
IN UINT64 AndData
)
{
UINT64 Value1;
UINT64 Value2;
ASSERT (EndBit < sizeof (Operand) * 8);
ASSERT (StartBit <= EndBit);
Value1 = LShiftU64 (~AndData, StartBit);
Value2 = LShiftU64 ((UINT64)-2, EndBit);
return Operand & ~(Value1 & ~Value2);
}
/**
Reads a bit field from a 64-bit value, performs a bitwise AND followed by a
bitwise OR, and returns the result.
Performs a bitwise AND between the bit field specified by StartBit and EndBit
in Operand and the value specified by AndData, followed by a bitwise
inclusive OR with value specified by OrData. All other bits in Operand are
preserved. The new 64-bit value is returned.
If 64-bit operations are not supported, then ASSERT().
If StartBit is greater than 63, then ASSERT().
If EndBit is greater than 63, then ASSERT().
If EndBit is less than StartBit, then ASSERT().
@param Operand Operand on which to perform the bitfield operation.
@param StartBit The ordinal of the least significant bit in the bit field.
Range 0..63.
@param EndBit The ordinal of the most significant bit in the bit field.
Range 0..63.
@param AndData The value to AND with the read value from the value.
@param OrData The value to OR with the result of the AND operation.
@return The new 64-bit value.
**/
UINT64
EFIAPI
BitFieldAndThenOr64 (
IN UINT64 Operand,
IN UINTN StartBit,
IN UINTN EndBit,
IN UINT64 AndData,
IN UINT64 OrData
)
{
ASSERT (EndBit < sizeof (Operand) * 8);
ASSERT (StartBit <= EndBit);
return BitFieldOr64 (
BitFieldAnd64 (Operand, StartBit, EndBit, AndData),
StartBit,
EndBit,
OrData
);
}

339
MdePkg/Library/BaseLib/CheckSum.c Normal file
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@ -0,0 +1,339 @@
/** @file
Utility functions to generate checksum based on 2's complement
algorithm.
Copyright (c) 2007, Intel Corporation<BR>
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
Module Name: CheckSum.c
**/
//
// Include common header file for this module.
//
#include "CommonHeader.h"
/**
Calculate the sum of all elements in a buffer in unit of UINT8.
During calculation, the carry bits are dropped.
This function calculates the sum of all elements in a buffer
in unit of UINT8. The carry bits in result of addition are dropped.
The result is returned as UINT8. If Length is Zero, then Zero is
returned.
If Buffer is NULL, then ASSERT().
If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT().
@param Buffer Pointer to the buffer to carry out the sum operation.
@param Length The size, in bytes, of Buffer .
@return Sum The sum of Buffer with carry bits dropped during additions.
**/
UINT8
EFIAPI
CalculateSum8 (
IN CONST UINT8 *Buffer,
IN UINTN Length
)
{
UINT8 Sum;
UINTN Count;
ASSERT (Buffer != NULL);
ASSERT (Length <= (MAX_ADDRESS - ((UINTN) Buffer) + 1));
for (Sum = 0, Count = 0; Count < Length; Count++) {
Sum = (UINT8) (Sum + *(Buffer + Count));
}
return Sum;
}
/**
Returns the two's complement checksum of all elements in a buffer
of 8-bit values.
This function first calculates the sum of the 8-bit values in the
buffer specified by Buffer and Length. The carry bits in the result
of addition are dropped. Then, the two's complement of the sum is
returned. If Length is 0, then 0 is returned.
If Buffer is NULL, then ASSERT().
If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT().
@param Buffer Pointer to the buffer to carry out the checksum operation.
@param Length The size, in bytes, of Buffer.
@return Checksum The 2's complement checksum of Buffer.
**/
UINT8
EFIAPI
CalculateCheckSum8 (
IN CONST UINT8 *Buffer,
IN UINTN Length
)
{
UINT8 CheckSum;
CheckSum = CalculateSum8 (Buffer, Length);
//
// Return the checksum based on 2's complement.
//
return (UINT8) (0x100 - CheckSum);
}
/**
Returns the sum of all elements in a buffer of 16-bit values. During
calculation, the carry bits are dropped.
This function calculates the sum of the 16-bit values in the buffer
specified by Buffer and Length. The carry bits in result of addition are dropped.
The 16-bit result is returned. If Length is 0, then 0 is returned.
If Buffer is NULL, then ASSERT().
If Buffer is not aligned on a 16-bit boundary, then ASSERT().
If Length is not aligned on a 16-bit boundary, then ASSERT().
If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT().
@param Buffer Pointer to the buffer to carry out the sum operation.
@param Length The size, in bytes, of Buffer.
@return Sum The sum of Buffer with carry bits dropped during additions.
**/
UINT16
EFIAPI
CalculateSum16 (
IN CONST UINT16 *Buffer,
IN UINTN Length
)
{
UINT16 Sum;
UINTN Count;
ASSERT (Buffer != NULL);
ASSERT (((UINTN) Buffer & 0x1) == 0);
ASSERT ((Length & 0x1) == 0);
ASSERT (Length <= (MAX_ADDRESS - ((UINTN) Buffer) + 1));
for (Sum = 0, Count = 0; Count < Length; Count++) {
Sum = (UINT16) (Sum + *(Buffer + Count));
}
return Sum;
}
/**
Returns the two's complement checksum of all elements in a buffer of
16-bit values.
This function first calculates the sum of the 16-bit values in the buffer
specified by Buffer and Length. The carry bits in the result of addition
are dropped. Then, the two's complement of the sum is returned. If Length
is 0, then 0 is returned.
If Buffer is NULL, then ASSERT().
If Buffer is not aligned on a 16-bit boundary, then ASSERT().
If Length is not aligned on a 16-bit boundary, then ASSERT().
If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT().
@param Buffer Pointer to the buffer to carry out the checksum operation.
@param Length The size, in bytes, of Buffer.
@return Checksum The 2's complement checksum of Buffer.
**/
UINT16
EFIAPI
CalculateCheckSum16 (
IN CONST UINT16 *Buffer,
IN UINTN Length
)
{
UINT16 CheckSum;
CheckSum = CalculateSum16 (Buffer, Length);
//
// Return the checksum based on 2's complement.
//
return (UINT16) (0x10000 - CheckSum);
}
/**
Returns the sum of all elements in a buffer of 32-bit values. During
calculation, the carry bits are dropped.
This function calculates the sum of the 32-bit values in the buffer
specified by Buffer and Length. The carry bits in result of addition are dropped.
The 32-bit result is returned. If Length is 0, then 0 is returned.
If Buffer is NULL, then ASSERT().
If Buffer is not aligned on a 32-bit boundary, then ASSERT().
If Length is not aligned on a 32-bit boundary, then ASSERT().
If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT().
@param Buffer Pointer to the buffer to carry out the sum operation.
@param Length The size, in bytes, of Buffer.
@return Sum The sum of Buffer with carry bits dropped during additions.
**/
UINT32
EFIAPI
CalculateSum32 (
IN CONST UINT32 *Buffer,
IN UINTN Length
)
{
UINT32 Sum;
UINTN Count;
ASSERT (Buffer != NULL);
ASSERT (((UINTN) Buffer & 0x3) == 0);
ASSERT ((Length & 0x3) == 0);
ASSERT (Length <= (MAX_ADDRESS - ((UINTN) Buffer) + 1));
for (Sum = 0, Count = 0; Count < Length; Count++) {
Sum = Sum + *(Buffer + Count);
}
return Sum;
}
/**
Returns the two's complement checksum of all elements in a buffer of
32-bit values.
This function first calculates the sum of the 32-bit values in the buffer
specified by Buffer and Length. The carry bits in the result of addition
are dropped. Then, the two's complement of the sum is returned. If Length
is 0, then 0 is returned.
If Buffer is NULL, then ASSERT().
If Buffer is not aligned on a 32-bit boundary, then ASSERT().
If Length is not aligned on a 32-bit boundary, then ASSERT().
If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT().
@param Buffer Pointer to the buffer to carry out the checksum operation.
@param Length The size, in bytes, of Buffer.
@return Checksum The 2's complement checksum of Buffer.
**/
UINT32
EFIAPI
CalculateCheckSum32 (
IN CONST UINT32 *Buffer,
IN UINTN Length
)
{
UINT32 CheckSum;
CheckSum = CalculateSum32 (Buffer, Length);
//
// Return the checksum based on 2's complement.
//
return (UINT32) ((UINT32)(-1) - CheckSum + 1);
}
/**
Returns the sum of all elements in a buffer of 64-bit values. During
calculation, the carry bits are dropped.
This function calculates the sum of the 64-bit values in the buffer
specified by Buffer and Length. The carry bits in result of addition are dropped.
The 64-bit result is returned. If Length is 0, then 0 is returned.
If Buffer is NULL, then ASSERT().
If Buffer is not aligned on a 64-bit boundary, then ASSERT().
If Length is not aligned on a 64-bit boundary, then ASSERT().
If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT().
@param Buffer Pointer to the buffer to carry out the sum operation.
@param Length The size, in bytes, of Buffer.
@return Sum The sum of Buffer with carry bits dropped during additions.
**/
UINT64
EFIAPI
CalculateSum64 (
IN CONST UINT64 *Buffer,
IN UINTN Length
)
{
UINT64 Sum;
UINTN Count;
ASSERT (Buffer != NULL);
ASSERT (((UINTN) Buffer & 0x7) == 0);
ASSERT ((Length & 0x7) == 0);
ASSERT (Length <= (MAX_ADDRESS - ((UINTN) Buffer) + 1));
for (Sum = 0, Count = 0; Count < Length; Count++) {
Sum = Sum + *(Buffer + Count);
}
return Sum;
}
/**
Returns the two's complement checksum of all elements in a buffer of
64-bit values.
This function first calculates the sum of the 64-bit values in the buffer
specified by Buffer and Length. The carry bits in the result of addition
are dropped. Then, the two's complement of the sum is returned. If Length
is 0, then 0 is returned.
If Buffer is NULL, then ASSERT().
If Buffer is not aligned on a 64-bit boundary, then ASSERT().
If Length is not aligned on a 64-bit boundary, then ASSERT().
If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT().
@param Buffer Pointer to the buffer to carry out the checksum operation.
@param Length The size, in bytes, of Buffer.
@return Checksum The 2's complement checksum of Buffer.
**/
UINT64
EFIAPI
CalculateCheckSum64 (
IN CONST UINT64 *Buffer,
IN UINTN Length
)
{
UINT64 CheckSum;
CheckSum = CalculateSum64 (Buffer, Length);
//
// Return the checksum based on 2's complement.
//
return (UINT64) ((UINT64)(-1) - CheckSum + 1);
}

35
MdePkg/Library/BaseLib/CommonHeader.h Normal file
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/**@file
Common header file shared by all source files.
This file includes package header files, library classes and protocol, PPI & GUID definitions.
Copyright (c) 2007 - 2007, Intel Corporation.
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef __COMMON_HEADER_H_
#define __COMMON_HEADER_H_
//
// The package level header files this module uses
//
#include <Base.h>
//
// The protocols, PPI and GUID defintions for this module
//
//
// The Library classes this module consumes
//
#include <Library/BaseLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/DebugLib.h>
#include <Library/TimerLib.h>
#include <Library/PcdLib.h>
#endif

72
MdePkg/Library/BaseLib/Cpu.c Normal file
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/** @file
Base Library CPU Functions for all architectures.
Copyright (c) 2006, Intel Corporation<BR>
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
Module Name: Cpu.c
**/
//
// Include common header file for this module.
//
#include "CommonHeader.h"
/**
Disables CPU interrupts and returns the interrupt state prior to the disable
operation.
Disables CPU interrupts and returns the interrupt state prior to the disable
operation.
@retval TRUE CPU interrupts were enabled on entry to this call.
@retval FALSE CPU interrupts were disabled on entry to this call.
**/
BOOLEAN
EFIAPI
SaveAndDisableInterrupts (
VOID
)
{
BOOLEAN InterruptState;
InterruptState = GetInterruptState ();
DisableInterrupts ();
return InterruptState;
}
/**
Set the current CPU interrupt state.
Sets the current CPU interrupt state to the state specified by
InterruptState. If InterruptState is TRUE, then interrupts are enabled. If
InterruptState is FALSE, then interrupts are disabled. InterruptState is
returned.
@param InterruptState TRUE if interrupts should enabled. FALSE if
interrupts should be disabled.
@return InterruptState
**/
BOOLEAN
EFIAPI
SetInterruptState (
IN BOOLEAN InterruptState
)
{
if (InterruptState) {
EnableInterrupts ();
} else {
DisableInterrupts ();
}
return InterruptState;
}

38
MdePkg/Library/BaseLib/CpuDeadLoop.c Normal file
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/** @file
Base Library CPU Functions for all architectures.
Copyright (c) 2006, Intel Corporation<BR>
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
//
// Include common header file for this module.
//
#include "CommonHeader.h"
/**
Executes an infinite loop.
Forces the CPU to execute an infinite loop. A debugger may be used to skip
past the loop and the code that follows the loop must execute properly. This
implies that the infinite loop must not cause the code that follow it to be
optimized away.
**/
VOID
EFIAPI
CpuDeadLoop (
VOID
)
{
volatile UINTN Index;
for (Index = 0; Index == 0;);
}

51
MdePkg/Library/BaseLib/DivS64x64Remainder.c Normal file
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/** @file
Math worker functions.
Copyright (c) 2006, Intel Corporation<BR>
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
//
// Include common header file for this module.
//
#include "CommonHeader.h"
#include "BaseLibInternals.h"
/**
Divides a 64-bit signed integer by a 64-bit signed integer and generates a
64-bit signed result and a optional 64-bit signed remainder.
This function divides the 64-bit signed value Dividend by the 64-bit signed
value Divisor and generates a 64-bit signed quotient. If Remainder is not
NULL, then the 64-bit signed remainder is returned in Remainder. This
function returns the 64-bit signed quotient.
If Divisor is 0, then ASSERT().
@param Dividend A 64-bit signed value.
@param Divisor A 64-bit signed value.
@param Remainder A pointer to a 64-bit signed value. This parameter is
optional and may be NULL.
@return Dividend / Divisor
**/
INT64
EFIAPI
DivS64x64Remainder (
IN INT64 Dividend,
IN INT64 Divisor,
OUT INT64 *Remainder OPTIONAL
)
{
ASSERT (Divisor != 0);
return InternalMathDivRemS64x64 (Dividend, Divisor, Remainder);
}

47
MdePkg/Library/BaseLib/DivU64x32.c Normal file
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/** @file
Math worker functions.
Copyright (c) 2006, Intel Corporation<BR>
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
//
// Include common header file for this module.
//
#include "CommonHeader.h"
#include "BaseLibInternals.h"
/**
Divides a 64-bit unsigned integer by a 32-bit unsigned integer and generates
a 64-bit unsigned result.
This function divides the 64-bit unsigned value Dividend by the 32-bit
unsigned value Divisor and generates a 64-bit unsigned quotient. This
function returns the 64-bit unsigned quotient.
If Divisor is 0, then ASSERT().
@param Dividend A 64-bit unsigned value.
@param Divisor A 32-bit unsigned value.
@return Dividend / Divisor
**/
UINT64
EFIAPI
DivU64x32 (
IN UINT64 Dividend,
IN UINT32 Divisor
)
{
ASSERT (Divisor != 0);
return InternalMathDivU64x32 (Dividend, Divisor);
}

51
MdePkg/Library/BaseLib/DivU64x32Remainder.c Normal file
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/** @file
Math worker functions.
Copyright (c) 2006, Intel Corporation<BR>
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
//
// Include common header file for this module.
//
#include "CommonHeader.h"
#include "BaseLibInternals.h"
/**
Divides a 64-bit unsigned integer by a 32-bit unsigned integer and generates
a 64-bit unsigned result and an optional 32-bit unsigned remainder.
This function divides the 64-bit unsigned value Dividend by the 32-bit
unsigned value Divisor and generates a 64-bit unsigned quotient. If Remainder
is not NULL, then the 32-bit unsigned remainder is returned in Remainder.
This function returns the 64-bit unsigned quotient.
If Divisor is 0, then ASSERT().
@param Dividend A 64-bit unsigned value.
@param Divisor A 32-bit unsigned value.
@param Remainder A pointer to a 32-bit unsigned value. This parameter is
optional and may be NULL.
@return Dividend / Divisor
**/
UINT64
EFIAPI
DivU64x32Remainder (
IN UINT64 Dividend,
IN UINT32 Divisor,
OUT UINT32 *Remainder OPTIONAL
)
{
ASSERT (Divisor != 0);
return InternalMathDivRemU64x32 (Dividend, Divisor, Remainder);
}

51
MdePkg/Library/BaseLib/DivU64x64Remainder.c Normal file
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/** @file
Math worker functions.
Copyright (c) 2006, Intel Corporation<BR>
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
//
// Include common header file for this module.
//
#include "CommonHeader.h"
#include "BaseLibInternals.h"
/**
Divides a 64-bit unsigned integer by a 64-bit unsigned integer and generates
a 64-bit unsigned result and an optional 64-bit unsigned remainder.
This function divides the 64-bit unsigned value Dividend by the 64-bit
unsigned value Divisor and generates a 64-bit unsigned quotient. If Remainder
is not NULL, then the 64-bit unsigned remainder is returned in Remainder.
This function returns the 64-bit unsigned quotient.
If Divisor is 0, then ASSERT().
@param Dividend A 64-bit unsigned value.
@param Divisor A 64-bit unsigned value.
@param Remainder A pointer to a 64-bit unsigned value. This parameter is
optional and may be NULL.
@return Dividend / Divisor
**/
UINT64
EFIAPI
DivU64x64Remainder (
IN UINT64 Dividend,
IN UINT64 Divisor,
OUT UINT64 *Remainder OPTIONAL
)
{
ASSERT (Divisor != 0);
return InternalMathDivRemU64x64 (Dividend, Divisor, Remainder);
}

46
MdePkg/Library/BaseLib/GetPowerOfTwo32.c Normal file
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/** @file
Math worker functions.
Copyright (c) 2006, Intel Corporation<BR>
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
//
// Include common header file for this module.
//
#include "CommonHeader.h"
#include "BaseLibInternals.h"
/**
Returns the value of the highest bit set in a 32-bit value. Equivalent to
1 << HighBitSet32(x).
This function computes the value of the highest bit set in the 32-bit value
specified by Operand. If Operand is zero, then zero is returned.
@param Operand The 32-bit operand to evaluate.
@return 1 << HighBitSet32(Operand)
@retval 0 Operand is zero.
**/
UINT32
EFIAPI
GetPowerOfTwo32 (
IN UINT32 Operand
)
{
if (Operand == 0) {
return 0;
}
return 1ul << HighBitSet32 (Operand);
}

46
MdePkg/Library/BaseLib/GetPowerOfTwo64.c Normal file
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/** @file
Math worker functions.
Copyright (c) 2006, Intel Corporation<BR>
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
//
// Include common header file for this module.
//
#include "CommonHeader.h"
#include "BaseLibInternals.h"
/**
Returns the value of the highest bit set in a 64-bit value. Equivalent to
1 << HighBitSet64(x).
This function computes the value of the highest bit set in the 64-bit value
specified by Operand. If Operand is zero, then zero is returned.
@param Operand The 64-bit operand to evaluate.
@return 1 << HighBitSet64(Operand)
@retval 0 Operand is zero.
**/
UINT64
EFIAPI
GetPowerOfTwo64 (
IN UINT64 Operand
)
{
if (Operand == 0) {
return 0;
}
return LShiftU64 (1, HighBitSet64 (Operand));
}

49
MdePkg/Library/BaseLib/HighBitSet32.c Normal file
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/** @file
Math worker functions.
Copyright (c) 2006, Intel Corporation<BR>
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
//
// Include common header file for this module.
//
#include "CommonHeader.h"
#include "BaseLibInternals.h"
/**
Returns the bit position of the highest bit set in a 32-bit value. Equivalent
to log2(x).
This function computes the bit position of the highest bit set in the 32-bit
value specified by Operand. If Operand is zero, then -1 is returned.
Otherwise, a value between 0 and 31 is returned.
@param Operand The 32-bit operand to evaluate.
@return Position of the highest bit set in Operand if found.
@retval -1 Operand is zero.
**/
INTN
EFIAPI
HighBitSet32 (
IN UINT32 Operand
)
{
INTN BitIndex;
if (Operand == 0) {
return - 1;
}
for (BitIndex = 31; (INT32)Operand > 0; BitIndex--, Operand <<= 1);
return BitIndex;
}

57
MdePkg/Library/BaseLib/HighBitSet64.c Normal file
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/** @file
Math worker functions.
Copyright (c) 2006, Intel Corporation<BR>
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
//
// Include common header file for this module.
//
#include "CommonHeader.h"
#include "BaseLibInternals.h"
/**
Returns the bit position of the highest bit set in a 64-bit value. Equivalent
to log2(x).
This function computes the bit position of the highest bit set in the 64-bit
value specified by Operand. If Operand is zero, then -1 is returned.
Otherwise, a value between 0 and 63 is returned.
@param Operand The 64-bit operand to evaluate.
@return Position of the highest bit set in Operand if found.
@retval -1 Operand is zero.
**/
INTN
EFIAPI
HighBitSet64 (
IN UINT64 Operand
)
{
if (Operand == (UINT32)Operand) {
//
// Operand is just a 32-bit integer
//
return HighBitSet32 ((UINT32)Operand);
}
//
// Operand is really a 64-bit integer
//
if (sizeof (UINTN) == sizeof (UINT32)) {
return HighBitSet32 (((UINT32*)&Operand)[1]) + 32;
} else {
return HighBitSet32 ((UINT32)RShiftU64 (Operand, 32)) + 32;
}
}

46
MdePkg/Library/BaseLib/Ia32/ARShiftU64.S Normal file
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//
// Include common header file for this module.
//
#include "CommonHeader.h"
#------------------------------------------------------------------------------
#
# Copyright (c) 2006, Intel Corporation
# All rights reserved. This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
# Module Name:
#
# ARShiftU64.asm
#
# Abstract:
#
# 64-bit arithmetic right shift function for IA-32
#
#------------------------------------------------------------------------------
.globl ASM_PFX(InternalMathARShiftU64)
#------------------------------------------------------------------------------
# UINT64
# EFIAPI
# InternalMathARShiftU64 (
# IN UINT64 Operand,
# IN UINTN Count
# );
#------------------------------------------------------------------------------
ASM_PFX(InternalMathARShiftU64):
movb 12(%esp), %cl
movl 8(%esp), %eax
cltd
testb $32, %cl
cmovz %eax, %edx
cmovz 4(%esp), %eax
shrdl %cl, %edx, %eax
sar %cl, %edx
ret

46
MdePkg/Library/BaseLib/Ia32/ARShiftU64.asm Normal file
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;------------------------------------------------------------------------------
;
; Copyright (c) 2006, Intel Corporation
; All rights reserved. This program and the accompanying materials
; are licensed and made available under the terms and conditions of the BSD License
; which accompanies this distribution. The full text of the license may be found at
; http://opensource.org/licenses/bsd-license.php
;
; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
;
; Module Name:
;
; ARShiftU64.asm
;
; Abstract:
;
; 64-bit arithmetic right shift function for IA-32
;
;------------------------------------------------------------------------------
.686
.model flat,C
.code
;------------------------------------------------------------------------------
; UINT64
; EFIAPI
; InternalMathARShiftU64 (
; IN UINT64 Operand,
; IN UINTN Count
; );
;------------------------------------------------------------------------------
InternalMathARShiftU64 PROC
mov cl, [esp + 12]
mov eax, [esp + 8]
cdq
test cl, 32
cmovz edx, eax
cmovz eax, [esp + 4]
shrd eax, edx, cl
sar edx, cl
ret
InternalMathARShiftU64 ENDP
END

38
MdePkg/Library/BaseLib/Ia32/ARShiftU64.c Normal file
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/** @file
64-bit arithmetic right shift function for IA-32.
Copyright (c) 2006 - 2007, Intel Corporation<BR>
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
//
// Include common header file for this module.
//
#include "CommonHeader.h"
UINT64
EFIAPI
InternalMathARShiftU64 (
IN UINT64 Operand,
IN UINTN Count
)
{
_asm {
mov cl, byte ptr [Count]
mov eax, dword ptr [Operand + 4]
cdq
test cl, 32
cmovz edx, eax
cmovz eax, dword ptr [Operand + 0]
shrd eax, edx, cl
sar edx, cl
}
}

39
MdePkg/Library/BaseLib/Ia32/CpuBreakpoint.S Normal file
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//
// Include common header file for this module.
//
#include "CommonHeader.h"
#------------------------------------------------------------------------------ ;
# Copyright (c) 2006, Intel Corporation
# All rights reserved. This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
# Module Name:
#
# CpuBreakpoint.s
#
# Abstract:
#
# CpuBreakpoint function
#
# Notes:
#
#------------------------------------------------------------------------------
.globl ASM_PFX(CpuBreakpoint)
#------------------------------------------------------------------------------
# VOID
# EFIAPI
# CpuBreakpoint (
# VOID
# );
#------------------------------------------------------------------------------
ASM_PFX(CpuBreakpoint):
int $3
ret

40
MdePkg/Library/BaseLib/Ia32/CpuBreakpoint.asm Normal file
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@ -0,0 +1,40 @@
;------------------------------------------------------------------------------ ;
; Copyright (c) 2006, Intel Corporation
; All rights reserved. This program and the accompanying materials
; are licensed and made available under the terms and conditions of the BSD License
; which accompanies this distribution. The full text of the license may be found at
; http://opensource.org/licenses/bsd-license.php
;
; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
;
; Module Name:
;
; CpuBreakpoint.Asm
;
; Abstract:
;
; CpuBreakpoint function
;
; Notes:
;
;------------------------------------------------------------------------------
.686
.model flat
.xmm
.code
;------------------------------------------------------------------------------
; VOID
; EFIAPI
; CpuBreakpoint (
; VOID
; );
;------------------------------------------------------------------------------
_CpuBreakpoint PROC
int 3
ret
_CpuBreakpoint ENDP
END

35
MdePkg/Library/BaseLib/Ia32/CpuBreakpoint.c Normal file
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/** @file
CpuBreakpoint function.
Copyright (c) 2006 - 2007, Intel Corporation<BR>
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
//
// Include common header file for this module.
//
#include "CommonHeader.h"
//
// Microsoft Visual Studio 7.1 Function Prototypes for I/O Intrinsics
//
void __debugbreak ();
#pragma intrinsic(__debugbreak)
VOID
EFIAPI
CpuBreakpoint (
VOID
)
{
__debugbreak ();
}

40
MdePkg/Library/BaseLib/Ia32/CpuFlushTlb.S Normal file
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//
// Include common header file for this module.
//
#include "CommonHeader.h"
#------------------------------------------------------------------------------ ;
# Copyright (c) 2006, Intel Corporation
# All rights reserved. This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
# Module Name:
#
# CpuFlushTlb.Asm
#
# Abstract:
#
# CpuFlushTlb function
#
# Notes:
#
#------------------------------------------------------------------------------
.globl ASM_PFX(CpuFlushTlb)
#------------------------------------------------------------------------------
# VOID
# EFIAPI
# CpuFlushTlb (
# VOID
# );
#------------------------------------------------------------------------------
ASM_PFX(CpuFlushTlb):
movl %cr3, %eax
movl %eax, %cr3
ret

40
MdePkg/Library/BaseLib/Ia32/CpuFlushTlb.asm Normal file
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@ -0,0 +1,40 @@
;------------------------------------------------------------------------------ ;
; Copyright (c) 2006, Intel Corporation
; All rights reserved. This program and the accompanying materials
; are licensed and made available under the terms and conditions of the BSD License
; which accompanies this distribution. The full text of the license may be found at
; http://opensource.org/licenses/bsd-license.php
;
; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
;
; Module Name:
;
; CpuFlushTlb.Asm
;
; Abstract:
;
; CpuFlushTlb function
;
; Notes:
;
;------------------------------------------------------------------------------
.386p
.model flat,C
.code
;------------------------------------------------------------------------------
; VOID
; EFIAPI
; CpuFlushTlb (
; VOID
; );
;------------------------------------------------------------------------------
CpuFlushTlb PROC
mov eax, cr3
mov cr3, eax ; moving to CR3 flushes TLB
ret
CpuFlushTlb ENDP
END

31
MdePkg/Library/BaseLib/Ia32/CpuFlushTlb.c Normal file
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@ -0,0 +1,31 @@
/** @file
CpuFlushTlb function.
Copyright (c) 2006 - 2007, Intel Corporation<BR>
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
//
// Include common header file for this module.
//
#include "CommonHeader.h"
VOID
EFIAPI
CpuFlushTlb (
VOID
)
{
_asm {
mov eax, cr3
mov cr3, eax
}
}

68
MdePkg/Library/BaseLib/Ia32/CpuId.S Normal file
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@ -0,0 +1,68 @@
//
// Include common header file for this module.
//
#include "CommonHeader.h"
#------------------------------------------------------------------------------
#
# Copyright (c) 2006, Intel Corporation
# All rights reserved. This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
# Module Name:
#
# CpuId.Asm
#
# Abstract:
#
# AsmCpuid function
#
# Notes:
#
#------------------------------------------------------------------------------
.globl ASM_PFX(AsmCpuid)
#------------------------------------------------------------------------------
# VOID
# EFIAPI
# AsmCpuid (
# IN UINT32 RegisterInEax,
# OUT UINT32 *RegisterOutEax OPTIONAL,
# OUT UINT32 *RegisterOutEbx OPTIONAL,
# OUT UINT32 *RegisterOutEcx OPTIONAL,
# OUT UINT32 *RegisterOutEdx OPTIONAL
# )
#------------------------------------------------------------------------------
ASM_PFX(AsmCpuid):
push %ebx
push %ebp
movl %esp, %ebp
movl 12(%ebp), %eax
cpuid
push %ecx
movl 16(%ebp), %ecx
jecxz L1
movl %eax, (%ecx)
L1:
movl 20(%ebp), %ecx
jecxz L2
movl %ebx, (%ecx)
L2:
movl 24(%ebp), %ecx
jecxz L3
popl (%ecx)
L3:
movl 28(%ebp), %ecx
jecxz L4
movl %edx, (%ecx)
L4:
movl 12(%ebp), %eax
leave
pop %ebx
ret

66
MdePkg/Library/BaseLib/Ia32/CpuId.asm Normal file
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@ -0,0 +1,66 @@
;------------------------------------------------------------------------------
;
; Copyright (c) 2006, Intel Corporation
; All rights reserved. This program and the accompanying materials
; are licensed and made available under the terms and conditions of the BSD License
; which accompanies this distribution. The full text of the license may be found at
; http://opensource.org/licenses/bsd-license.php
;
; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
;
; Module Name:
;
; CpuId.Asm
;
; Abstract:
;
; AsmCpuid function
;
; Notes:
;
;------------------------------------------------------------------------------
.586P
.model flat,C
.code
;------------------------------------------------------------------------------
; VOID
; EFIAPI
; AsmCpuid (
; IN UINT32 RegisterInEax,
; OUT UINT32 *RegisterOutEax OPTIONAL,
; OUT UINT32 *RegisterOutEbx OPTIONAL,
; OUT UINT32 *RegisterOutEcx OPTIONAL,
; OUT UINT32 *RegisterOutEdx OPTIONAL
; );
;------------------------------------------------------------------------------
AsmCpuid PROC USES ebx
push ebp
mov ebp, esp
mov eax, [ebp + 12]
cpuid
push ecx
mov ecx, [ebp + 16]
jecxz @F
mov [ecx], eax
@@:
mov ecx, [ebp + 20]
jecxz @F
mov [ecx], ebx
@@:
mov ecx, [ebp + 24]
jecxz @F
pop [ecx]
@@:
mov ecx, [ebp + 28]
jecxz @F
mov [ecx], edx
@@:
mov eax, [ebp + 12]
leave
ret
AsmCpuid ENDP
END

54
MdePkg/Library/BaseLib/Ia32/CpuId.c Normal file
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@ -0,0 +1,54 @@
/** @file
AsmCpuid function.
Copyright (c) 2006 - 2007, Intel Corporation<BR>
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
//
// Include common header file for this module.
//
#include "CommonHeader.h"
UINT32
EFIAPI
AsmCpuid (
IN UINT32 Index,
OUT UINT32 *RegisterEax, OPTIONAL
OUT UINT32 *RegisterEbx, OPTIONAL
OUT UINT32 *RegisterEcx, OPTIONAL
OUT UINT32 *RegisterEdx OPTIONAL
)
{
_asm {
mov eax, Index
cpuid
push ecx
mov ecx, RegisterEax
jecxz SkipEax
mov [ecx], eax
SkipEax:
mov ecx, RegisterEbx
jecxz SkipEbx
mov [ecx], ebx
SkipEbx:
pop eax
mov ecx, RegisterEcx
jecxz SkipEcx
mov [ecx], eax
SkipEcx:
mov ecx, RegisterEdx
jecxz SkipEdx
mov [ecx], edx
SkipEdx:
mov eax, Index
}
}

72
MdePkg/Library/BaseLib/Ia32/CpuIdEx.S Normal file
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//
// Include common header file for this module.
//
#include "CommonHeader.h"
#------------------------------------------------------------------------------
#
# Copyright (c) 2006, Intel Corporation
# All rights reserved. This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
# Module Name:
#
# CpuIdEx.Asm
#
# Abstract:
#
# AsmCpuidEx function
#
# Notes:
#
#------------------------------------------------------------------------------
.686:
.code:
#------------------------------------------------------------------------------
# UINT32
# EFIAPI
# AsmCpuidEx (
# IN UINT32 RegisterInEax,
# IN UINT32 RegisterInEcx,
# OUT UINT32 *RegisterOutEax OPTIONAL,
# OUT UINT32 *RegisterOutEbx OPTIONAL,
# OUT UINT32 *RegisterOutEcx OPTIONAL,
# OUT UINT32 *RegisterOutEdx OPTIONAL
# )
#------------------------------------------------------------------------------
.globl ASM_PFX(AsmCpuidEx)
ASM_PFX(AsmCpuidEx):
push %ebx
push %ebp
movl %esp, %ebp
movl 12(%ebp), %eax
movl 16(%ebp), %ecx
cpuid
push %ecx
movl 20(%ebp), %ecx
jecxz L1
movl %eax, (%ecx)
L1:
movl 24(%ebp), %ecx
jecxz L2
movl %ebx, (%ecx)
L2:
movl 28(%ebp), %ecx
jecxz L3
popl (%ecx)
L3:
movl 32(%ebp), %edx
jecxz L4
movl %edx, (%ecx)
L4:
movl 12(%ebp), %eax
leave
pop %ebx
ret

68
MdePkg/Library/BaseLib/Ia32/CpuIdEx.asm Normal file
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@ -0,0 +1,68 @@
;------------------------------------------------------------------------------
;
; Copyright (c) 2006, Intel Corporation
; All rights reserved. This program and the accompanying materials
; are licensed and made available under the terms and conditions of the BSD License
; which accompanies this distribution. The full text of the license may be found at
; http://opensource.org/licenses/bsd-license.php
;
; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
;
; Module Name:
;
; CpuIdEx.Asm
;
; Abstract:
;
; AsmCpuidEx function
;
; Notes:
;
;------------------------------------------------------------------------------
.686
.model flat,C
.code
;------------------------------------------------------------------------------
; UINT32
; EFIAPI
; AsmCpuidEx (
; IN UINT32 RegisterInEax,
; IN UINT32 RegisterInEcx,
; OUT UINT32 *RegisterOutEax OPTIONAL,
; OUT UINT32 *RegisterOutEbx OPTIONAL,
; OUT UINT32 *RegisterOutEcx OPTIONAL,
; OUT UINT32 *RegisterOutEdx OPTIONAL
; )
;------------------------------------------------------------------------------
AsmCpuidEx PROC USES ebx
push ebp
mov ebp, esp
mov eax, [ebp + 12]
mov ecx, [ebp + 16]
cpuid
push ecx
mov ecx, [ebp + 20]
jecxz @F
mov [ecx], eax
@@:
mov ecx, [ebp + 24]
jecxz @F
mov [ecx], ebx
@@:
mov ecx, [ebp + 28]
jecxz @F
pop [ecx]
@@:
mov edx, [ebp + 32]
jecxz @F
mov [ecx], edx
@@:
mov eax, [ebp + 12]
leave
ret
AsmCpuidEx ENDP
END

55
MdePkg/Library/BaseLib/Ia32/CpuIdEx.c Normal file
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@ -0,0 +1,55 @@
/** @file
AsmCpuidEx function.
Copyright (c) 2006 - 2007, Intel Corporation<BR>
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
//
// Include common header file for this module.
//
#include "CommonHeader.h"
UINT32
EFIAPI
AsmCpuidEx (
IN UINT32 Index,
IN UINT32 SubIndex,
OUT UINT32 *RegisterEax, OPTIONAL
OUT UINT32 *RegisterEbx, OPTIONAL
OUT UINT32 *RegisterEcx, OPTIONAL
OUT UINT32 *RegisterEdx OPTIONAL
)
{
_asm {
mov eax, Index
mov ecx, SubIndex
cpuid
push ecx
mov ecx, RegisterEax
jecxz SkipEax
mov [ecx], eax
SkipEax:
mov ecx, RegisterEbx
jecxz SkipEbx
mov [ecx], ebx
SkipEbx:
pop eax
mov ecx, RegisterEcx
jecxz SkipEcx
mov [ecx], eax
SkipEcx:
mov ecx, RegisterEdx
jecxz SkipEdx
mov [ecx], edx
SkipEdx:
mov eax, Index
}
}

39
MdePkg/Library/BaseLib/Ia32/CpuPause.S Normal file
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@ -0,0 +1,39 @@
//
// Include common header file for this module.
//
#include "CommonHeader.h"
#------------------------------------------------------------------------------ ;
# Copyright (c) 2006, Intel Corporation
# All rights reserved. This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
# Module Name:
#
# CpuPause.Asm
#
# Abstract:
#
# CpuPause function
#
# Notes:
#
#------------------------------------------------------------------------------
.globl ASM_PFX(CpuPause)
#------------------------------------------------------------------------------
# VOID
# EFIAPI
# CpuPause (
# VOID
# );
#------------------------------------------------------------------------------
ASM_PFX(CpuPause):
pause
ret

40
MdePkg/Library/BaseLib/Ia32/CpuPause.asm Normal file
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@ -0,0 +1,40 @@
;------------------------------------------------------------------------------ ;
; Copyright (c) 2006, Intel Corporation
; All rights reserved. This program and the accompanying materials
; are licensed and made available under the terms and conditions of the BSD License
; which accompanies this distribution. The full text of the license may be found at
; http://opensource.org/licenses/bsd-license.php
;
; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
;
; Module Name:
;
; CpuPause.Asm
;
; Abstract:
;
; CpuPause function
;
; Notes:
;
;------------------------------------------------------------------------------
.686
.model flat,C
.xmm
.code
;------------------------------------------------------------------------------
; VOID
; EFIAPI
; CpuPause (
; VOID
; );
;------------------------------------------------------------------------------
CpuPause PROC
pause
ret
CpuPause ENDP
END

30
MdePkg/Library/BaseLib/Ia32/CpuPause.c Normal file
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@ -0,0 +1,30 @@
/** @file
CpuPause function.
Copyright (c) 2006 - 2007, Intel Corporation<BR>
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
//
// Include common header file for this module.
//
#include "CommonHeader.h"
VOID
EFIAPI
CpuPause (
VOID
)
{
_asm {
pause
}
}

39
MdePkg/Library/BaseLib/Ia32/CpuSleep.S Normal file
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@ -0,0 +1,39 @@
//
// Include common header file for this module.
//
#include "CommonHeader.h"
#------------------------------------------------------------------------------ ;
# Copyright (c) 2006, Intel Corporation
# All rights reserved. This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
# Module Name:
#
# CpuSleep.Asm
#
# Abstract:
#
# CpuSleep function
#
# Notes:
#
#------------------------------------------------------------------------------
.globl ASM_PFX(CpuSleep)
#------------------------------------------------------------------------------
# VOID
# EFIAPI
# CpuSleep (
# VOID
# );
#------------------------------------------------------------------------------
ASM_PFX(CpuSleep):
hlt
ret

39
MdePkg/Library/BaseLib/Ia32/CpuSleep.asm Normal file
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@ -0,0 +1,39 @@
;------------------------------------------------------------------------------ ;
; Copyright (c) 2006, Intel Corporation
; All rights reserved. This program and the accompanying materials
; are licensed and made available under the terms and conditions of the BSD License
; which accompanies this distribution. The full text of the license may be found at
; http://opensource.org/licenses/bsd-license.php
;
; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
;
; Module Name:
;
; CpuSleep.Asm
;
; Abstract:
;
; CpuSleep function
;
; Notes:
;
;------------------------------------------------------------------------------
.386
.model flat,C
.code
;------------------------------------------------------------------------------
; VOID
; EFIAPI
; CpuSleep (
; VOID
; );
;------------------------------------------------------------------------------
CpuSleep PROC
hlt
ret
CpuSleep ENDP
END

30
MdePkg/Library/BaseLib/Ia32/CpuSleep.c Normal file
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@ -0,0 +1,30 @@
/** @file
CpuSleep function.
Copyright (c) 2006 - 2007, Intel Corporation<BR>
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
//
// Include common header file for this module.
//
#include "CommonHeader.h"
VOID
EFIAPI
CpuSleep (
VOID
)
{
_asm {
hlt
}
}

40
MdePkg/Library/BaseLib/Ia32/DisableInterrupts.S Normal file
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@ -0,0 +1,40 @@
//
// Include common header file for this module.
//
#include "CommonHeader.h"
#------------------------------------------------------------------------------
#
# Copyright (c) 2006, Intel Corporation
# All rights reserved. This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
# Module Name:
#
# DisableInterrupts.Asm
#
# Abstract:
#
# DisableInterrupts function
#
# Notes:
#
#------------------------------------------------------------------------------
.globl ASM_PFX(DisableInterrupts)
#------------------------------------------------------------------------------
# VOID
# EFIAPI
# DisableInterrupts (
# VOID
# );
#------------------------------------------------------------------------------
ASM_PFX(DisableInterrupts):
cli
ret

40
MdePkg/Library/BaseLib/Ia32/DisableInterrupts.asm Normal file
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@ -0,0 +1,40 @@
;------------------------------------------------------------------------------
;
; Copyright (c) 2006, Intel Corporation
; All rights reserved. This program and the accompanying materials
; are licensed and made available under the terms and conditions of the BSD License
; which accompanies this distribution. The full text of the license may be found at
; http://opensource.org/licenses/bsd-license.php
;
; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
;
; Module Name:
;
; DisableInterrupts.Asm
;
; Abstract:
;
; DisableInterrupts function
;
; Notes:
;
;------------------------------------------------------------------------------
.386p
.model flat,C
.code
;------------------------------------------------------------------------------
; VOID
; EFIAPI
; DisableInterrupts (
; VOID
; );
;------------------------------------------------------------------------------
DisableInterrupts PROC
cli
ret
DisableInterrupts ENDP
END

30
MdePkg/Library/BaseLib/Ia32/DisableInterrupts.c Normal file
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@ -0,0 +1,30 @@
/** @file
DisableInterrupts function.
Copyright (c) 2006 - 2007, Intel Corporation<BR>
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
//
// Include common header file for this module.
//
#include "CommonHeader.h"
VOID
EFIAPI
DisableInterrupts (
VOID
)
{
_asm {
cli
}
}

57
MdePkg/Library/BaseLib/Ia32/DisablePaging32.S Normal file
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@ -0,0 +1,57 @@
//
// Include common header file for this module.
//
#include "CommonHeader.h"
#------------------------------------------------------------------------------
#
# Copyright (c) 2006, Intel Corporation
# All rights reserved. This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
# Module Name:
#
# DisablePaging32.Asm
#
# Abstract:
#
# InternalX86DisablePaging32 function
#
# Notes:
#
#------------------------------------------------------------------------------
.globl ASM_PFX(InternalX86DisablePaging32)
#------------------------------------------------------------------------------
# VOID
# EFIAPI
# InternalX86DisablePaging32 (
# IN SWITCH_STACK_ENTRY_POINT EntryPoint,
# IN VOID *Context1, OPTIONAL
# IN VOID *Context2, OPTIONAL
# IN VOID *NewStack
# );
#------------------------------------------------------------------------------
ASM_PFX(InternalX86DisablePaging32):
movl 4(%esp), %ebx
movl 8(%esp), %ecx
movl 12(%esp), %edx
pushfl
pop %edi
cli
movl %cr0, %eax
btrl $31, %eax
movl 16(%esp), %esp
movl %eax, %cr0
push %edi
popfl
push %edx
push %ecx
call *%ebx
jmp .

57
MdePkg/Library/BaseLib/Ia32/DisablePaging32.asm Normal file
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@ -0,0 +1,57 @@
;------------------------------------------------------------------------------
;
; Copyright (c) 2006, Intel Corporation
; All rights reserved. This program and the accompanying materials
; are licensed and made available under the terms and conditions of the BSD License
; which accompanies this distribution. The full text of the license may be found at
; http://opensource.org/licenses/bsd-license.php
;
; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
;
; Module Name:
;
; DisablePaging32.Asm
;
; Abstract:
;
; AsmDisablePaging32 function
;
; Notes:
;
;------------------------------------------------------------------------------
.386
.model flat,C
.code
;------------------------------------------------------------------------------
; VOID
; EFIAPI
; InternalX86DisablePaging32 (
; IN SWITCH_STACK_ENTRY_POINT EntryPoint,
; IN VOID *Context1, OPTIONAL
; IN VOID *Context2, OPTIONAL
; IN VOID *NewStack
; );
;------------------------------------------------------------------------------
InternalX86DisablePaging32 PROC
mov ebx, [esp + 4]
mov ecx, [esp + 8]
mov edx, [esp + 12]
pushfd
pop edi ; save EFLAGS to edi
cli
mov eax, cr0
btr eax, 31
mov esp, [esp + 16]
mov cr0, eax
push edi
popfd ; restore EFLAGS from edi
push edx
push ecx
call ebx
jmp $ ; EntryPoint() should not return
InternalX86DisablePaging32 ENDP
END

51
MdePkg/Library/BaseLib/Ia32/DisablePaging32.c Normal file
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@ -0,0 +1,51 @@
/** @file
AsmDisablePaging32 function.
Copyright (c) 2006 - 2007, Intel Corporation<BR>
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
//
// Include common header file for this module.
//
#include "CommonHeader.h"
__declspec (naked)
VOID
EFIAPI
InternalX86DisablePaging32 (
IN SWITCH_STACK_ENTRY_POINT EntryPoint,
IN VOID *Context1, OPTIONAL
IN VOID *Context2, OPTIONAL
IN VOID *NewStack
)
{
_asm {
push ebp
mov ebp, esp
mov ebx, EntryPoint
mov ecx, Context1
mov edx, Context2
pushfd
pop edi // save EFLAGS to edi
cli
mov eax, cr0
btr eax, 31
mov esp, NewStack
mov cr0, eax
push edi
popfd // restore EFLAGS from edi
push edx
push ecx
call ebx
jmp $ // EntryPoint() should not return
}
}

59
MdePkg/Library/BaseLib/Ia32/DivS64x64Remainder.c Normal file
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@ -0,0 +1,59 @@
/** @file
Integer division worker functions for Ia32.
Copyright (c) 2006, Intel Corporation<BR>
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
Module Name: DivS64x64Remainder.c
**/
//
// Include common header file for this module.
//
#include "CommonHeader.h"
#include "../BaseLibInternals.h"
/**
Worker function that Divides a 64-bit signed integer by a 64-bit signed integer and
generates a 64-bit signed result and a optional 64-bit signed remainder.
This function divides the 64-bit unsigned value Dividend by the 64-bit
unsigned value Divisor and generates a 64-bit unsigned quotient. If Remainder
is not NULL, then the 64-bit unsigned remainder is returned in Remainder.
This function returns the 64-bit unsigned quotient.
@param Dividend A 64-bit signed value.
@param Divisor A 64-bit signed value.
@param Remainder A pointer to a 64-bit signed value. This parameter is
optional and may be NULL.
@return Dividend / Divisor
**/
INT64
InternalMathDivRemS64x64 (
IN INT64 Dividend,
IN INT64 Divisor,
OUT INT64 *Remainder OPTIONAL
)
{
INT64 Quot;
Quot = InternalMathDivRemU64x64 (
Dividend >= 0 ? Dividend : -Dividend,
Divisor >= 0 ? Divisor : -Divisor,
(UINT64 *) Remainder
);
if (Remainder != NULL && Dividend < 0) {
*Remainder = -*Remainder;
}
return (Dividend ^ Divisor) >= 0 ? Quot : -Quot;
}

46
MdePkg/Library/BaseLib/Ia32/DivU64x32.S Normal file
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//
// Include common header file for this module.
//
#include "CommonHeader.h"
#------------------------------------------------------------------------------
#
# Copyright (c) 2006, Intel Corporation
# All rights reserved. This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
# Module Name:
#
# DivU64x32.asm
#
# Abstract:
#
# Calculate the quotient of a 64-bit integer by a 32-bit integer
#
#------------------------------------------------------------------------------
.globl ASM_PFX(InternalMathDivU64x32)
#------------------------------------------------------------------------------
# UINT64
# EFIAPI
# InternalMathDivU64x32 (
# IN UINT64 Dividend,
# IN UINT32 Divisor
# );
#------------------------------------------------------------------------------
ASM_PFX(InternalMathDivU64x32):
movl 8(%esp), %eax
movl 12(%esp), %ecx
xorl %edx, %edx
divl %ecx
push %eax
movl 8(%esp), %eax
divl %ecx
pop %edx
ret

46
MdePkg/Library/BaseLib/Ia32/DivU64x32.asm Normal file
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;------------------------------------------------------------------------------
;
; Copyright (c) 2006, Intel Corporation
; All rights reserved. This program and the accompanying materials
; are licensed and made available under the terms and conditions of the BSD License
; which accompanies this distribution. The full text of the license may be found at
; http://opensource.org/licenses/bsd-license.php
;
; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
;
; Module Name:
;
; DivU64x32.asm
;
; Abstract:
;
; Calculate the quotient of a 64-bit integer by a 32-bit integer
;
;------------------------------------------------------------------------------
.386
.model flat,C
.code
;------------------------------------------------------------------------------
; UINT64
; EFIAPI
; InternalMathDivU64x32 (
; IN UINT64 Dividend,
; IN UINT32 Divisor
; );
;------------------------------------------------------------------------------
InternalMathDivU64x32 PROC
mov eax, [esp + 8]
mov ecx, [esp + 12]
xor edx, edx
div ecx
push eax ; save quotient on stack
mov eax, [esp + 8]
div ecx
pop edx ; restore high-order dword of the quotient
ret
InternalMathDivU64x32 ENDP
END

38
MdePkg/Library/BaseLib/Ia32/DivU64x32.c Normal file
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/** @file
Calculate the quotient of a 64-bit integer by a 32-bit integer
Copyright (c) 2006 - 2007, Intel Corporation<BR>
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
//
// Include common header file for this module.
//
#include "CommonHeader.h"
UINT64
EFIAPI
InternalMathDivU64x32 (
IN UINT64 Dividend,
IN UINT32 Divisor
)
{
_asm {
mov eax, dword ptr [Dividend + 4]
mov ecx, Divisor
xor edx, edx
div ecx
push eax ; save quotient on stack
mov eax, dword ptr [Dividend]
div ecx
pop edx ; restore high-order dword of the quotient
}
}

51
MdePkg/Library/BaseLib/Ia32/DivU64x32Remainder.S Normal file
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//
// Include common header file for this module.
//
#include "CommonHeader.h"
#------------------------------------------------------------------------------
#
# Copyright (c) 2006, Intel Corporation
# All rights reserved. This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
# Module Name:
#
# DivError.asm
#
# Abstract:
#
# Set error flag for all division functions
#
#------------------------------------------------------------------------------
.globl ASM_PFX(InternalMathDivRemU64x32)
#------------------------------------------------------------------------------
# UINT64
# EFIAPI
# InternalMathDivRemU64x32 (
# IN UINT64 Dividend,
# IN UINT32 Divisor,
# OUT UINT32 *Remainder
# );
#------------------------------------------------------------------------------
ASM_PFX(InternalMathDivRemU64x32):
movl 12(%esp), %ecx
movl 8(%esp), %eax
xorl %edx, %edx
divl %ecx
push %eax
movl 8(%esp), %eax
divl %ecx
movl 20(%esp), %ecx
jecxz L1
movl %edx, (%ecx)
L1:
pop %edx
ret

51
MdePkg/Library/BaseLib/Ia32/DivU64x32Remainder.asm Normal file
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;------------------------------------------------------------------------------
;
; Copyright (c) 2006, Intel Corporation
; All rights reserved. This program and the accompanying materials
; are licensed and made available under the terms and conditions of the BSD License
; which accompanies this distribution. The full text of the license may be found at
; http://opensource.org/licenses/bsd-license.php
;
; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
;
; Module Name:
;
; DivError.asm
;
; Abstract:
;
; Set error flag for all division functions
;
;------------------------------------------------------------------------------
.386
.model flat,C
.code
;------------------------------------------------------------------------------
; UINT64
; EFIAPI
; InternalMathDivRemU64x32 (
; IN UINT64 Dividend,
; IN UINT32 Divisor,
; OUT UINT32 *Remainder
; );
;------------------------------------------------------------------------------
InternalMathDivRemU64x32 PROC
mov ecx, [esp + 12] ; ecx <- divisor
mov eax, [esp + 8] ; eax <- dividend[32..63]
xor edx, edx
div ecx ; eax <- quotient[32..63], edx <- remainder
push eax
mov eax, [esp + 8] ; eax <- dividend[0..31]
div ecx ; eax <- quotient[0..31]
mov ecx, [esp + 20] ; ecx <- Remainder
jecxz @F ; abandon remainder if Remainder == NULL
mov [ecx], edx
@@:
pop edx ; edx <- quotient[32..63]
ret
InternalMathDivRemU64x32 ENDP
END

43
MdePkg/Library/BaseLib/Ia32/DivU64x32Remainder.c Normal file
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/** @file
Set error flag for all division functions
Copyright (c) 2006 - 2007, Intel Corporation<BR>
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
//
// Include common header file for this module.
//
#include "CommonHeader.h"
UINT64
EFIAPI
InternalMathDivRemU64x32 (
IN UINT64 Dividend,
IN UINT32 Divisor,
OUT UINT32 *Remainder
)
{
_asm {
mov ecx, Divisor
mov eax, dword ptr [Dividend + 4]
xor edx, edx
div ecx
push eax
mov eax, dword ptr [Dividend + 0]
div ecx
mov ecx, Remainder
jecxz RemainderNull // abandon remainder if Remainder == NULL
mov [ecx], edx
RemainderNull:
pop edx
}
}

94
MdePkg/Library/BaseLib/Ia32/DivU64x64Remainder.S Normal file
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//
// Include common header file for this module.
//
#include "CommonHeader.h"
#------------------------------------------------------------------------------
#
# Copyright (c) 2006, Intel Corporation
# All rights reserved. This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
# Module Name:
#
# DivU64x64Remainder.asm
#
# Abstract:
#
# Calculate the quotient of a 64-bit integer by a 64-bit integer and returns
# both the quotient and the remainder
#
#------------------------------------------------------------------------------
.globl ASM_PFX(InternalMathDivRemU64x32), ASM_PFX(InternalMathDivRemU64x64)
#------------------------------------------------------------------------------
# UINT64
# EFIAPI
# InternalMathDivRemU64x64 (
# IN UINT64 Dividend,
# IN UINT64 Divisor,
# OUT UINT64 *Remainder OPTIONAL
# );
#------------------------------------------------------------------------------
ASM_PFX(InternalMathDivRemU64x64):
movl 16(%esp), %ecx
testl %ecx, %ecx
jnz Hard
movl 20(%esp), %ecx
jecxz L1
and $0, 4(%ecx)
movl %ecx, 16(%esp)
L1:
jmp ASM_PFX(InternalMathDivRemU64x32)
Hard:
push %ebx
push %esi
push %edi
mov 20(%esp), %edx
mov 16(%esp), %eax
movl %edx, %edi
movl %eax, %esi
mov 24(%esp), %ebx
L2:
shrl %edx
rcrl $1, %eax
shrdl $1, %ecx, %ebx
shrl %ecx
jnz L2
divl %ebx
movl %eax, %ebx
movl 28(%esp), %ecx
mull 24(%esp)
imull %ebx, %ecx
addl %ecx, %edx
mov 32(%esp), %ecx
jc TooLarge
cmpl %edx, %edi
ja Correct
jb TooLarge
cmpl %eax, %esi
jae Correct
TooLarge:
decl %ebx
jecxz Return
sub 24(%esp), %eax
sbb 28(%esp), %edx
Correct:
jecxz Return
subl %eax, %esi
sbbl %edx, %edi
movl %esi, (%ecx)
movl %edi, 4(%ecx)
Return:
movl %ebx, %eax
xorl %edx, %edx
pop %edi
pop %esi
pop %ebx
ret

92
MdePkg/Library/BaseLib/Ia32/DivU64x64Remainder.asm Normal file
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@ -0,0 +1,92 @@
;------------------------------------------------------------------------------
;
; Copyright (c) 2006, Intel Corporation
; All rights reserved. This program and the accompanying materials
; are licensed and made available under the terms and conditions of the BSD License
; which accompanies this distribution. The full text of the license may be found at
; http://opensource.org/licenses/bsd-license.php
;
; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
;
; Module Name:
;
; DivU64x64Remainder.asm
;
; Abstract:
;
; Calculate the quotient of a 64-bit integer by a 64-bit integer and returns
; both the quotient and the remainder
;
;------------------------------------------------------------------------------
.386
.model flat,C
.code
EXTERN InternalMathDivRemU64x32:PROC
;------------------------------------------------------------------------------
; UINT64
; EFIAPI
; InternalMathDivRemU64x64 (
; IN UINT64 Dividend,
; IN UINT64 Divisor,
; OUT UINT64 *Remainder OPTIONAL
; );
;------------------------------------------------------------------------------
InternalMathDivRemU64x64 PROC
mov ecx, [esp + 16] ; ecx <- divisor[32..63]
test ecx, ecx
jnz _@DivRemU64x64 ; call _@DivRemU64x64 if Divisor > 2^32
mov ecx, [esp + 20]
jecxz @F
and dword ptr [ecx + 4], 0 ; zero high dword of remainder
mov [esp + 16], ecx ; set up stack frame to match DivRemU64x32
@@:
jmp InternalMathDivRemU64x32
InternalMathDivRemU64x64 ENDP
_@DivRemU64x64 PROC USES ebx esi edi
mov edx, dword ptr [esp + 20]
mov eax, dword ptr [esp + 16] ; edx:eax <- dividend
mov edi, edx
mov esi, eax ; edi:esi <- dividend
mov ebx, dword ptr [esp + 24] ; ecx:ebx <- divisor
@@:
shr edx, 1
rcr eax, 1
shrd ebx, ecx, 1
shr ecx, 1
jnz @B
div ebx
mov ebx, eax ; ebx <- quotient
mov ecx, [esp + 28] ; ecx <- high dword of divisor
mul dword ptr [esp + 24] ; edx:eax <- quotient * divisor[0..31]
imul ecx, ebx ; ecx <- quotient * divisor[32..63]
add edx, ecx ; edx <- (quotient * divisor)[32..63]
mov ecx, dword ptr [esp + 32] ; ecx <- addr for Remainder
jc @TooLarge ; product > 2^64
cmp edi, edx ; compare high 32 bits
ja @Correct
jb @TooLarge ; product > dividend
cmp esi, eax
jae @Correct ; product <= dividend
@TooLarge:
dec ebx ; adjust quotient by -1
jecxz @Return ; return if Remainder == NULL
sub eax, dword ptr [esp + 24]
sbb edx, dword ptr [esp + 28] ; edx:eax <- (quotient - 1) * divisor
@Correct:
jecxz @Return
sub esi, eax
sbb edi, edx ; edi:esi <- remainder
mov [ecx], esi
mov [ecx + 4], edi
@Return:
mov eax, ebx ; eax <- quotient
xor edx, edx ; quotient is 32 bits long
ret
_@DivRemU64x64 ENDP
END

71
MdePkg/Library/BaseLib/Ia32/DivU64x64Remainder.c Normal file
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/** @file
Calculate the quotient of a 64-bit integer by a 64-bit integer and returns
both the quotient and the remainderSet error flag for all division functions
Copyright (c) 2006 - 2007, Intel Corporation<BR>
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
//
// Include common header file for this module.
//
#include "CommonHeader.h"
UINT64
EFIAPI
InternalMathDivRemU64x64 (
IN UINT64 Dividend,
IN UINT64 Divisor,
OUT UINT64 *Remainder OPTIONAL
)
{
_asm {
mov edx, dword ptr [Dividend + 4]
mov eax, dword ptr [Dividend + 0] // edx:eax <- dividend
mov edi, edx
mov esi, eax // edi:esi <- dividend
mov ecx, dword ptr [Divisor + 4]
mov ebx, dword ptr [Divisor + 0] // ecx:ebx <- divisor
BitLoop:
shr edx, 1
rcr eax, 1
shrd ebx, ecx, 1
shr ecx, 1
jnz BitLoop
div ebx
mov ebx, eax // ebx <- quotient
mov ecx, dword ptr [Divisor + 4]
mul dword ptr [Divisor]
imul ecx, ebx
add edx, ecx
mov ecx, Remainder
jc TooLarge // product > 2^64
cmp edi, edx // compare high 32 bits
ja Correct
jb TooLarge // product > dividend
cmp esi, eax
jae Correct // product <= dividend
TooLarge:
dec ebx // adjust quotient by -1
jecxz Return // return if Remainder == NULL
sub eax, dword ptr [Divisor + 0]
sbb edx, dword ptr [Divisor + 4]
Correct:
jecxz Return
sub esi, eax
sbb edi, edx // edi:esi <- remainder
mov [ecx], esi
mov [ecx + 4], edi
Return:
mov eax, ebx // eax <- quotient
xor edx, edx
}
}

41
MdePkg/Library/BaseLib/Ia32/EnableDisableInterrupts.S Normal file
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@ -0,0 +1,41 @@
//
// Include common header file for this module.
//
#include "CommonHeader.h"
#------------------------------------------------------------------------------
#
# Copyright (c) 2006, Intel Corporation
# All rights reserved. This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
# Module Name:
#
# EnableDisableInterrupts.Asm
#
# Abstract:
#
# EnableDisableInterrupts function
#
# Notes:
#
#------------------------------------------------------------------------------
.globl ASM_PFX(EnableDisableInterrupts)
#------------------------------------------------------------------------------
# VOID
# EFIAPI
# EnableDisableInterrupts (
# VOID
# );
#------------------------------------------------------------------------------
ASM_PFX(EnableDisableInterrupts):
sti
cli
ret

41
MdePkg/Library/BaseLib/Ia32/EnableDisableInterrupts.asm Normal file
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;------------------------------------------------------------------------------
;
; Copyright (c) 2006, Intel Corporation
; All rights reserved. This program and the accompanying materials
; are licensed and made available under the terms and conditions of the BSD License
; which accompanies this distribution. The full text of the license may be found at
; http://opensource.org/licenses/bsd-license.php
;
; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
;
; Module Name:
;
; EnableDisableInterrupts.Asm
;
; Abstract:
;
; EnableDisableInterrupts function
;
; Notes:
;
;------------------------------------------------------------------------------
.386p
.model flat
.code
;------------------------------------------------------------------------------
; VOID
; EFIAPI
; EnableDisableInterrupts (
; VOID
; );
;------------------------------------------------------------------------------
_EnableDisableInterrupts PROC
sti
cli
ret
_EnableDisableInterrupts ENDP
END

33
MdePkg/Library/BaseLib/Ia32/EnableDisableInterrupts.c Normal file
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/** @file
EnableDisableInterrupts function
Copyright (c) 2006 - 2007, Intel Corporation<BR>
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
//
// Include common header file for this module.
//
#include "CommonHeader.h"
VOID
EFIAPI
EnableDisableInterrupts (
VOID
)
{
_asm {
sti
nop
nop
cli
}
}

40
MdePkg/Library/BaseLib/Ia32/EnableInterrupts.S Normal file
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@ -0,0 +1,40 @@
//
// Include common header file for this module.
//
#include "CommonHeader.h"
#------------------------------------------------------------------------------
#
# Copyright (c) 2006, Intel Corporation
# All rights reserved. This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
# Module Name:
#
# EnableInterrupts.Asm
#
# Abstract:
#
# EnableInterrupts function
#
# Notes:
#
#------------------------------------------------------------------------------
.globl ASM_PFX(EnableInterrupts)
#------------------------------------------------------------------------------
# VOID
# EFIAPI
# EnableInterrupts (
# VOID
# );
#------------------------------------------------------------------------------
ASM_PFX(EnableInterrupts):
sti
ret

40
MdePkg/Library/BaseLib/Ia32/EnableInterrupts.asm Normal file
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@ -0,0 +1,40 @@
;------------------------------------------------------------------------------
;
; Copyright (c) 2006, Intel Corporation
; All rights reserved. This program and the accompanying materials
; are licensed and made available under the terms and conditions of the BSD License
; which accompanies this distribution. The full text of the license may be found at
; http://opensource.org/licenses/bsd-license.php
;
; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
;
; Module Name:
;
; EnableInterrupts.Asm
;
; Abstract:
;
; EnableInterrupts function
;
; Notes:
;
;------------------------------------------------------------------------------
.386p
.model flat
.code
;------------------------------------------------------------------------------
; VOID
; EFIAPI
; EnableInterrupts (
; VOID
; );
;------------------------------------------------------------------------------
_EnableInterrupts PROC
sti
ret
_EnableInterrupts ENDP
END

30
MdePkg/Library/BaseLib/Ia32/EnableInterrupts.c Normal file
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@ -0,0 +1,30 @@
/** @file
EnableInterrupts function
Copyright (c) 2006 - 2007, Intel Corporation<BR>
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
//
// Include common header file for this module.
//
#include "CommonHeader.h"
VOID
EFIAPI
EnableInterrupts (
VOID
)
{
_asm {
sti
}
}

57
MdePkg/Library/BaseLib/Ia32/EnablePaging32.S Normal file
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@ -0,0 +1,57 @@
//
// Include common header file for this module.
//
#include "CommonHeader.h"
#------------------------------------------------------------------------------
#
# Copyright (c) 2006, Intel Corporation
# All rights reserved. This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
# Module Name:
#
# EnablePaging32.Asm
#
# Abstract:
#
# InternalX86EnablePaging32 function
#
# Notes:
#
#------------------------------------------------------------------------------
.globl ASM_PFX(InternalX86EnablePaging32)
#------------------------------------------------------------------------------
# VOID
# EFIAPI
# InternalX86EnablePaging32 (
# IN SWITCH_STACK_ENTRY_POINT EntryPoint,
# IN VOID *Context1, OPTIONAL
# IN VOID *Context2, OPTIONAL
# IN VOID *NewStack
# );
#------------------------------------------------------------------------------
ASM_PFX(InternalX86EnablePaging32):
movl 4(%esp), %ebx
movl 8(%esp), %ecx
movl 12(%esp), %edx
pushfl
pop %edi
cli
movl %cr0, %eax
btsl $31, %eax
movl 16(%esp), %esp
movl %eax, %cr0
push %edi
popfl
push %edx
push %ecx
call *%ebx
jmp .

57
MdePkg/Library/BaseLib/Ia32/EnablePaging32.asm Normal file
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@ -0,0 +1,57 @@
;------------------------------------------------------------------------------
;
; Copyright (c) 2006, Intel Corporation
; All rights reserved. This program and the accompanying materials
; are licensed and made available under the terms and conditions of the BSD License
; which accompanies this distribution. The full text of the license may be found at
; http://opensource.org/licenses/bsd-license.php
;
; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
;
; Module Name:
;
; EnablePaging32.Asm
;
; Abstract:
;
; AsmEnablePaging32 function
;
; Notes:
;
;------------------------------------------------------------------------------
.386
.model flat,C
.code
;------------------------------------------------------------------------------
; VOID
; EFIAPI
; InternalX86EnablePaging32 (
; IN SWITCH_STACK_ENTRY_POINT EntryPoint,
; IN VOID *Context1, OPTIONAL
; IN VOID *Context2, OPTIONAL
; IN VOID *NewStack
; );
;------------------------------------------------------------------------------
InternalX86EnablePaging32 PROC
mov ebx, [esp + 4]
mov ecx, [esp + 8]
mov edx, [esp + 12]
pushfd
pop edi ; save flags in edi
cli
mov eax, cr0
bts eax, 31
mov esp, [esp + 16]
mov cr0, eax
push edi
popfd ; restore flags
push edx
push ecx
call ebx
jmp $
InternalX86EnablePaging32 ENDP
END

51
MdePkg/Library/BaseLib/Ia32/EnablePaging32.c Normal file
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/** @file
AsmEnablePaging32 function
Copyright (c) 2006 - 2007, Intel Corporation<BR>
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
//
// Include common header file for this module.
//
#include "CommonHeader.h"
__declspec (naked)
VOID
EFIAPI
InternalX86EnablePaging32 (
IN SWITCH_STACK_ENTRY_POINT EntryPoint,
IN VOID *Context1, OPTIONAL
IN VOID *Context2, OPTIONAL
IN VOID *NewStack
)
{
_asm {
push ebp
mov ebp, esp
mov ebx, EntryPoint
mov ecx, Context1
mov edx, Context2
pushfd
pop edi
cli
mov eax, cr0
bts eax, 31
mov esp, NewStack
mov cr0, eax
push edi
popfd
push edx
push ecx
call ebx
jmp $
}
}

68
MdePkg/Library/BaseLib/Ia32/EnablePaging64.S Normal file
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@ -0,0 +1,68 @@
//
// Include common header file for this module.
//
#include "CommonHeader.h"
#------------------------------------------------------------------------------
#
# Copyright (c) 2006, Intel Corporation
# All rights reserved. This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
# Module Name:
#
# EnablePaging64.Asm
#
# Abstract:
#
# InternalX86EnablePaging64 function
#
# Notes:
#
#------------------------------------------------------------------------------
.globl ASM_PFX(InternalX86EnablePaging64)
#------------------------------------------------------------------------------
# VOID
# EFIAPI
# InternalX86EnablePaging64 (
# IN UINT16 CodeSelector,
# IN UINT64 EntryPoint,
# IN UINT64 Context1, OPTIONAL
# IN UINT64 Context2, OPTIONAL
# IN UINT64 NewStack
# );
#------------------------------------------------------------------------------
ASM_PFX(InternalX86EnablePaging64):
cli
movl $LongStart, (%esp)
movl %cr4, %eax
orb $0x20, %al
movl %eax, %cr4 # enable PAE
movl $0xc0000080, %ecx
rdmsr
orb $1, %ah # set LME
wrmsr
movl %cr0, %eax
btsl $31, %eax
movl %eax, %cr0 # enable paging
lret
LongStart: # long mode starts here
.byte 0x67, 0x48
movl (%esp), %ebx # mov rbx, [esp]
.byte 0x67, 0x48
movl 8(%esp), %ecx # mov rcx, [esp + 8]
.byte 0x67, 0x48
movl 0x10(%esp), %edx # mov rdx, [esp + 10h]
.byte 0x67, 0x48
movl 0x18(%esp), %esp # mov rsp, [esp + 18h]
.byte 0x48
addl $0x-20, %esp # add rsp, -20h
call *%ebx # call rbx
jmp .

73
MdePkg/Library/BaseLib/Ia32/EnablePaging64.asm Normal file
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@ -0,0 +1,73 @@
//
// Include common header file for this module.
//
#include "CommonHeader.h"
;------------------------------------------------------------------------------
;
; Copyright (c) 2006, Intel Corporation
; All rights reserved. This program and the accompanying materials
; are licensed and made available under the terms and conditions of the BSD License
; which accompanies this distribution. The full text of the license may be found at
; http://opensource.org/licenses/bsd-license.php
;
; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
;
; Module Name:
;
; EnablePaging64.Asm
;
; Abstract:
;
; AsmEnablePaging64 function
;
; Notes:
;
;------------------------------------------------------------------------------
.686p
.model flat,C
.code
;------------------------------------------------------------------------------
; VOID
; EFIAPI
; InternalX86EnablePaging64 (
; IN UINT16 Cs,
; IN UINT64 EntryPoint,
; IN UINT64 Context1, OPTIONAL
; IN UINT64 Context2, OPTIONAL
; IN UINT64 NewStack
; );
;------------------------------------------------------------------------------
InternalX86EnablePaging64 PROC
cli
mov [esp], @F ; offset for far retf, seg is the 1st arg
mov eax, cr4
or al, (1 SHL 5)
mov cr4, eax ; enable PAE
mov ecx, 0c0000080h
rdmsr
or ah, 1 ; set LME
wrmsr
mov eax, cr0
bts eax, 31 ; set PG
mov cr0, eax ; enable paging
retf ; topmost 2 dwords hold the address
@@: ; long mode starts here
DB 67h, 48h ; 32-bit address size, 64-bit operand size
mov ebx, [esp] ; mov rbx, [esp]
DB 67h, 48h
mov ecx, [esp + 8] ; mov rcx, [esp + 8]
DB 67h, 48h
mov edx, [esp + 10h] ; mov rdx, [esp + 10h]
DB 67h, 48h
mov esp, [esp + 18h] ; mov rsp, [esp + 18h]
DB 48h
add esp, -20h ; add rsp, -20h
call ebx ; call rbx
hlt ; no one should get here
InternalX86EnablePaging64 ENDP
END

41
MdePkg/Library/BaseLib/Ia32/FlushCacheLine.S Normal file
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@ -0,0 +1,41 @@
//
// Include common header file for this module.
//
#include "CommonHeader.h"
#------------------------------------------------------------------------------
#
# Copyright (c) 2006, Intel Corporation
# All rights reserved. This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
# Module Name:
#
# FlushCacheLine.Asm
#
# Abstract:
#
# AsmFlushCacheLine function
#
# Notes:
#
#------------------------------------------------------------------------------
.globl ASM_PFX(AsmFlushCacheLine)
#------------------------------------------------------------------------------
# VOID
# EFIAPI
# AsmFlushCacheLine (
# IN VOID *LinearAddress
# );
#------------------------------------------------------------------------------
ASM_PFX(AsmFlushCacheLine):
movl 4(%esp), %eax
clflush (%eax)
ret

42
MdePkg/Library/BaseLib/Ia32/FlushCacheLine.asm Normal file
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@ -0,0 +1,42 @@
;------------------------------------------------------------------------------
;
; Copyright (c) 2006, Intel Corporation
; All rights reserved. This program and the accompanying materials
; are licensed and made available under the terms and conditions of the BSD License
; which accompanies this distribution. The full text of the license may be found at
; http://opensource.org/licenses/bsd-license.php
;
; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
;
; Module Name:
;
; FlushCacheLine.Asm
;
; Abstract:
;
; AsmFlushCacheLine function
;
; Notes:
;
;------------------------------------------------------------------------------
.586P
.model flat,C
.xmm
.code
;------------------------------------------------------------------------------
; VOID *
; EFIAPI
; AsmFlushCacheLine (
; IN VOID *LinearAddress
; );
;------------------------------------------------------------------------------
AsmFlushCacheLine PROC
mov eax, [esp + 4]
clflush [eax]
ret
AsmFlushCacheLine ENDP
END

31
MdePkg/Library/BaseLib/Ia32/FlushCacheLine.c Normal file
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@ -0,0 +1,31 @@
/** @file
AsmFlushCacheLine function
Copyright (c) 2006 - 2007, Intel Corporation<BR>
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
//
// Include common header file for this module.
//
#include "CommonHeader.h"
VOID *
EFIAPI
AsmFlushCacheLine (
IN VOID *LinearAddress
)
{
_asm {
mov eax, LinearAddress
clflush [eax]
}
}

41
MdePkg/Library/BaseLib/Ia32/FxRestore.S Normal file
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@ -0,0 +1,41 @@
//
// Include common header file for this module.
//
#include "CommonHeader.h"
#------------------------------------------------------------------------------
#
# Copyright (c) 2006, Intel Corporation
# All rights reserved. This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
# Module Name:
#
# FxRestore.Asm
#
# Abstract:
#
# InternalX86FxRestore function
#
# Notes:
#
#------------------------------------------------------------------------------
.globl ASM_PFX(InternalX86FxRestore)
#------------------------------------------------------------------------------
# VOID
# EFIAPI
# InternalX86FxRestore (
# IN CONST IA32_FX_BUFFER *Buffer
# );
#------------------------------------------------------------------------------
ASM_PFX(InternalX86FxRestore):
movl 4(%esp), %eax
fxrstor (%eax)
ret

42
MdePkg/Library/BaseLib/Ia32/FxRestore.asm Normal file
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@ -0,0 +1,42 @@
;------------------------------------------------------------------------------
;
; Copyright (c) 2006, Intel Corporation
; All rights reserved. This program and the accompanying materials
; are licensed and made available under the terms and conditions of the BSD License
; which accompanies this distribution. The full text of the license may be found at
; http://opensource.org/licenses/bsd-license.php
;
; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
;
; Module Name:
;
; FxRestore.Asm
;
; Abstract:
;
; AsmFxRestore function
;
; Notes:
;
;------------------------------------------------------------------------------
.586
.model flat,C
.xmm
.code
;------------------------------------------------------------------------------
; VOID
; EFIAPI
; InternalX86FxRestore (
; IN CONST IA32_FX_BUFFER *Buffer
; );
;------------------------------------------------------------------------------
InternalX86FxRestore PROC
mov eax, [esp + 4] ; Buffer must be 16-byte aligned
fxrstor [eax]
ret
InternalX86FxRestore ENDP
END

31
MdePkg/Library/BaseLib/Ia32/FxRestore.c Normal file
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@ -0,0 +1,31 @@
/** @file
AsmFxRestore function
Copyright (c) 2006 - 2007, Intel Corporation<BR>
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
//
// Include common header file for this module.
//
#include "CommonHeader.h"
VOID
EFIAPI
InternalX86FxRestore (
IN CONST IA32_FX_BUFFER *Buffer
)
{
_asm {
mov eax, Buffer
fxrstor [eax]
}
}

41
MdePkg/Library/BaseLib/Ia32/FxSave.S Normal file
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@ -0,0 +1,41 @@
//
// Include common header file for this module.
//
#include "CommonHeader.h"
#------------------------------------------------------------------------------
#
# Copyright (c) 2006, Intel Corporation
# All rights reserved. This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
# Module Name:
#
# FxSave.Asm
#
# Abstract:
#
# InternalX86FxSave function
#
# Notes:
#
#------------------------------------------------------------------------------
.globl ASM_PFX(InternalX86FxSave)
#------------------------------------------------------------------------------
# VOID
# EFIAPI
# InternalX86FxSave (
# OUT IA32_FX_BUFFER *Buffer
# );
#------------------------------------------------------------------------------
ASM_PFX(InternalX86FxSave):
movl 4(%esp), %eax
fxsave (%eax)
ret

42
MdePkg/Library/BaseLib/Ia32/FxSave.asm Normal file
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@ -0,0 +1,42 @@
;------------------------------------------------------------------------------
;
; Copyright (c) 2006, Intel Corporation
; All rights reserved. This program and the accompanying materials
; are licensed and made available under the terms and conditions of the BSD License
; which accompanies this distribution. The full text of the license may be found at
; http://opensource.org/licenses/bsd-license.php
;
; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
;
; Module Name:
;
; FxSave.Asm
;
; Abstract:
;
; AsmFxSave function
;
; Notes:
;
;------------------------------------------------------------------------------
.586
.model flat,C
.xmm
.code
;------------------------------------------------------------------------------
; VOID
; EFIAPI
; InternalX86FxSave (
; OUT IA32_FX_BUFFER *Buffer
; );
;------------------------------------------------------------------------------
InternalX86FxSave PROC
mov eax, [esp + 4] ; Buffer must be 16-byte aligned
fxsave [eax]
ret
InternalX86FxSave ENDP
END

31
MdePkg/Library/BaseLib/Ia32/FxSave.c Normal file
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@ -0,0 +1,31 @@
/** @file
AsmFxSave function
Copyright (c) 2006 - 2007, Intel Corporation<BR>
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
//
// Include common header file for this module.
//
#include "CommonHeader.h"
VOID
EFIAPI
InternalX86FxSave (
OUT IA32_FX_BUFFER *Buffer
)
{
_asm {
mov eax, Buffer
fxsave [eax]
}
}

46
MdePkg/Library/BaseLib/Ia32/InterlockedCompareExchange32.S Normal file
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@ -0,0 +1,46 @@
//
// Include common header file for this module.
//
#include "CommonHeader.h"
#------------------------------------------------------------------------------
#
# Copyright (c) 2006, Intel Corporation
# All rights reserved. This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
# Module Name:
#
# InterlockedCompareExchange32.Asm
#
# Abstract:
#
# InternalSyncCompareExchange32 function
#
# Notes:
#
#------------------------------------------------------------------------------
.globl ASM_PFX(InternalSyncCompareExchange32)
#------------------------------------------------------------------------------
# UINT32
# EFIAPI
# InternalSyncCompareExchange32 (
# IN UINT32 *Value,
# IN UINT32 CompareValue,
# IN UINT32 ExchangeValue
# );
#------------------------------------------------------------------------------
ASM_PFX(InternalSyncCompareExchange32):
movl 4(%esp), %ecx
movl 8(%esp), %eax
movl 12(%esp), %edx
lock
cmpxchgl %edx, (%ecx)
ret

45
MdePkg/Library/BaseLib/Ia32/InterlockedCompareExchange32.asm Normal file
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@ -0,0 +1,45 @@
;------------------------------------------------------------------------------
;
; Copyright (c) 2006, Intel Corporation
; All rights reserved. This program and the accompanying materials
; are licensed and made available under the terms and conditions of the BSD License
; which accompanies this distribution. The full text of the license may be found at
; http://opensource.org/licenses/bsd-license.php
;
; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
;
; Module Name:
;
; InterlockedCompareExchange32.Asm
;
; Abstract:
;
; InterlockedCompareExchange32 function
;
; Notes:
;
;------------------------------------------------------------------------------
.486
.model flat,C
.code
;------------------------------------------------------------------------------
; UINT32
; EFIAPI
; InternalSyncCompareExchange32 (
; IN UINT32 *Value,
; IN UINT32 CompareValue,
; IN UINT32 ExchangeValue
; );
;------------------------------------------------------------------------------
InternalSyncCompareExchange32 PROC
mov ecx, [esp + 4]
mov eax, [esp + 8]
mov edx, [esp + 12]
lock cmpxchg [ecx], edx
ret
InternalSyncCompareExchange32 ENDP
END

35
MdePkg/Library/BaseLib/Ia32/InterlockedCompareExchange32.c Normal file
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@ -0,0 +1,35 @@
/** @file
InterlockedCompareExchange32 function
Copyright (c) 2006 - 2007, Intel Corporation<BR>
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
//
// Include common header file for this module.
//
#include "CommonHeader.h"
UINT32
EFIAPI
InternalSyncCompareExchange32 (
IN UINT32 *Value,
IN UINT32 CompareValue,
IN UINT32 ExchangeValue
)
{
_asm {
mov ecx, Value
mov eax, CompareValue
mov edx, ExchangeValue
lock cmpxchg [ecx], edx
}
}

52
MdePkg/Library/BaseLib/Ia32/InterlockedCompareExchange64.S Normal file
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@ -0,0 +1,52 @@
//
// Include common header file for this module.
//
#include "CommonHeader.h"
#------------------------------------------------------------------------------
#
# Copyright (c) 2006, Intel Corporation
# All rights reserved. This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
# Module Name:
#
# InterlockedCompareExchange64.Asm
#
# Abstract:
#
# InternalSyncCompareExchange64 function
#
# Notes:
#
#------------------------------------------------------------------------------
.globl ASM_PFX(InternalSyncCompareExchange64)
#------------------------------------------------------------------------------
# UINT64
# EFIAPI
# InternalSyncCompareExchange64 (
# IN UINT64 *Value,
# IN UINT64 CompareValue,
# IN UINT64 ExchangeValue
# );
#------------------------------------------------------------------------------
ASM_PFX(InternalSyncCompareExchange64):
push %esi
push %ebx
movl 12(%esp), %esi
movl 16(%esp), %eax
movl 20(%esp), %edx
movl 24(%esp), %ebx
movl 28(%esp), %ecx
lock
cmpxchg8b (%esi)
pop %ebx
pop %esi
ret

47
MdePkg/Library/BaseLib/Ia32/InterlockedCompareExchange64.asm Normal file
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@ -0,0 +1,47 @@
;------------------------------------------------------------------------------
;
; Copyright (c) 2006, Intel Corporation
; All rights reserved. This program and the accompanying materials
; are licensed and made available under the terms and conditions of the BSD License
; which accompanies this distribution. The full text of the license may be found at
; http://opensource.org/licenses/bsd-license.php
;
; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
;
; Module Name:
;
; InterlockedCompareExchange64.Asm
;
; Abstract:
;
; InterlockedCompareExchange64 function
;
; Notes:
;
;------------------------------------------------------------------------------
.586P
.model flat,C
.code
;------------------------------------------------------------------------------
; UINT64
; EFIAPI
; InternalSyncCompareExchange64 (
; IN UINT64 *Value,
; IN UINT64 CompareValue,
; IN UINT64 ExchangeValue
; );
;------------------------------------------------------------------------------
InternalSyncCompareExchange64 PROC USES esi ebx
mov esi, [esp + 12]
mov eax, [esp + 16]
mov edx, [esp + 20]
mov ebx, [esp + 24]
mov ecx, [esp + 28]
lock cmpxchg8b qword ptr [esi]
ret
InternalSyncCompareExchange64 ENDP
END

36
MdePkg/Library/BaseLib/Ia32/InterlockedCompareExchange64.c Normal file
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@ -0,0 +1,36 @@
/** @file
InterlockedCompareExchange64 function
Copyright (c) 2006 - 2007, Intel Corporation<BR>
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
//
// Include common header file for this module.
//
#include "CommonHeader.h"
UINT64
EFIAPI
InternalSyncCompareExchange64 (
IN UINT64 *Value,
IN UINT64 CompareValue,
IN UINT64 ExchangeValue
)
{
_asm {
mov esi, Value
mov eax, dword ptr [CompareValue + 0]
mov edx, dword ptr [CompareValue + 4]
mov ebx, dword ptr [ExchangeValue + 0]
mov ecx, dword ptr [ExchangeValue + 4]
lock cmpxchg8b qword ptr [esi]
}
}

43
MdePkg/Library/BaseLib/Ia32/InterlockedDecrement.S Normal file
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@ -0,0 +1,43 @@
//
// Include common header file for this module.
//
#include "CommonHeader.h"
#------------------------------------------------------------------------------
#
# Copyright (c) 2006, Intel Corporation
# All rights reserved. This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
# Module Name:
#
# InterlockedDecrement.Asm
#
# Abstract:
#
# InternalSyncDecrement function
#
# Notes:
#
#------------------------------------------------------------------------------
.globl ASM_PFX(InternalSyncDecrement)
#------------------------------------------------------------------------------
# UINT32
# EFIAPI
# InternalSyncDecrement (
# IN UINT32 *Value
# );
#------------------------------------------------------------------------------
ASM_PFX(InternalSyncDecrement):
movl 4(%esp), %eax
lock
decl (%eax)
movl (%eax), %eax
ret

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