sravan/system76-edk2
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

UefiCpuPkg: Update PiSmmCpuDxeSmm pass XCODE5 tool chain

Browse Source 
https://bugzilla.tianocore.org/show_bug.cgi?id=849

In V2, use "mov rax, strict qword 0" to replace the hard code db.

1. Use lea instruction to get the address instead of mov instruction.
2. Use the dummy address as jmp destination, and add the logic to fix up
the address to the absolute address at boot time.
3. On MpFuncs.nasm, use ExchangeInfo to record InitializeFloatingPointUnits.
This way is same to MpInitLib.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Liming Gao <liming.gao@intel.com>
Cc: Andrew Fish <afish@apple.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
This commit is contained in:
Liming Gao
2018-01-11 17:05:15 +08:00
parent 1c7a65eba7
commit e21e355e2c
9 changed files with 79 additions and 24 deletions
Download Patch File Download Diff File Expand all files Collapse all files

30
UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm
View File

@@ -1,5 +1,5 @@
;------------------------------------------------------------------------------ ;
; Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
; Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
; This program and the accompanying materials
; are licensed and made available under the terms and conditions of the BSD License
; which accompanies this distribution. The full text of the license may be found at
@@ -158,7 +158,8 @@ Base:
mov cr0, rbx
retf
@LongMode: ; long mode (64-bit code) starts here
mov rax, ASM_PFX(gSmiHandlerIdtr)
mov rax, strict qword 0 ; mov rax, ASM_PFX(gSmiHandlerIdtr)
SmiHandlerIdtrAbsAddr:
lidt [rax]
lea ebx, [rdi + DSC_OFFSET]
mov ax, [rbx + DSC_DS]
@@ -169,7 +170,9 @@ Base:
mov gs, eax
mov ax, [rbx + DSC_SS]
mov ss, eax
; jmp _SmiHandler ; instruction is not needed
mov rax, strict qword 0 ; mov rax, _SmiHandler
_SmiHandlerAbsAddr:
jmp rax
_SmiHandler:
mov rbx, [rsp + 0x8] ; rcx <- CpuIndex
@@ -184,16 +187,13 @@ _SmiHandler:
add rsp, -0x20
mov rcx, rbx
mov rax, ASM_PFX(CpuSmmDebugEntry)
call rax
call ASM_PFX(CpuSmmDebugEntry)
mov rcx, rbx
mov rax, ASM_PFX(SmiRendezvous) ; rax <- absolute addr of SmiRedezvous
call rax
call ASM_PFX(SmiRendezvous)
mov rcx, rbx
mov rax, ASM_PFX(CpuSmmDebugExit)
call rax
call ASM_PFX(CpuSmmDebugExit)
add rsp, 0x20
@@ -205,7 +205,7 @@ _SmiHandler:
add rsp, 0x200
mov rax, ASM_PFX(mXdSupported)
lea rax, [ASM_PFX(mXdSupported)]
mov al, [rax]
cmp al, 0
jz .1
@@ -222,3 +222,13 @@ _SmiHandler:
ASM_PFX(gcSmiHandlerSize) DW $ - _SmiEntryPoint
global ASM_PFX(PiSmmCpuSmiEntryFixupAddress)
ASM_PFX(PiSmmCpuSmiEntryFixupAddress):
lea rax, [ASM_PFX(gSmiHandlerIdtr)]
lea rcx, [SmiHandlerIdtrAbsAddr]
mov qword [rcx - 8], rax
lea rax, [_SmiHandler]
lea rcx, [_SmiHandlerAbsAddr]
mov qword [rcx - 8], rax
ret