ArmPlatformPkg: Introduced 'ArmPlatformSecLib'
The function only used in Secure Firmware used to be mixed with the Non-Secure/Normal functions in ArmPlatformLib. When the Secure Firmware was not required for some platforms (eg: BeagleBoard), these functions were empty functions. This new interface has been created to clean the ArmPlatformLib interface between the SEC and PEI phases. Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13260 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
@@ -1,57 +1,53 @@
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#/* @file
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# Copyright (c) 2011, ARM Limited. All rights reserved.
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#
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||||
# This program and the accompanying materials
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# are licensed and made available under the terms and conditions of the BSD License
|
||||
# which accompanies this distribution. The full text of the license may be found at
|
||||
# http://opensource.org/licenses/bsd-license.php
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||||
#
|
||||
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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#
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#*/
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[Defines]
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INF_VERSION = 0x00010005
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BASE_NAME = CTA9x4ArmVExpressLib
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FILE_GUID = b16c63a0-f417-11df-b3af-0002a5d5c51b
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MODULE_TYPE = BASE
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VERSION_STRING = 1.0
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LIBRARY_CLASS = ArmPlatformLib
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[Packages]
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MdePkg/MdePkg.dec
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MdeModulePkg/MdeModulePkg.dec
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EmbeddedPkg/EmbeddedPkg.dec
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ArmPkg/ArmPkg.dec
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ArmPlatformPkg/ArmPlatformPkg.dec
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[LibraryClasses]
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ArmLib
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ArmTrustZoneLib
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ArmPlatformSysConfigLib
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ArmPlatformSecExtraActionLib
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IoLib
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L2X0CacheLib
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PL301AxiLib
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PL341DmcLib
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PL35xSmcLib
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SerialPortLib
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[Sources.common]
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CTA9x4Sec.c
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CTA9x4.c
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CTA9x4Boot.asm | RVCT
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CTA9x4Boot.S | GCC
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[FeaturePcd]
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gEmbeddedTokenSpaceGuid.PcdCacheEnable
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gArmPlatformTokenSpaceGuid.PcdNorFlashRemapping
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[FixedPcd]
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gArmTokenSpaceGuid.PcdTrustzoneSupport
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gArmTokenSpaceGuid.PcdL2x0ControllerBase
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gArmTokenSpaceGuid.PcdArmPrimaryCoreMask
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gArmTokenSpaceGuid.PcdArmPrimaryCore
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#/* @file
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# Copyright (c) 2011-2012, ARM Limited. All rights reserved.
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#
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# This program and the accompanying materials
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# are licensed and made available under the terms and conditions of the BSD License
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||||
# which accompanies this distribution. The full text of the license may be found at
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# http://opensource.org/licenses/bsd-license.php
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#
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# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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#
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#*/
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[Defines]
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INF_VERSION = 0x00010005
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BASE_NAME = CTA9x4ArmVExpressLibSec
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FILE_GUID = b16c63a0-f417-11df-b3af-0002a5d5c51b
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MODULE_TYPE = BASE
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VERSION_STRING = 1.0
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LIBRARY_CLASS = ArmPlatformLib
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[Packages]
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MdePkg/MdePkg.dec
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MdeModulePkg/MdeModulePkg.dec
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EmbeddedPkg/EmbeddedPkg.dec
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ArmPkg/ArmPkg.dec
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ArmPlatformPkg/ArmPlatformPkg.dec
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[LibraryClasses]
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IoLib
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ArmLib
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ArmTrustZoneLib
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PL341DmcLib
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PL301AxiLib
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L2X0CacheLib
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SerialPortLib
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[Sources.common]
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CTA9x4.c
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[FeaturePcd]
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gEmbeddedTokenSpaceGuid.PcdCacheEnable
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gArmPlatformTokenSpaceGuid.PcdNorFlashRemapping
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[FixedPcd]
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gArmTokenSpaceGuid.PcdTrustzoneSupport
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gArmTokenSpaceGuid.PcdSystemMemoryBase
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gArmTokenSpaceGuid.PcdSystemMemorySize
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gArmTokenSpaceGuid.PcdL2x0ControllerBase
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gArmTokenSpaceGuid.PcdArmPrimaryCoreMask
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gArmTokenSpaceGuid.PcdArmPrimaryCore
|
@@ -0,0 +1,50 @@
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#/* @file
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# Copyright (c) 2011-2012, ARM Limited. All rights reserved.
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#
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# This program and the accompanying materials
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# are licensed and made available under the terms and conditions of the BSD License
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# which accompanies this distribution. The full text of the license may be found at
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# http://opensource.org/licenses/bsd-license.php
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#
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# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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#
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#*/
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[Defines]
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INF_VERSION = 0x00010005
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BASE_NAME = RTSMArmVExpressLibSec
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FILE_GUID = a79eed97-4b98-4974-9690-37b32d6a5b56
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MODULE_TYPE = BASE
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VERSION_STRING = 1.0
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LIBRARY_CLASS = ArmPlatformLib
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[Packages]
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MdePkg/MdePkg.dec
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MdeModulePkg/MdeModulePkg.dec
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EmbeddedPkg/EmbeddedPkg.dec
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ArmPkg/ArmPkg.dec
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ArmPlatformPkg/ArmPlatformPkg.dec
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[LibraryClasses]
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IoLib
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ArmLib
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SerialPortLib
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[Sources.common]
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RTSM.c
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RTSMHelper.asm | RVCT
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RTSMHelper.S | GCC
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[FeaturePcd]
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gEmbeddedTokenSpaceGuid.PcdCacheEnable
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gArmPlatformTokenSpaceGuid.PcdNorFlashRemapping
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gArmPlatformTokenSpaceGuid.PcdStandalone
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[FixedPcd]
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gArmTokenSpaceGuid.PcdSystemMemoryBase
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gArmTokenSpaceGuid.PcdSystemMemorySize
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gArmTokenSpaceGuid.PcdFvBaseAddress
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gArmTokenSpaceGuid.PcdArmPrimaryCoreMask
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gArmTokenSpaceGuid.PcdArmPrimaryCore
|
@@ -0,0 +1,59 @@
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#/* @file
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# Copyright (c) 2011-2012, ARM Limited. All rights reserved.
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#
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||||
# This program and the accompanying materials
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# are licensed and made available under the terms and conditions of the BSD License
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# which accompanies this distribution. The full text of the license may be found at
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# http://opensource.org/licenses/bsd-license.php
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#
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# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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#
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#*/
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[Defines]
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INF_VERSION = 0x00010005
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BASE_NAME = CTA9x4ArmVExpressLib
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FILE_GUID = aac05341-56df-4a77-b20f-f5daa456bd90
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MODULE_TYPE = BASE
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VERSION_STRING = 1.0
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LIBRARY_CLASS = ArmPlatformSecLib
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[Packages]
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MdePkg/MdePkg.dec
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MdeModulePkg/MdeModulePkg.dec
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EmbeddedPkg/EmbeddedPkg.dec
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ArmPkg/ArmPkg.dec
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ArmPlatformPkg/ArmPlatformPkg.dec
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[LibraryClasses]
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ArmLib
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ArmTrustZoneLib
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ArmPlatformLib
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ArmPlatformSysConfigLib
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ArmPlatformSecExtraActionLib
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IoLib
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L2X0CacheLib
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PL301AxiLib
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PL341DmcLib
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PL35xSmcLib
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SerialPortLib
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[Sources.common]
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CTA9x4Sec.c
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CTA9x4Boot.asm | RVCT
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CTA9x4Boot.S | GCC
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[FeaturePcd]
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||||
gEmbeddedTokenSpaceGuid.PcdCacheEnable
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gArmPlatformTokenSpaceGuid.PcdNorFlashRemapping
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gArmPlatformTokenSpaceGuid.PcdStandalone
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gArmPlatformTokenSpaceGuid.PcdSystemMemoryInitializeInSec
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[FixedPcd]
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gArmTokenSpaceGuid.PcdTrustzoneSupport
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gArmTokenSpaceGuid.PcdL2x0ControllerBase
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gArmTokenSpaceGuid.PcdArmPrimaryCoreMask
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gArmTokenSpaceGuid.PcdArmPrimaryCore
|
@@ -1,5 +1,5 @@
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//
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// Copyright (c) 2011, ARM Limited. All rights reserved.
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// Copyright (c) 2011-2012, ARM Limited. All rights reserved.
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//
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// This program and the accompanying materials
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// are licensed and made available under the terms and conditions of the BSD License
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@@ -22,7 +22,7 @@
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.align 3
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GCC_ASM_EXPORT(ArmPlatformSecBootAction)
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GCC_ASM_EXPORT(ArmPlatformInitializeBootMemory)
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GCC_ASM_EXPORT(ArmPlatformSecBootMemoryInit)
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GCC_ASM_IMPORT(PL35xSmcInitialize)
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//
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@@ -82,7 +82,7 @@ ASM_PFX(ArmPlatformSecBootAction):
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pointer is not used (probably required to use assembly language)
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**/
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ASM_PFX(ArmPlatformInitializeBootMemory):
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ASM_PFX(ArmPlatformSecBootMemoryInit):
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mov r5, lr
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//
|
@@ -1,5 +1,5 @@
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//
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// Copyright (c) 2011, ARM Limited. All rights reserved.
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// Copyright (c) 2011-2012, ARM Limited. All rights reserved.
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//
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// This program and the accompanying materials
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// are licensed and made available under the terms and conditions of the BSD License
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@@ -21,7 +21,7 @@
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INCLUDE AsmMacroIoLib.inc
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EXPORT ArmPlatformSecBootAction
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EXPORT ArmPlatformInitializeBootMemory
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EXPORT ArmPlatformSecBootMemoryInit
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IMPORT PL35xSmcInitialize
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PRESERVE8
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@@ -84,7 +84,7 @@ ArmPlatformSecBootAction
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pointer is not used (probably required to use assembly language)
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**/
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ArmPlatformInitializeBootMemory
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ArmPlatformSecBootMemoryInit
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mov r5, lr
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//
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@@ -31,7 +31,7 @@
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**/
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VOID
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ArmPlatformTrustzoneInit (
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ArmPlatformSecTrustzoneInit (
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IN UINTN MpId
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)
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{
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@@ -114,10 +114,16 @@ ArmPlatformTrustzoneInit (
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For example, some L2x0 requires to be initialized in Secure World
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**/
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VOID
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RETURN_STATUS
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ArmPlatformSecInitialize (
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VOID
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) {
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IN UINTN MpId
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)
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{
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// If it is not the primary core then there is nothing to do
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if (!IS_PRIMARY_CORE(MpId)) {
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return RETURN_SUCCESS;
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}
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// The L2x0 controller must be intialize in Secure World
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L2x0CacheInit(PcdGet32(PcdL2x0ControllerBase),
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PL310_TAG_LATENCIES(L2x0_LATENCY_8_CYCLES,L2x0_LATENCY_8_CYCLES,L2x0_LATENCY_8_CYCLES),
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@@ -127,4 +133,16 @@ ArmPlatformSecInitialize (
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// Initialize the System Configuration
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ArmPlatformSysConfigInitialize ();
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// If we skip the PEI Core we could want to initialize the DRAM in the SEC phase.
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// If we are in standalone, we need the initialization to copy the UEFI firmware into DRAM
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if ((FeaturePcdGet (PcdSystemMemoryInitializeInSec)) || (FeaturePcdGet (PcdStandalone) == FALSE)) {
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// If it is not a standalone build ensure the PcdSystemMemoryInitializeInSec has been set
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ASSERT(FeaturePcdGet (PcdSystemMemoryInitializeInSec) == TRUE);
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// Initialize system memory (DRAM)
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ArmPlatformInitializeSystemMemory ();
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}
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return RETURN_SUCCESS;
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}
|
@@ -1,5 +1,5 @@
|
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#/* @file
|
||||
# Copyright (c) 2011, ARM Limited. All rights reserved.
|
||||
# Copyright (c) 2011-2012, ARM Limited. All rights reserved.
|
||||
#
|
||||
# This program and the accompanying materials
|
||||
# are licensed and made available under the terms and conditions of the BSD License
|
||||
@@ -13,11 +13,11 @@
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[Defines]
|
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INF_VERSION = 0x00010005
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BASE_NAME = RTSMArmVExpressLib
|
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FILE_GUID = 6352e3a0-ed14-4613-bf90-d316014dd142
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BASE_NAME = RTSMArmVExpressSecLib
|
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FILE_GUID = 1fdaabb0-ab7d-480c-91ff-428dc1546f3a
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MODULE_TYPE = BASE
|
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VERSION_STRING = 1.0
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LIBRARY_CLASS = ArmPlatformLib
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LIBRARY_CLASS = ArmPlatformSecLib
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[Packages]
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MdePkg/MdePkg.dec
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@@ -33,14 +33,11 @@
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[Sources.common]
|
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RTSMSec.c
|
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RTSM.c
|
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RTSMBoot.asm | RVCT
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RTSMBoot.S | GCC
|
||||
RTSMHelper.asm | RVCT
|
||||
RTSMHelper.S | GCC
|
||||
|
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[Protocols]
|
||||
|
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[FeaturePcd]
|
||||
gEmbeddedTokenSpaceGuid.PcdCacheEnable
|
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gArmPlatformTokenSpaceGuid.PcdNorFlashRemapping
|
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@@ -48,3 +45,6 @@
|
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|
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[FixedPcd]
|
||||
gArmTokenSpaceGuid.PcdFvBaseAddress
|
||||
|
||||
gArmTokenSpaceGuid.PcdArmPrimaryCoreMask
|
||||
gArmTokenSpaceGuid.PcdArmPrimaryCore
|
@@ -1,5 +1,5 @@
|
||||
//
|
||||
// Copyright (c) 2011, ARM Limited. All rights reserved.
|
||||
// Copyright (c) 2011-2012, ARM Limited. All rights reserved.
|
||||
//
|
||||
// This program and the accompanying materials
|
||||
// are licensed and made available under the terms and conditions of the BSD License
|
||||
@@ -21,7 +21,7 @@
|
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.align 3
|
||||
|
||||
GCC_ASM_EXPORT(ArmPlatformSecBootAction)
|
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GCC_ASM_EXPORT(ArmPlatformInitializeBootMemory)
|
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GCC_ASM_EXPORT(ArmPlatformSecBootMemoryInit)
|
||||
|
||||
/**
|
||||
Call at the beginning of the platform boot up
|
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@@ -45,6 +45,6 @@ ASM_PFX(ArmPlatformSecBootAction):
|
||||
pointer is not used (probably required to use assembly language)
|
||||
|
||||
**/
|
||||
ASM_PFX(ArmPlatformInitializeBootMemory):
|
||||
ASM_PFX(ArmPlatformSecBootMemoryInit):
|
||||
// The SMC does not need to be initialized for RTSM
|
||||
bx lr
|
@@ -20,7 +20,7 @@
|
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INCLUDE AsmMacroIoLib.inc
|
||||
|
||||
EXPORT ArmPlatformSecBootAction
|
||||
EXPORT ArmPlatformInitializeBootMemory
|
||||
EXPORT ArmPlatformSecBootMemoryInit
|
||||
|
||||
PRESERVE8
|
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AREA RTSMVExpressBootMode, CODE, READONLY
|
||||
@@ -47,6 +47,6 @@ ArmPlatformSecBootAction
|
||||
pointer is not used (probably required to use assembly language)
|
||||
|
||||
**/
|
||||
ArmPlatformInitializeBootMemory
|
||||
ArmPlatformSecBootMemoryInit
|
||||
// The SMC does not need to be initialized for RTSM
|
||||
bx lr
|
@@ -0,0 +1,71 @@
|
||||
#
|
||||
# Copyright (c) 2011-2012, ARM Limited. All rights reserved.
|
||||
#
|
||||
# This program and the accompanying materials
|
||||
# are licensed and made available under the terms and conditions of the BSD License
|
||||
# which accompanies this distribution. The full text of the license may be found at
|
||||
# http:#opensource.org/licenses/bsd-license.php
|
||||
#
|
||||
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
#
|
||||
#
|
||||
|
||||
#include <AsmMacroIoLib.h>
|
||||
#include <Base.h>
|
||||
#include <Library/PcdLib.h>
|
||||
#include <AutoGen.h>
|
||||
#.include AsmMacroIoLib.inc
|
||||
|
||||
#include <Chipset/ArmCortexA9.h>
|
||||
|
||||
.text
|
||||
.align 2
|
||||
|
||||
GCC_ASM_EXPORT(ArmGetCpuCountPerCluster)
|
||||
|
||||
# IN None
|
||||
# OUT r0 = SCU Base Address
|
||||
ASM_PFX(ArmGetScuBaseAddress):
|
||||
# Read Configuration Base Address Register. ArmCBar cannot be called to get
|
||||
# the Configuration BAR as a stack is not necessary setup. The SCU is at the
|
||||
# offset 0x0000 from the Private Memory Region.
|
||||
mrc p15, 4, r0, c15, c0, 0
|
||||
bx lr
|
||||
|
||||
# IN None
|
||||
# OUT r0 = number of cores present in the system
|
||||
ASM_PFX(ArmGetCpuCountPerCluster):
|
||||
stmfd SP!, {r1-r2}
|
||||
|
||||
# Read CP15 MIDR
|
||||
mrc p15, 0, r1, c0, c0, 0
|
||||
|
||||
# Check if the CPU is A15
|
||||
mov r1, r1, LSR #4
|
||||
LoadConstantToReg (ARM_CPU_TYPE_MASK, r0)
|
||||
and r1, r1, r0
|
||||
|
||||
LoadConstantToReg (ARM_CPU_TYPE_A15, r0)
|
||||
cmp r1, r0
|
||||
beq _Read_cp15_reg
|
||||
|
||||
_CPU_is_not_A15:
|
||||
mov r2, lr @ Save link register
|
||||
bl ArmGetScuBaseAddress @ Read SCU Base Address
|
||||
mov lr, r2 @ Restore link register val
|
||||
ldr r0, [r0, #A9_SCU_CONFIG_OFFSET] @ Read SCU Config reg to get CPU count
|
||||
b _Return
|
||||
|
||||
_Read_cp15_reg:
|
||||
mrc p15, 1, r0, c9, c0, 2 @ Read C9 register of CP15 to get CPU count
|
||||
lsr r0, #24
|
||||
|
||||
_Return:
|
||||
and r0, r0, #3
|
||||
# Add '1' to the number of CPU on the Cluster
|
||||
add r0, r0, #1
|
||||
ldmfd SP!, {r1-r2}
|
||||
bx lr
|
||||
|
||||
ASM_FUNCTION_REMOVE_IF_UNREFERENCED
|
@@ -0,0 +1,73 @@
|
||||
//
|
||||
// Copyright (c) 2011-2012, ARM Limited. All rights reserved.
|
||||
//
|
||||
// This program and the accompanying materials
|
||||
// are licensed and made available under the terms and conditions of the BSD License
|
||||
// which accompanies this distribution. The full text of the license may be found at
|
||||
// http://opensource.org/licenses/bsd-license.php
|
||||
//
|
||||
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
//
|
||||
//
|
||||
|
||||
#include <AsmMacroIoLib.h>
|
||||
#include <Base.h>
|
||||
#include <Library/PcdLib.h>
|
||||
|
||||
#include <Chipset/ArmCortexA9.h>
|
||||
|
||||
#include <AutoGen.h>
|
||||
|
||||
INCLUDE AsmMacroIoLib.inc
|
||||
|
||||
EXPORT ArmGetCpuCountPerCluster
|
||||
|
||||
AREA RTSMHelper, CODE, READONLY
|
||||
|
||||
// IN None
|
||||
// OUT r0 = SCU Base Address
|
||||
ArmGetScuBaseAddress
|
||||
// Read Configuration Base Address Register. ArmCBar cannot be called to get
|
||||
// the Configuration BAR as a stack is not necessary setup. The SCU is at the
|
||||
// offset 0x0000 from the Private Memory Region.
|
||||
mrc p15, 4, r0, c15, c0, 0
|
||||
bx lr
|
||||
|
||||
// IN None
|
||||
// OUT r0 = number of cores present in the system
|
||||
ArmGetCpuCountPerCluster
|
||||
stmfd SP!, {r1-r2}
|
||||
|
||||
// Read CP15 MIDR
|
||||
mrc p15, 0, r1, c0, c0, 0
|
||||
|
||||
// Check if the CPU is A15
|
||||
mov r1, r1, LSR #4
|
||||
mov r0, #ARM_CPU_TYPE_MASK
|
||||
and r1, r1, r0
|
||||
|
||||
mov r0, #ARM_CPU_TYPE_A15
|
||||
cmp r1, r0
|
||||
beq _Read_cp15_reg
|
||||
|
||||
_CPU_is_not_A15
|
||||
mov r2, lr ; Save link register
|
||||
bl ArmGetScuBaseAddress ; Read SCU Base Address
|
||||
mov lr, r2 ; Restore link register val
|
||||
ldr r0, [r0, #A9_SCU_CONFIG_OFFSET] ; Read SCU Config reg to get CPU count
|
||||
b _Return
|
||||
|
||||
_Read_cp15_reg
|
||||
mrc p15, 1, r0, c9, c0, 2 ; Read C9 register of CP15 to get CPU count
|
||||
lsr r0, #24
|
||||
|
||||
|
||||
_Return
|
||||
and r0, r0, #3
|
||||
// Add '1' to the number of CPU on the Cluster
|
||||
add r0, r0, #1
|
||||
ldmfd SP!, {r1-r2}
|
||||
bx lr
|
||||
|
||||
END
|
@@ -30,7 +30,7 @@
|
||||
|
||||
**/
|
||||
VOID
|
||||
ArmPlatformTrustzoneInit (
|
||||
ArmPlatformSecTrustzoneInit (
|
||||
IN UINTN MpId
|
||||
)
|
||||
{
|
||||
@@ -44,11 +44,16 @@ ArmPlatformTrustzoneInit (
|
||||
For example, some L2x0 requires to be initialized in Secure World
|
||||
|
||||
**/
|
||||
VOID
|
||||
RETURN_STATUS
|
||||
ArmPlatformSecInitialize (
|
||||
VOID
|
||||
IN UINTN MpId
|
||||
)
|
||||
{
|
||||
// If it is not the primary core then there is nothing to do
|
||||
if (!IS_PRIMARY_CORE(MpId)) {
|
||||
return RETURN_SUCCESS;
|
||||
}
|
||||
|
||||
// Configure periodic timer (TIMER0) for 1MHz operation
|
||||
MmioOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, SP810_SYS_CTRL_TIMER0_TIMCLK);
|
||||
// Configure 1MHz clock
|
||||
@@ -57,6 +62,8 @@ ArmPlatformSecInitialize (
|
||||
MmioAndThenOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, ~SP810_SYS_CTRL_TIMER2_EN, SP810_SYS_CTRL_TIMER2_TIMCLK);
|
||||
// Configure SP810 to use 1MHz clock and disable
|
||||
MmioAndThenOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, ~SP810_SYS_CTRL_TIMER3_EN, SP810_SYS_CTRL_TIMER3_TIMCLK);
|
||||
|
||||
return RETURN_SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
Reference in New Issue
Block a user