1. Separated DxeSmmCpuExceptionHandlerLib.inf into 2 instance DxeCpuExceptionHandlerLib.inf and SmmCpuExceptionHandlerLib.inf.
2. Updated CPU Exception Handler Library instance according to the new CPU Exception Handler Library class definitions. 3. Updated CPU Exception Handler Library instance to handle the vector attributes defined in PI 1.2.1. Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com> Reviewed-by: Hot Tian <hot.tian@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14885 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
Jeff Fan
vanjeff
@@ -1,6 +1,6 @@
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#------------------------------------------------------------------------------
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#*
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#* Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>
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#* Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.<BR>
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#* This program and the accompanying materials
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#* are licensed and made available under the terms and conditions of the BSD License
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#* which accompanies this distribution. The full text of the license may be found at
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@@ -19,21 +19,6 @@
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#.MMX
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#.XMM
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#EXTRN ASM_PFX(mErrorCodeFlag):DWORD # Error code flags for exceptions
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#
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# point to the external interrupt vector table
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#
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ExternalVectorTablePtr:
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.byte 0, 0, 0, 0
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ASM_GLOBAL ASM_PFX(InitializeExternalVectorTablePtr)
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ASM_PFX(InitializeExternalVectorTablePtr):
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movl 4(%esp), %eax
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movl %eax, ExternalVectorTablePtr
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ret
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#------------------------------------------------------------------------------
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# VOID
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# SetCodeSelector (
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@@ -68,298 +53,5 @@ ASM_PFX(SetDataSelectors):
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movw %cx, %gs
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ret
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#---------------------------------------;
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# CommonInterruptEntry ;
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#---------------------------------------;
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# The follow algorithm is used for the common interrupt routine.
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ASM_GLOBAL ASM_PFX(CommonInterruptEntry)
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ASM_PFX(CommonInterruptEntry):
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cli
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#
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# All interrupt handlers are invoked through interrupt gates, so
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# IF flag automatically cleared at the entry point
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#
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#
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# Calculate vector number
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#
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# Get the return address of call, actually, it is the
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# address of vector number.
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#
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xchgl (%esp), %ecx
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movw (%ecx), %cx
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andl $0x0FFFF, %ecx
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cmpl $32, %ecx # Intel reserved vector for exceptions?
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jae NoErrorCode
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bt %ecx, ASM_PFX(mErrorCodeFlag)
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jc HasErrorCode
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NoErrorCode:
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#
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# Stack:
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# +---------------------+
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# + EFlags +
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# +---------------------+
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# + CS +
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# +---------------------+
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# + EIP +
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# +---------------------+
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# + ECX +
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# +---------------------+ <-- ESP
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#
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# Registers:
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# ECX - Vector Number
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#
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#
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# Put Vector Number on stack
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#
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pushl %ecx
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#
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# Put 0 (dummy) error code on stack, and restore ECX
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#
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xorl %ecx, %ecx # ECX = 0
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xchgl 4(%esp), %ecx
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jmp ErrorCodeAndVectorOnStack
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HasErrorCode:
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#
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# Stack:
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# +---------------------+
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# + EFlags +
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# +---------------------+
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# + CS +
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# +---------------------+
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# + EIP +
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# +---------------------+
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# + Error Code +
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# +---------------------+
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# + ECX +
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# +---------------------+ <-- ESP
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#
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# Registers:
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# ECX - Vector Number
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#
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#
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# Put Vector Number on stack and restore ECX
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#
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xchgl (%esp), %ecx
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ErrorCodeAndVectorOnStack:
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pushl %ebp
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movl %esp, %ebp
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#
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# Stack:
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# +---------------------+
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# + EFlags +
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# +---------------------+
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# + CS +
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# +---------------------+
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# + EIP +
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# +---------------------+
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# + Error Code +
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# +---------------------+
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# + Vector Number +
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# +---------------------+
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# + EBP +
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# +---------------------+ <-- EBP
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#
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#
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# Align stack to make sure that EFI_FX_SAVE_STATE_IA32 of EFI_SYSTEM_CONTEXT_IA32
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# is 16-byte aligned
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#
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andl $0x0fffffff0, %esp
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subl $12, %esp
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#; UINT32 Edi, Esi, Ebp, Esp, Ebx, Edx, Ecx, Eax;
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pushl %eax
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pushl %ecx
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pushl %edx
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pushl %ebx
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leal 24(%ebp), %ecx
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pushl %ecx # ESP
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pushl (%ebp) # EBP
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pushl %esi
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pushl %edi
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#; UINT32 Gs, Fs, Es, Ds, Cs, Ss;
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movl %ss, %eax
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pushl %eax
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movzwl 16(%ebp), %eax
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pushl %eax
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movl %ds, %eax
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pushl %eax
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movl %es, %eax
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pushl %eax
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movl %fs, %eax
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pushl %eax
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movl %gs, %eax
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pushl %eax
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#; UINT32 Eip;
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movl 12(%ebp), %eax
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pushl %eax
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#; UINT32 Gdtr[2], Idtr[2];
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subl $8, %esp
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sidt (%esp)
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movl 2(%esp), %eax
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xchgl (%esp), %eax
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andl $0x0FFFF, %eax
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movl %eax, 4(%esp)
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subl $8, %esp
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sgdt (%esp)
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movl 2(%esp), %eax
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xchgl (%esp), %eax
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andl $0x0FFFF, %eax
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movl %eax, 4(%esp)
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#; UINT32 Ldtr, Tr;
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xorl %eax, %eax
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str %ax
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pushl %eax
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sldt %ax
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pushl %eax
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#; UINT32 EFlags;
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movl 20(%ebp), %eax
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pushl %eax
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#; UINT32 Cr0, Cr1, Cr2, Cr3, Cr4;
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movl %cr4, %eax
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orl $0x208, %eax
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movl %eax, %cr4
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pushl %eax
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movl %cr3, %eax
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pushl %eax
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movl %cr2, %eax
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pushl %eax
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xorl %eax, %eax
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pushl %eax
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movl %cr0, %eax
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pushl %eax
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#; UINT32 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
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movl %dr7, %eax
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pushl %eax
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movl %dr6, %eax
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pushl %eax
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movl %dr3, %eax
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pushl %eax
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movl %dr2, %eax
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pushl %eax
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movl %dr1, %eax
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pushl %eax
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movl %dr0, %eax
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pushl %eax
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#; FX_SAVE_STATE_IA32 FxSaveState;
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subl $512, %esp
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movl %esp, %edi
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.byte 0x0f, 0x0ae, 0x07 #fxsave [edi]
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#; UEFI calling convention for IA32 requires that Direction flag in EFLAGs is clear
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cld
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#; UINT32 ExceptionData;
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pushl 8(%ebp)
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#; call into exception handler
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movl ExternalVectorTablePtr, %eax # get the interrupt vectors base
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orl %eax, %eax # NULL?
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jz nullExternalExceptionHandler
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mov 4(%ebp), %ecx
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movl (%eax,%ecx,4), %eax
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orl %eax, %eax # NULL?
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jz nullExternalExceptionHandler
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#; Prepare parameter and call
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movl %esp, %edx
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pushl %edx
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movl 4(%ebp), %edx
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pushl %edx
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#
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# Call External Exception Handler
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#
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call *%eax
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addl $8, %esp
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nullExternalExceptionHandler:
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cli
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#; UINT32 ExceptionData;
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addl $4, %esp
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#; FX_SAVE_STATE_IA32 FxSaveState;
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movl %esp, %esi
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.byte 0x0f, 0x0ae, 0x0e # fxrstor [esi]
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addl $512, %esp
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#; UINT32 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
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#; Skip restoration of DRx registers to support in-circuit emualators
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#; or debuggers set breakpoint in interrupt/exception context
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addl $24, %esp
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#; UINT32 Cr0, Cr1, Cr2, Cr3, Cr4;
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popl %eax
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movl %eax, %cr0
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addl $4, %esp # not for Cr1
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popl %eax
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movl %eax, %cr2
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popl %eax
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movl %eax, %cr3
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popl %eax
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movl %eax, %cr4
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#; UINT32 EFlags;
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popl 20(%ebp)
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#; UINT32 Ldtr, Tr;
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#; UINT32 Gdtr[2], Idtr[2];
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#; Best not let anyone mess with these particular registers...
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addl $24, %esp
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#; UINT32 Eip;
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popl 12(%ebp)
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#; UINT32 Gs, Fs, Es, Ds, Cs, Ss;
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#; NOTE - modified segment registers could hang the debugger... We
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#; could attempt to insulate ourselves against this possibility,
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#; but that poses risks as well.
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#;
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popl %gs
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popl %fs
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popl %es
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popl %ds
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popl 16(%ebp)
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popl %ss
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#; UINT32 Edi, Esi, Ebp, Esp, Ebx, Edx, Ecx, Eax;
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popl %edi
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popl %esi
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addl $4, %esp # not for ebp
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addl $4, %esp # not for esp
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popl %ebx
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popl %edx
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popl %ecx
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popl %eax
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movl %ebp, %esp
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popl %ebp
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addl $8, %esp
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iretl
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#END
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