1. Separated DxeSmmCpuExceptionHandlerLib.inf into 2 instance DxeCpuExceptionHandlerLib.inf and SmmCpuExceptionHandlerLib.inf.
2. Updated CPU Exception Handler Library instance according to the new CPU Exception Handler Library class definitions. 3. Updated CPU Exception Handler Library instance to handle the vector attributes defined in PI 1.2.1. Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com> Reviewed-by: Hot Tian <hot.tian@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14885 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
Jeff Fan
vanjeff
@@ -2,7 +2,7 @@
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#------------------------------------------------------------------------------
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#*
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#* Copyright (c) 2008 - 2011, Intel Corporation. All rights reserved.<BR>
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#* Copyright (c) 2008 - 2013, Intel Corporation. All rights reserved.<BR>
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#* This program and the accompanying materials
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#* are licensed and made available under the terms and conditions of the BSD License
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#* which accompanies this distribution. The full text of the license may be found at
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@@ -21,22 +21,6 @@
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#text SEGMENT
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#EXTRN ASM_PFX(mErrorCodeFlag):DWORD # Error code flags for exceptions
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#
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# point to the external interrupt vector table
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#
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ExternalVectorTablePtr:
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.byte 0, 0, 0, 0, 0, 0, 0, 0
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ASM_GLOBAL ASM_PFX(InitializeExternalVectorTablePtr)
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ASM_PFX(InitializeExternalVectorTablePtr):
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lea ExternalVectorTablePtr(%rip), %rax # save vector number
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mov %rcx, (%rax)
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ret
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#------------------------------------------------------------------------------
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# VOID
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# SetCodeSelector (
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@@ -69,275 +53,6 @@ ASM_PFX(SetDataSelectors):
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movw %cx, %gs
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ret
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#---------------------------------------;
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# CommonInterruptEntry ;
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#---------------------------------------;
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# The follow algorithm is used for the common interrupt routine.
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ASM_GLOBAL ASM_PFX(CommonInterruptEntry)
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ASM_PFX(CommonInterruptEntry):
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cli
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#
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# All interrupt handlers are invoked through interrupt gates, so
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# IF flag automatically cleared at the entry point
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#
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#
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# Calculate vector number
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#
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xchgq (%rsp), %rcx # get the return address of call, actually, it is the address of vector number.
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movzwl (%rcx), %ecx
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cmp $32, %ecx # Intel reserved vector for exceptions?
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jae NoErrorCode
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pushq %rax
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leaq ASM_PFX(mErrorCodeFlag)(%rip), %rax
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bt %ecx, (%rax)
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popq %rax
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jc CommonInterruptEntry_al_0000
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NoErrorCode:
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#
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# Push a dummy error code on the stack
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# to maintain coherent stack map
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#
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pushq (%rsp)
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movq $0, 8(%rsp)
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CommonInterruptEntry_al_0000:
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pushq %rbp
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movq %rsp, %rbp
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#
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# Stack:
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# +---------------------+ <-- 16-byte aligned ensured by processor
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# + Old SS +
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# +---------------------+
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# + Old RSP +
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# +---------------------+
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# + RFlags +
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# +---------------------+
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# + CS +
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# +---------------------+
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# + RIP +
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# +---------------------+
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# + Error Code +
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# +---------------------+
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# + RCX / Vector Number +
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# +---------------------+
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# + RBP +
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# +---------------------+ <-- RBP, 16-byte aligned
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#
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#
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# Since here the stack pointer is 16-byte aligned, so
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# EFI_FX_SAVE_STATE_X64 of EFI_SYSTEM_CONTEXT_x64
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# is 16-byte aligned
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#
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#; UINT64 Rdi, Rsi, Rbp, Rsp, Rbx, Rdx, Rcx, Rax;
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#; UINT64 R8, R9, R10, R11, R12, R13, R14, R15;
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pushq %r15
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pushq %r14
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pushq %r13
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pushq %r12
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pushq %r11
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pushq %r10
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pushq %r9
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pushq %r8
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pushq %rax
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pushq 8(%rbp) # RCX
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pushq %rdx
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pushq %rbx
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pushq 48(%rbp) # RSP
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pushq (%rbp) # RBP
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pushq %rsi
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pushq %rdi
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#; UINT64 Gs, Fs, Es, Ds, Cs, Ss; insure high 16 bits of each is zero
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movzwq 56(%rbp), %rax
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pushq %rax # for ss
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movzwq 32(%rbp), %rax
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pushq %rax # for cs
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movl %ds, %eax
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pushq %rax
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movl %es, %eax
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pushq %rax
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movl %fs, %eax
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pushq %rax
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movl %gs, %eax
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pushq %rax
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movq %rcx, 8(%rbp) # save vector number
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#; UINT64 Rip;
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pushq 24(%rbp)
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#; UINT64 Gdtr[2], Idtr[2];
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xorq %rax, %rax
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pushq %rax
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pushq %rax
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sidt (%rsp)
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xchgq 2(%rsp), %rax
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xchgq (%rsp), %rax
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xchgq 8(%rsp), %rax
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xorq %rax, %rax
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pushq %rax
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pushq %rax
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sgdt (%rsp)
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xchgq 2(%rsp), %rax
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xchgq (%rsp), %rax
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xchgq 8(%rsp), %rax
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#; UINT64 Ldtr, Tr;
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xorq %rax, %rax
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str %ax
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pushq %rax
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sldt %ax
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pushq %rax
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#; UINT64 RFlags;
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pushq 40(%rbp)
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#; UINT64 Cr0, Cr1, Cr2, Cr3, Cr4, Cr8;
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movq %cr8, %rax
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pushq %rax
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movq %cr4, %rax
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orq $0x208, %rax
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movq %rax, %cr4
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pushq %rax
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mov %cr3, %rax
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pushq %rax
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mov %cr2, %rax
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pushq %rax
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xorq %rax, %rax
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pushq %rax
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mov %cr0, %rax
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pushq %rax
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#; UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
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movq %dr7, %rax
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pushq %rax
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movq %dr6, %rax
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pushq %rax
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movq %dr3, %rax
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pushq %rax
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movq %dr2, %rax
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pushq %rax
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movq %dr1, %rax
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pushq %rax
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movq %dr0, %rax
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pushq %rax
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#; FX_SAVE_STATE_X64 FxSaveState;
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subq $512, %rsp
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movq %rsp, %rdi
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.byte 0x0f, 0x0ae, 0x07 #fxsave [rdi]
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#; UEFI calling convention for x64 requires that Direction flag in EFLAGs is clear
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cld
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#; UINT32 ExceptionData;
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pushq 16(%rbp)
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#; call into exception handler
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movq 8(%rbp), %rcx
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leaq ExternalVectorTablePtr(%rip), %rax
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movl (%eax), %eax
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movq (%rax,%rcx,8), %rax
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orq %rax, %rax # NULL?
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je nonNullValue#
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#; Prepare parameter and call
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# mov rcx, [rbp + 8]
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mov %rsp, %rdx
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#
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# Per X64 calling convention, allocate maximum parameter stack space
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# and make sure RSP is 16-byte aligned
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#
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subq $40, %rsp
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call *%rax
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addq $40, %rsp
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nonNullValue:
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cli
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#; UINT64 ExceptionData;
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addq $8, %rsp
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#; FX_SAVE_STATE_X64 FxSaveState;
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movq %rsp, %rsi
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.byte 0x0f, 0x0ae, 0x0E # fxrstor [rsi]
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addq $512, %rsp
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#; UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
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#; Skip restoration of DRx registers to support in-circuit emualators
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#; or debuggers set breakpoint in interrupt/exception context
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addq $48, %rsp
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#; UINT64 Cr0, Cr1, Cr2, Cr3, Cr4, Cr8;
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popq %rax
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movq %rax, %cr0
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addq $8, %rsp # not for Cr1
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popq %rax
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movq %rax, %cr2
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popq %rax
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movq %rax, %cr3
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popq %rax
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movq %rax, %cr4
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popq %rax
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movq %rax, %cr8
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#; UINT64 RFlags;
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popq 40(%rbp)
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#; UINT64 Ldtr, Tr;
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#; UINT64 Gdtr[2], Idtr[2];
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#; Best not let anyone mess with these particular registers...
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addq $48, %rsp
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#; UINT64 Rip;
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popq 24(%rbp)
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#; UINT64 Gs, Fs, Es, Ds, Cs, Ss;
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popq %rax
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# mov %rax, %gs ; not for gs
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popq %rax
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# mov %rax, %fs ; not for fs
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# (X64 will not use fs and gs, so we do not restore it)
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popq %rax
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movl %eax, %es
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popq %rax
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movl %eax, %ds
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popq 32(%rbp) # for cs
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popq 56(%rbp) # for ss
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#; UINT64 Rdi, Rsi, Rbp, Rsp, Rbx, Rdx, Rcx, Rax;
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#; UINT64 R8, R9, R10, R11, R12, R13, R14, R15;
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popq %rdi
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popq %rsi
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addq $8, %rsp # not for rbp
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popq 48(%rbp) # for rsp
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popq %rbx
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popq %rdx
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popq %rcx
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popq %rax
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popq %r8
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popq %r9
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popq %r10
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popq %r11
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popq %r12
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popq %r13
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popq %r14
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popq %r15
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movq %rbp, %rsp
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popq %rbp
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addq $16, %rsp
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iretq
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#text ENDS
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#END
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@@ -1,7 +1,7 @@
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TITLE CpuAsm.asm:
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;------------------------------------------------------------------------------
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;*
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;* Copyright (c) 2008 - 2011, Intel Corporation. All rights reserved.<BR>
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;* Copyright (c) 2008 - 2013, Intel Corporation. All rights reserved.<BR>
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;* This program and the accompanying materials
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;* are licensed and made available under the terms and conditions of the BSD License
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;* which accompanies this distribution. The full text of the license may be found at
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@@ -18,18 +18,6 @@
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.code
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EXTRN mErrorCodeFlag:DWORD ; Error code flags for exceptions
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;
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; point to the external interrupt vector table
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;
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ExternalVectorTablePtr QWORD 0
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InitializeExternalVectorTablePtr PROC PUBLIC
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mov ExternalVectorTablePtr, rcx
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ret
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InitializeExternalVectorTablePtr ENDP
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;------------------------------------------------------------------------------
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; VOID
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; SetCodeSelector (
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@@ -62,270 +50,5 @@ SetDataSelectors PROC PUBLIC
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ret
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SetDataSelectors ENDP
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;---------------------------------------;
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; CommonInterruptEntry ;
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;---------------------------------------;
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; The follow algorithm is used for the common interrupt routine.
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CommonInterruptEntry PROC PUBLIC
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cli
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;
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; All interrupt handlers are invoked through interrupt gates, so
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; IF flag automatically cleared at the entry point
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;
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;
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; Calculate vector number
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;
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xchg rcx, [rsp] ; get the return address of call, actually, it is the address of vector number.
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movzx ecx, word ptr [rcx]
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cmp ecx, 32 ; Intel reserved vector for exceptions?
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jae NoErrorCode
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bt mErrorCodeFlag, ecx
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jc @F
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NoErrorCode:
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;
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; Push a dummy error code on the stack
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; to maintain coherent stack map
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;
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push [rsp]
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mov qword ptr [rsp + 8], 0
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@@:
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push rbp
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mov rbp, rsp
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;
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; Stack:
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; +---------------------+ <-- 16-byte aligned ensured by processor
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; + Old SS +
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; +---------------------+
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; + Old RSP +
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; +---------------------+
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; + RFlags +
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; +---------------------+
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; + CS +
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; +---------------------+
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; + RIP +
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; +---------------------+
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; + Error Code +
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; +---------------------+
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; + RCX / Vector Number +
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; +---------------------+
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; + RBP +
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; +---------------------+ <-- RBP, 16-byte aligned
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;
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;
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; Since here the stack pointer is 16-byte aligned, so
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; EFI_FX_SAVE_STATE_X64 of EFI_SYSTEM_CONTEXT_x64
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; is 16-byte aligned
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;
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;; UINT64 Rdi, Rsi, Rbp, Rsp, Rbx, Rdx, Rcx, Rax;
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;; UINT64 R8, R9, R10, R11, R12, R13, R14, R15;
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push r15
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push r14
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push r13
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push r12
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push r11
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push r10
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push r9
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push r8
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push rax
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push qword ptr [rbp + 8] ; RCX
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push rdx
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push rbx
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push qword ptr [rbp + 48] ; RSP
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push qword ptr [rbp] ; RBP
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push rsi
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push rdi
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;; UINT64 Gs, Fs, Es, Ds, Cs, Ss; insure high 16 bits of each is zero
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movzx rax, word ptr [rbp + 56]
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push rax ; for ss
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movzx rax, word ptr [rbp + 32]
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push rax ; for cs
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mov rax, ds
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push rax
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mov rax, es
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push rax
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mov rax, fs
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push rax
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mov rax, gs
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push rax
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mov [rbp + 8], rcx ; save vector number
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;; UINT64 Rip;
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push qword ptr [rbp + 24]
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;; UINT64 Gdtr[2], Idtr[2];
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xor rax, rax
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push rax
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push rax
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sidt [rsp]
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xchg rax, [rsp + 2]
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xchg rax, [rsp]
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xchg rax, [rsp + 8]
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xor rax, rax
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push rax
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push rax
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sgdt [rsp]
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xchg rax, [rsp + 2]
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xchg rax, [rsp]
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xchg rax, [rsp + 8]
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;; UINT64 Ldtr, Tr;
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xor rax, rax
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str ax
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push rax
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sldt ax
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push rax
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;; UINT64 RFlags;
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push qword ptr [rbp + 40]
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;; UINT64 Cr0, Cr1, Cr2, Cr3, Cr4, Cr8;
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mov rax, cr8
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push rax
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mov rax, cr4
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or rax, 208h
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mov cr4, rax
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push rax
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mov rax, cr3
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push rax
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mov rax, cr2
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push rax
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xor rax, rax
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push rax
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mov rax, cr0
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push rax
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;; UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
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mov rax, dr7
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push rax
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mov rax, dr6
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push rax
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mov rax, dr3
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push rax
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mov rax, dr2
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push rax
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mov rax, dr1
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push rax
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mov rax, dr0
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push rax
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;; FX_SAVE_STATE_X64 FxSaveState;
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sub rsp, 512
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mov rdi, rsp
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db 0fh, 0aeh, 07h ;fxsave [rdi]
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||||
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||||
;; UEFI calling convention for x64 requires that Direction flag in EFLAGs is clear
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||||
cld
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;; UINT32 ExceptionData;
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push qword ptr [rbp + 16]
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;; call into exception handler
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mov rcx, [rbp + 8]
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mov rax, ExternalVectorTablePtr ; get the interrupt vectors base
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||||
mov rax, [rax + rcx * 8]
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or rax, rax ; NULL?
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||||
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||||
je nonNullValue;
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||||
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;; Prepare parameter and call
|
||||
; mov rcx, [rbp + 8]
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||||
mov rdx, rsp
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||||
;
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||||
; Per X64 calling convention, allocate maximum parameter stack space
|
||||
; and make sure RSP is 16-byte aligned
|
||||
;
|
||||
sub rsp, 4 * 8 + 8
|
||||
call rax
|
||||
add rsp, 4 * 8 + 8
|
||||
|
||||
nonNullValue:
|
||||
cli
|
||||
;; UINT64 ExceptionData;
|
||||
add rsp, 8
|
||||
|
||||
;; FX_SAVE_STATE_X64 FxSaveState;
|
||||
|
||||
mov rsi, rsp
|
||||
db 0fh, 0aeh, 0Eh ; fxrstor [rsi]
|
||||
add rsp, 512
|
||||
|
||||
;; UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
|
||||
;; Skip restoration of DRx registers to support in-circuit emualators
|
||||
;; or debuggers set breakpoint in interrupt/exception context
|
||||
add rsp, 8 * 6
|
||||
|
||||
;; UINT64 Cr0, Cr1, Cr2, Cr3, Cr4, Cr8;
|
||||
pop rax
|
||||
mov cr0, rax
|
||||
add rsp, 8 ; not for Cr1
|
||||
pop rax
|
||||
mov cr2, rax
|
||||
pop rax
|
||||
mov cr3, rax
|
||||
pop rax
|
||||
mov cr4, rax
|
||||
pop rax
|
||||
mov cr8, rax
|
||||
|
||||
;; UINT64 RFlags;
|
||||
pop qword ptr [rbp + 40]
|
||||
|
||||
;; UINT64 Ldtr, Tr;
|
||||
;; UINT64 Gdtr[2], Idtr[2];
|
||||
;; Best not let anyone mess with these particular registers...
|
||||
add rsp, 48
|
||||
|
||||
;; UINT64 Rip;
|
||||
pop qword ptr [rbp + 24]
|
||||
|
||||
;; UINT64 Gs, Fs, Es, Ds, Cs, Ss;
|
||||
pop rax
|
||||
; mov gs, rax ; not for gs
|
||||
pop rax
|
||||
; mov fs, rax ; not for fs
|
||||
; (X64 will not use fs and gs, so we do not restore it)
|
||||
pop rax
|
||||
mov es, rax
|
||||
pop rax
|
||||
mov ds, rax
|
||||
pop qword ptr [rbp + 32] ; for cs
|
||||
pop qword ptr [rbp + 56] ; for ss
|
||||
|
||||
;; UINT64 Rdi, Rsi, Rbp, Rsp, Rbx, Rdx, Rcx, Rax;
|
||||
;; UINT64 R8, R9, R10, R11, R12, R13, R14, R15;
|
||||
pop rdi
|
||||
pop rsi
|
||||
add rsp, 8 ; not for rbp
|
||||
pop qword ptr [rbp + 48] ; for rsp
|
||||
pop rbx
|
||||
pop rdx
|
||||
pop rcx
|
||||
pop rax
|
||||
pop r8
|
||||
pop r9
|
||||
pop r10
|
||||
pop r11
|
||||
pop r12
|
||||
pop r13
|
||||
pop r14
|
||||
pop r15
|
||||
|
||||
mov rsp, rbp
|
||||
pop rbp
|
||||
add rsp, 16
|
||||
iretq
|
||||
|
||||
CommonInterruptEntry ENDP
|
||||
|
||||
END
|
||||
|
||||
|
||||
Reference in New Issue
Block a user