1. Separated DxeSmmCpuExceptionHandlerLib.inf into 2 instance DxeCpuExceptionHandlerLib.inf and SmmCpuExceptionHandlerLib.inf.
2. Updated CPU Exception Handler Library instance according to the new CPU Exception Handler Library class definitions. 3. Updated CPU Exception Handler Library instance to handle the vector attributes defined in PI 1.2.1. Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com> Reviewed-by: Hot Tian <hot.tian@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14885 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
Jeff Fan
vanjeff
@@ -1,7 +1,7 @@
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/** @file
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x64 CPU Exception Hanlder.
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Copyright (c) 2012, Intel Corporation. All rights reserved.<BR>
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Copyright (c) 2012 - 2013, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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@@ -15,61 +15,102 @@
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#include "CpuExceptionCommon.h"
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/**
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Internal function to setup CPU exception handlers.
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Return address map of exception handler template so that C code can generate
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exception tables.
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@param IdtEntry Pointer to IDT entry to be updated.
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@param InterruptHandler IDT handler value.
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**/
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VOID
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InternalSetupCpuExceptionHandlers (
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VOID
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ArchUpdateIdtEntry (
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IN IA32_IDT_GATE_DESCRIPTOR *IdtEntry,
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IN UINTN InterruptHandler
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)
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{
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IA32_DESCRIPTOR IdtDescriptor;
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UINTN IdtSize;
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EXCEPTION_HANDLER_TEMPLATE_MAP TemplateMap;
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UINT16 CodeSegment;
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IA32_IDT_GATE_DESCRIPTOR *IdtEntry;
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UINTN Index;
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UINTN InterruptHandler;
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//
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// Read IDT descriptor and calculate IDT size
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//
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AsmReadIdtr (&IdtDescriptor);
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IdtSize = (IdtDescriptor.Limit + 1) / sizeof (IA32_IDT_GATE_DESCRIPTOR);
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if (IdtSize > CPU_EXCEPTION_NUM) {
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//
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// CPU exeption library only setup CPU_EXCEPTION_NUM exception handler at most
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//
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IdtSize = CPU_EXCEPTION_NUM;
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}
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//
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// Use current CS as the segment selector of interrupt gate in IDT
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//
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CodeSegment = AsmReadCs ();
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IdtEntry = (IA32_IDT_GATE_DESCRIPTOR *) IdtDescriptor.Base;
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GetTemplateAddressMap (&TemplateMap);
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for (Index = 0; Index < IdtSize; Index ++) {
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InterruptHandler = TemplateMap.ExceptionStart + Index * TemplateMap.ExceptionStubHeaderSize;
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IdtEntry[Index].Bits.OffsetLow = (UINT16)(UINTN)InterruptHandler;
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IdtEntry[Index].Bits.OffsetHigh = (UINT16)((UINTN)InterruptHandler >> 16);
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IdtEntry[Index].Bits.OffsetUpper = (UINT32)((UINTN)InterruptHandler >> 32);
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IdtEntry[Index].Bits.Selector = CodeSegment;
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IdtEntry[Index].Bits.GateType = IA32_IDT_GATE_TYPE_INTERRUPT_32;
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}
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IdtEntry->Bits.OffsetLow = (UINT16)(UINTN)InterruptHandler;
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IdtEntry->Bits.OffsetHigh = (UINT16)((UINTN)InterruptHandler >> 16);
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IdtEntry->Bits.OffsetUpper = (UINT32)((UINTN)InterruptHandler >> 32);
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IdtEntry->Bits.GateType = IA32_IDT_GATE_TYPE_INTERRUPT_32;
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}
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/**
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Common exception handler.
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Read IDT handler value from IDT entry.
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@param IdtEntry Pointer to IDT entry to be read.
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**/
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UINTN
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ArchGetIdtHandler (
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IN IA32_IDT_GATE_DESCRIPTOR *IdtEntry
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)
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{
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return IdtEntry->Bits.OffsetLow + (((UINTN) IdtEntry->Bits.OffsetHigh) << 16) +
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(((UINTN) IdtEntry->Bits.OffsetUpper) << 32);
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}
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/**
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Save CPU exception context when handling EFI_VECTOR_HANDOFF_HOOK_AFTER case.
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@param ExceptionType Exception type.
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@param SystemContext Pointer to EFI_SYSTEM_CONTEXT.
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**/
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VOID
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ArchSaveExceptionContext (
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IN UINTN ExceptionType,
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IN EFI_SYSTEM_CONTEXT SystemContext
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)
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{
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IA32_EFLAGS32 Eflags;
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//
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// Save Exception context in global variable
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//
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mReservedVectors[ExceptionType].OldSs = SystemContext.SystemContextX64->Ss;
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mReservedVectors[ExceptionType].OldSp = SystemContext.SystemContextX64->Rsp;
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mReservedVectors[ExceptionType].OldFlags = SystemContext.SystemContextX64->Rflags;
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mReservedVectors[ExceptionType].OldCs = SystemContext.SystemContextX64->Cs;
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mReservedVectors[ExceptionType].OldIp = SystemContext.SystemContextX64->Rip;
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mReservedVectors[ExceptionType].ExceptionData = SystemContext.SystemContextX64->ExceptionData;
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//
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// Clear IF flag to avoid old IDT handler enable interrupt by IRET
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//
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Eflags.UintN = SystemContext.SystemContextX64->Rflags;
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Eflags.Bits.IF = 0;
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SystemContext.SystemContextX64->Rflags = Eflags.UintN;
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//
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// Modify the EIP in stack, then old IDT handler will return to the stub code
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//
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SystemContext.SystemContextX64->Rip = (UINTN) mReservedVectors[ExceptionType].HookAfterStubHeaderCode;
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}
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/**
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Restore CPU exception context when handling EFI_VECTOR_HANDOFF_HOOK_AFTER case.
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@param ExceptionType Exception type.
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@param SystemContext Pointer to EFI_SYSTEM_CONTEXT.
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**/
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VOID
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ArchRestoreExceptionContext (
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IN UINTN ExceptionType,
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IN EFI_SYSTEM_CONTEXT SystemContext
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)
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{
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SystemContext.SystemContextX64->Ss = mReservedVectors[ExceptionType].OldSs;
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SystemContext.SystemContextX64->Rsp = mReservedVectors[ExceptionType].OldSp;
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SystemContext.SystemContextX64->Rflags = mReservedVectors[ExceptionType].OldFlags;
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SystemContext.SystemContextX64->Cs = mReservedVectors[ExceptionType].OldCs;
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SystemContext.SystemContextX64->Rip = mReservedVectors[ExceptionType].OldIp;
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SystemContext.SystemContextX64->ExceptionData = mReservedVectors[ExceptionType].ExceptionData;
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}
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/**
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Dump CPU content information.
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@param ExceptionType Exception type.
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@param SystemContext Pointer to EFI_SYSTEM_CONTEXT.
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**/
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VOID
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DumpCpuContent (
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IN UINTN ExceptionType,
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IN EFI_EXCEPTION_TYPE ExceptionType,
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IN EFI_SYSTEM_CONTEXT SystemContext
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)
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{
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@@ -0,0 +1,46 @@
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/** @file
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X64 arch definition for CPU Exception Handler Library.
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Copyright (c) 2013, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#ifndef _ARCH_CPU_INTERRUPT_DEFS_H_
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#define _ARCH_CPU_INTERRUPT_DEFS_H_
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typedef struct {
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EFI_SYSTEM_CONTEXT_X64 SystemContext;
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BOOLEAN ExceptionDataFlag;
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UINTN OldIdtHandler;
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} EXCEPTION_HANDLER_CONTEXT;
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//
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// Register Structure Definitions
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//
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typedef struct {
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EFI_STATUS_CODE_DATA Header;
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EFI_SYSTEM_CONTEXT_X64 SystemContext;
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} CPU_STATUS_CODE_TEMPLATE;
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typedef struct {
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SPIN_LOCK SpinLock;
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UINT32 ApicId;
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UINT32 Attribute;
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UINTN ExceptonHandler;
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UINTN OldSs;
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UINTN OldSp;
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UINTN OldFlags;
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UINTN OldCs;
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UINTN OldIp;
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UINTN ExceptionData;
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UINT8 HookAfterStubHeaderCode[HOOKAFTER_STUB_SIZE];
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} RESERVED_VECTORS_DATA;
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#endif
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@@ -1,5 +1,5 @@
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#------------------------------------------------------------------------------ ;
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# Copyright (c) 2012, Intel Corporation. All rights reserved.<BR>
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# Copyright (c) 2012 - 2013, Intel Corporation. All rights reserved.<BR>
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# This program and the accompanying materials
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# are licensed and made available under the terms and conditions of the BSD License
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# which accompanies this distribution. The full text of the license may be found at
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@@ -21,114 +21,264 @@
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#------------------------------------------------------------------------------
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#EXTRN ASM_PFX(mErrorCodeFlag):DWORD # Error code flags for exceptions
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ASM_GLOBAL ASM_PFX(CommonExceptionHandler)
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ASM_GLOBAL ASM_PFX(CommonInterruptEntry)
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ASM_GLOBAL ASM_PFX(HookAfterStubHeaderEnd)
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#EXTRN ASM_PFX(mErrorCodeFlag):DWORD # Error code flags for exceptions
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#EXTRN ASM_PFX(mDoFarReturnFlag):QWORD # Do far return flag
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.text
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#
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# point to the external interrupt vector table
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# exception handler stub table
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#
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Exception0Handle:
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pushq $0
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jmp ASM_PFX(CommonInterruptEntry)
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.byte 0x6a # push #VectorNum
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.byte 0
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pushq %rax
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.byte 0x48, 0xB8
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.quad ASM_PFX(CommonInterruptEntry)
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jmp *%rax
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Exception1Handle:
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pushq $1
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jmp ASM_PFX(CommonInterruptEntry)
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.byte 0x6a # push #VectorNum
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.byte 1
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pushq %rax
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.byte 0x48, 0xB8
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.quad ASM_PFX(CommonInterruptEntry)
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jmp *%rax
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Exception2Handle:
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pushq $2
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jmp ASM_PFX(CommonInterruptEntry)
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.byte 0x6a # push #VectorNum
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.byte 2
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pushq %rax
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.byte 0x48, 0xB8
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.quad ASM_PFX(CommonInterruptEntry)
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jmp *%rax
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Exception3Handle:
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pushq $3
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jmp ASM_PFX(CommonInterruptEntry)
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.byte 0x6a # push #VectorNum
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.byte 3
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pushq %rax
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.byte 0x48, 0xB8
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.quad ASM_PFX(CommonInterruptEntry)
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jmp *%rax
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Exception4Handle:
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pushq $4
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jmp ASM_PFX(CommonInterruptEntry)
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.byte 0x6a # push #VectorNum
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.byte 4
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pushq %rax
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.byte 0x48, 0xB8
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.quad ASM_PFX(CommonInterruptEntry)
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jmp *%rax
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Exception5Handle:
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pushq $5
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jmp ASM_PFX(CommonInterruptEntry)
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.byte 0x6a # push #VectorNum
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.byte 5
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pushq %rax
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.byte 0x48, 0xB8
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.quad ASM_PFX(CommonInterruptEntry)
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jmp *%rax
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Exception6Handle:
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pushq $6
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jmp ASM_PFX(CommonInterruptEntry)
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.byte 0x6a # push #VectorNum
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.byte 6
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pushq %rax
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.byte 0x48, 0xB8
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.quad ASM_PFX(CommonInterruptEntry)
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jmp *%rax
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Exception7Handle:
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pushq $7
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jmp ASM_PFX(CommonInterruptEntry)
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.byte 0x6a # push #VectorNum
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.byte 7
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pushq %rax
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.byte 0x48, 0xB8
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.quad ASM_PFX(CommonInterruptEntry)
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jmp *%rax
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Exception8Handle:
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pushq $8
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jmp ASM_PFX(CommonInterruptEntry)
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.byte 0x6a # push #VectorNum
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.byte 8
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pushq %rax
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.byte 0x48, 0xB8
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.quad ASM_PFX(CommonInterruptEntry)
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jmp *%rax
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Exception9Handle:
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pushq $9
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jmp ASM_PFX(CommonInterruptEntry)
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.byte 0x6a # push #VectorNum
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.byte 9
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pushq %rax
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.byte 0x48, 0xB8
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.quad ASM_PFX(CommonInterruptEntry)
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jmp *%rax
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Exception10Handle:
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pushq $10
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jmp ASM_PFX(CommonInterruptEntry)
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.byte 0x6a # push #VectorNum
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.byte 10
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pushq %rax
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.byte 0x48, 0xB8
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.quad ASM_PFX(CommonInterruptEntry)
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jmp *%rax
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Exception11Handle:
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pushq $11
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jmp ASM_PFX(CommonInterruptEntry)
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.byte 0x6a # push #VectorNum
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.byte 11
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pushq %rax
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.byte 0x48, 0xB8
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.quad ASM_PFX(CommonInterruptEntry)
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jmp *%rax
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Exception12Handle:
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pushq $12
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jmp ASM_PFX(CommonInterruptEntry)
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.byte 0x6a # push #VectorNum
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.byte 12
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pushq %rax
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.byte 0x48, 0xB8
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.quad ASM_PFX(CommonInterruptEntry)
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jmp *%rax
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Exception13Handle:
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pushq $13
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jmp ASM_PFX(CommonInterruptEntry)
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.byte 0x6a # push #VectorNum
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.byte 13
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pushq %rax
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.byte 0x48, 0xB8
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.quad ASM_PFX(CommonInterruptEntry)
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jmp *%rax
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Exception14Handle:
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pushq $14
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jmp ASM_PFX(CommonInterruptEntry)
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.byte 0x6a # push #VectorNum
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.byte 14
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pushq %rax
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.byte 0x48, 0xB8
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.quad ASM_PFX(CommonInterruptEntry)
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jmp *%rax
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Exception15Handle:
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pushq $15
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jmp ASM_PFX(CommonInterruptEntry)
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.byte 0x6a # push #VectorNum
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.byte 15
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pushq %rax
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.byte 0x48, 0xB8
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.quad ASM_PFX(CommonInterruptEntry)
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jmp *%rax
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Exception16Handle:
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pushq $16
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jmp ASM_PFX(CommonInterruptEntry)
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.byte 0x6a # push #VectorNum
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.byte 16
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pushq %rax
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.byte 0x48, 0xB8
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.quad ASM_PFX(CommonInterruptEntry)
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jmp *%rax
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Exception17Handle:
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pushq $17
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jmp ASM_PFX(CommonInterruptEntry)
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.byte 0x6a # push #VectorNum
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.byte 17
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pushq %rax
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.byte 0x48, 0xB8
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.quad ASM_PFX(CommonInterruptEntry)
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jmp *%rax
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Exception18Handle:
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pushq $18
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jmp ASM_PFX(CommonInterruptEntry)
|
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.byte 0x6a # push #VectorNum
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.byte 18
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pushq %rax
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.byte 0x48, 0xB8
|
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.quad ASM_PFX(CommonInterruptEntry)
|
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jmp *%rax
|
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Exception19Handle:
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pushq $19
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jmp ASM_PFX(CommonInterruptEntry)
|
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.byte 0x6a # push #VectorNum
|
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.byte 19
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pushq %rax
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.byte 0x48, 0xB8
|
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.quad ASM_PFX(CommonInterruptEntry)
|
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jmp *%rax
|
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Exception20Handle:
|
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pushq $20
|
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jmp ASM_PFX(CommonInterruptEntry)
|
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.byte 0x6a # push #VectorNum
|
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.byte 20
|
||||
pushq %rax
|
||||
.byte 0x48, 0xB8
|
||||
.quad ASM_PFX(CommonInterruptEntry)
|
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jmp *%rax
|
||||
Exception21Handle:
|
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pushq $21
|
||||
jmp ASM_PFX(CommonInterruptEntry)
|
||||
.byte 0x6a # push #VectorNum
|
||||
.byte 21
|
||||
pushq %rax
|
||||
.byte 0x48, 0xB8
|
||||
.quad ASM_PFX(CommonInterruptEntry)
|
||||
jmp *%rax
|
||||
Exception22Handle:
|
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pushq $22
|
||||
jmp ASM_PFX(CommonInterruptEntry)
|
||||
.byte 0x6a # push #VectorNum
|
||||
.byte 22
|
||||
pushq %rax
|
||||
.byte 0x48, 0xB8
|
||||
.quad ASM_PFX(CommonInterruptEntry)
|
||||
jmp *%rax
|
||||
Exception23Handle:
|
||||
pushq $23
|
||||
jmp ASM_PFX(CommonInterruptEntry)
|
||||
.byte 0x6a # push #VectorNum
|
||||
.byte 23
|
||||
pushq %rax
|
||||
.byte 0x48, 0xB8
|
||||
.quad ASM_PFX(CommonInterruptEntry)
|
||||
jmp *%rax
|
||||
Exception24Handle:
|
||||
pushq $24
|
||||
jmp ASM_PFX(CommonInterruptEntry)
|
||||
.byte 0x6a # push #VectorNum
|
||||
.byte 24
|
||||
pushq %rax
|
||||
.byte 0x48, 0xB8
|
||||
.quad ASM_PFX(CommonInterruptEntry)
|
||||
jmp *%rax
|
||||
Exception25Handle:
|
||||
pushq $25
|
||||
jmp ASM_PFX(CommonInterruptEntry)
|
||||
.byte 0x6a # push #VectorNum
|
||||
.byte 25
|
||||
pushq %rax
|
||||
.byte 0x48, 0xB8
|
||||
.quad ASM_PFX(CommonInterruptEntry)
|
||||
jmp *%rax
|
||||
Exception26Handle:
|
||||
pushq $26
|
||||
jmp ASM_PFX(CommonInterruptEntry)
|
||||
.byte 0x6a # push #VectorNum
|
||||
.byte 26
|
||||
pushq %rax
|
||||
.byte 0x48, 0xB8
|
||||
.quad ASM_PFX(CommonInterruptEntry)
|
||||
jmp *%rax
|
||||
Exception27Handle:
|
||||
pushq $27
|
||||
jmp ASM_PFX(CommonInterruptEntry)
|
||||
.byte 0x6a # push #VectorNum
|
||||
.byte 27
|
||||
pushq %rax
|
||||
.byte 0x48, 0xB8
|
||||
.quad ASM_PFX(CommonInterruptEntry)
|
||||
jmp *%rax
|
||||
Exception28Handle:
|
||||
pushq $28
|
||||
jmp ASM_PFX(CommonInterruptEntry)
|
||||
.byte 0x6a # push #VectorNum
|
||||
.byte 28
|
||||
pushq %rax
|
||||
.byte 0x48, 0xB8
|
||||
.quad ASM_PFX(CommonInterruptEntry)
|
||||
jmp *%rax
|
||||
Exception29Handle:
|
||||
pushq $29
|
||||
jmp ASM_PFX(CommonInterruptEntry)
|
||||
.byte 0x6a # push #VectorNum
|
||||
.byte 29
|
||||
pushq %rax
|
||||
.byte 0x48, 0xB8
|
||||
.quad ASM_PFX(CommonInterruptEntry)
|
||||
jmp *%rax
|
||||
Exception30Handle:
|
||||
pushq $30
|
||||
jmp ASM_PFX(CommonInterruptEntry)
|
||||
.byte 0x6a # push #VectorNum
|
||||
.byte 30
|
||||
pushq %rax
|
||||
.byte 0x48, 0xB8
|
||||
.quad ASM_PFX(CommonInterruptEntry)
|
||||
jmp *%rax
|
||||
Exception31Handle:
|
||||
pushq $31
|
||||
jmp ASM_PFX(CommonInterruptEntry)
|
||||
|
||||
.byte 0x6a # push #VectorNum
|
||||
.byte 31
|
||||
pushq %rax
|
||||
.byte 0x48, 0xB8
|
||||
.quad ASM_PFX(CommonInterruptEntry)
|
||||
jmp *%rax
|
||||
|
||||
HookAfterStubHeaderBegin:
|
||||
.byte 0x6a # push
|
||||
VectorNum:
|
||||
.byte 0 # 0 will be fixed
|
||||
pushq %rax
|
||||
.byte 0x48, 0xB8 # movq ASM_PFX(HookAfterStubHeaderEnd), %rax
|
||||
.quad ASM_PFX(HookAfterStubHeaderEnd)
|
||||
jmp *%rax
|
||||
ASM_GLOBAL ASM_PFX(HookAfterStubHeaderEnd)
|
||||
ASM_PFX(HookAfterStubHeaderEnd):
|
||||
movq %rsp, %rax
|
||||
subq $8, %rsp
|
||||
andl $0x0fffffff0, %esp
|
||||
pushq %rcx
|
||||
movq 8(%rax), %rcx
|
||||
bt %ecx, ASM_PFX(mErrorCodeFlag)
|
||||
jc NoErrorData
|
||||
pushq (%rsp) # push additional rcx to make stack alignment
|
||||
NoErrorData:
|
||||
xchgq (%rsp), %rcx # restore rcx, save Exception Number in stack
|
||||
pushq (%rax) # push rax into stack to keep code consistence
|
||||
|
||||
#---------------------------------------;
|
||||
# CommonInterruptEntry ;
|
||||
@@ -138,6 +288,7 @@ Exception31Handle:
|
||||
ASM_GLOBAL ASM_PFX(CommonInterruptEntry)
|
||||
ASM_PFX(CommonInterruptEntry):
|
||||
cli
|
||||
popq %rax
|
||||
#
|
||||
# All interrupt handlers are invoked through interrupt gates, so
|
||||
# IF flag automatically cleared at the entry point
|
||||
@@ -145,7 +296,8 @@ ASM_PFX(CommonInterruptEntry):
|
||||
#
|
||||
# Calculate vector number
|
||||
#
|
||||
xchgq (%rsp), %rcx # get the return address of call, actually, it is the address of vector number.
|
||||
xchgq (%rsp), %rcx # get the return address of call, actually, it is the address of vector number.
|
||||
andq $0x0FF, %rcx
|
||||
cmp $32, %ecx # Intel reserved vector for exceptions?
|
||||
jae NoErrorCode
|
||||
pushq %rax
|
||||
@@ -165,6 +317,8 @@ NoErrorCode:
|
||||
CommonInterruptEntry_al_0000:
|
||||
pushq %rbp
|
||||
movq %rsp, %rbp
|
||||
pushq $0 # check EXCEPTION_HANDLER_CONTEXT.OldIdtHandler
|
||||
pushq $0 # check EXCEPTION_HANDLER_CONTEXT.ExceptionDataFlag
|
||||
|
||||
#
|
||||
# Stack:
|
||||
@@ -385,20 +539,53 @@ CommonInterruptEntry_al_0000:
|
||||
movq %rbp, %rsp
|
||||
popq %rbp
|
||||
addq $16, %rsp
|
||||
cmpq $0, -32(%rsp) # check EXCEPTION_HANDLER_CONTEXT.OldIdtHandler
|
||||
jz DoReturn # check EXCEPTION_HANDLER_CONTEXT.ExceptionDataFlag
|
||||
cmpb $1, -40(%rsp)
|
||||
jz ErrorCode
|
||||
jmp *-32(%rsp)
|
||||
ErrorCode:
|
||||
subq $8, %rsp
|
||||
jmp *-24(%rsp)
|
||||
|
||||
DoReturn:
|
||||
cmpq $0, ASM_PFX(mDoFarReturnFlag) # Check if need to do far return instead of IRET
|
||||
jz DoIret
|
||||
pushq %rax
|
||||
movq %rsp, %rax # save old RSP to rax
|
||||
movq 0x20(%rsp), %rsp
|
||||
pushq 0x10(%rax) # save CS in new location
|
||||
pushq 0x8(%rax) # save EIP in new location
|
||||
pushq 0x18(%rax) # save EFLAGS in new location
|
||||
movq (%rax), %rax # restore rax
|
||||
popfq # restore EFLAGS
|
||||
.byte 0x48 # prefix to composite "retq" with next "retf"
|
||||
retf # far return
|
||||
DoIret:
|
||||
iretq
|
||||
|
||||
|
||||
#-------------------------------------------------------------------------------------
|
||||
# AsmGetAddressMap (&AddressMap);
|
||||
# AsmGetTemplateAddressMap (&AddressMap);
|
||||
#-------------------------------------------------------------------------------------
|
||||
# comments here for definition of address map
|
||||
ASM_GLOBAL ASM_PFX(GetTemplateAddressMap)
|
||||
ASM_PFX(GetTemplateAddressMap):
|
||||
ASM_GLOBAL ASM_PFX(AsmGetTemplateAddressMap)
|
||||
ASM_PFX(AsmGetTemplateAddressMap):
|
||||
|
||||
movabsq $Exception0Handle, %rax
|
||||
movq %rax, (%rcx)
|
||||
movq $(Exception1Handle - Exception0Handle), 0x08(%rcx)
|
||||
movabsq $HookAfterStubHeaderBegin, %rax
|
||||
movq %rax, 0x10(%rcx)
|
||||
ret
|
||||
|
||||
#-------------------------------------------------------------------------------------
|
||||
# AsmVectorNumFixup (*VectorBase, VectorNum);
|
||||
#-------------------------------------------------------------------------------------
|
||||
ASM_GLOBAL ASM_PFX(AsmVectorNumFixup)
|
||||
ASM_PFX(AsmVectorNumFixup):
|
||||
movq %rdx, %rax
|
||||
movb %al, (VectorNum - HookAfterStubHeaderBegin)(%rcx)
|
||||
ret
|
||||
|
||||
#END
|
||||
|
||||
@@ -25,133 +25,79 @@
|
||||
;
|
||||
externdef CommonExceptionHandler:near
|
||||
|
||||
EXTRN mErrorCodeFlag:DWORD ; Error code flags for exceptions
|
||||
EXTRN mErrorCodeFlag:DWORD ; Error code flags for exceptions
|
||||
EXTRN mDoFarReturnFlag:QWORD ; Do far return flag
|
||||
|
||||
data SEGMENT
|
||||
|
||||
CommonEntryAddr dq CommonInterruptEntry;
|
||||
|
||||
.code
|
||||
|
||||
Exception0Handle:
|
||||
push 0
|
||||
jmp qword ptr [CommonEntryAddr]
|
||||
Exception1Handle:
|
||||
push 1
|
||||
jmp qword ptr [CommonEntryAddr]
|
||||
Exception2Handle:
|
||||
push 2
|
||||
jmp qword ptr [CommonEntryAddr]
|
||||
Exception3Handle:
|
||||
push 3
|
||||
jmp qword ptr [CommonEntryAddr]
|
||||
Exception4Handle:
|
||||
push 4
|
||||
jmp qword ptr [CommonEntryAddr]
|
||||
Exception5Handle:
|
||||
push 5
|
||||
jmp qword ptr [CommonEntryAddr]
|
||||
Exception6Handle:
|
||||
push 6
|
||||
jmp qword ptr [CommonEntryAddr]
|
||||
Exception7Handle:
|
||||
push 7
|
||||
jmp qword ptr [CommonEntryAddr]
|
||||
Exception8Handle:
|
||||
push 8
|
||||
jmp qword ptr [CommonEntryAddr]
|
||||
Exception9Handle:
|
||||
push 9
|
||||
jmp qword ptr [CommonEntryAddr]
|
||||
Exception10Handle:
|
||||
push 10
|
||||
jmp qword ptr [CommonEntryAddr]
|
||||
Exception11Handle:
|
||||
push 11
|
||||
jmp qword ptr [CommonEntryAddr]
|
||||
Exception12Handle:
|
||||
push 12
|
||||
jmp qword ptr [CommonEntryAddr]
|
||||
Exception13Handle:
|
||||
push 13
|
||||
jmp qword ptr [CommonEntryAddr]
|
||||
Exception14Handle:
|
||||
push 14
|
||||
jmp qword ptr [CommonEntryAddr]
|
||||
Exception15Handle:
|
||||
push 15
|
||||
jmp qword ptr [CommonEntryAddr]
|
||||
Exception16Handle:
|
||||
push 16
|
||||
jmp qword ptr [CommonEntryAddr]
|
||||
Exception17Handle:
|
||||
push 17
|
||||
jmp qword ptr [CommonEntryAddr]
|
||||
Exception18Handle:
|
||||
push 18
|
||||
jmp qword ptr [CommonEntryAddr]
|
||||
Exception19Handle:
|
||||
push 19
|
||||
jmp qword ptr [CommonEntryAddr]
|
||||
Exception20Handle:
|
||||
push 20
|
||||
jmp qword ptr [CommonEntryAddr]
|
||||
Exception21Handle:
|
||||
push 21
|
||||
jmp qword ptr [CommonEntryAddr]
|
||||
Exception22Handle:
|
||||
push 22
|
||||
jmp qword ptr [CommonEntryAddr]
|
||||
Exception23Handle:
|
||||
push 23
|
||||
jmp qword ptr [CommonEntryAddr]
|
||||
Exception24Handle:
|
||||
push 24
|
||||
jmp qword ptr [CommonEntryAddr]
|
||||
Exception25Handle:
|
||||
push 25
|
||||
jmp qword ptr [CommonEntryAddr]
|
||||
Exception26Handle:
|
||||
push 26
|
||||
jmp qword ptr [CommonEntryAddr]
|
||||
Exception27Handle:
|
||||
push 27
|
||||
jmp qword ptr [CommonEntryAddr]
|
||||
Exception28Handle:
|
||||
push 28
|
||||
jmp qword ptr [CommonEntryAddr]
|
||||
Exception29Handle:
|
||||
push 29
|
||||
jmp qword ptr [CommonEntryAddr]
|
||||
Exception30Handle:
|
||||
push 30
|
||||
jmp qword ptr [CommonEntryAddr]
|
||||
Exception31Handle:
|
||||
push 31
|
||||
jmp qword ptr [CommonEntryAddr]
|
||||
ALIGN 8
|
||||
|
||||
;CommonInterruptEntrypoint:
|
||||
;---------------------------------------;
|
||||
; _CommonEntry ;
|
||||
;----------------------------------------------------------------------------;
|
||||
; The follow algorithm is used for the common interrupt routine.
|
||||
; Entry from each interrupt with a push eax and eax=interrupt number
|
||||
AsmIdtVectorBegin:
|
||||
REPEAT 32
|
||||
db 6ah ; push #VectorNum
|
||||
db ($ - AsmIdtVectorBegin) / ((AsmIdtVectorEnd - AsmIdtVectorBegin) / 32) ; VectorNum
|
||||
push rax
|
||||
mov rax, CommonInterruptEntry
|
||||
jmp rax
|
||||
ENDM
|
||||
AsmIdtVectorEnd:
|
||||
|
||||
HookAfterStubHeaderBegin:
|
||||
db 6ah ; push
|
||||
@VectorNum:
|
||||
db 0 ; 0 will be fixed
|
||||
push rax
|
||||
mov rax, HookAfterStubHeaderEnd
|
||||
jmp rax
|
||||
HookAfterStubHeaderEnd:
|
||||
mov rax, rsp
|
||||
sub rsp, 8h
|
||||
and sp, 0fff0h
|
||||
push rcx
|
||||
mov rcx, [rax + 8]
|
||||
bt mErrorCodeFlag, ecx
|
||||
jc @F
|
||||
push [rsp] ; push additional rcx to make stack alignment
|
||||
@@:
|
||||
xchg rcx, [rsp] ; restore rcx, save Exception Number in stack
|
||||
push [rax] ; push rax into stack to keep code consistence
|
||||
|
||||
;---------------------------------------;
|
||||
; CommonInterruptEntry ;
|
||||
;---------------------------------------;
|
||||
; The follow algorithm is used for the common interrupt routine.
|
||||
|
||||
; Entry from each interrupt with a push eax and eax=interrupt number
|
||||
; Stack frame would be as follows as specified in IA32 manuals:
|
||||
;
|
||||
; +---------------------+ <-- 16-byte aligned ensured by processor
|
||||
; + Old SS +
|
||||
; +---------------------+
|
||||
; + Old RSP +
|
||||
; +---------------------+
|
||||
; + RFlags +
|
||||
; +---------------------+
|
||||
; + CS +
|
||||
; +---------------------+
|
||||
; + RIP +
|
||||
; +---------------------+
|
||||
; + Error Code +
|
||||
; +---------------------+
|
||||
; + Vector Number +
|
||||
; +---------------------+
|
||||
; + RBP +
|
||||
; +---------------------+ <-- RBP, 16-byte aligned
|
||||
; The follow algorithm is used for the common interrupt routine.
|
||||
CommonInterruptEntry PROC PUBLIC
|
||||
cli
|
||||
pop rax
|
||||
;
|
||||
; All interrupt handlers are invoked through interrupt gates, so
|
||||
; IF flag automatically cleared at the entry point
|
||||
;
|
||||
;
|
||||
; Calculate vector number
|
||||
;
|
||||
xchg rcx, [rsp] ; get the return address of call, actually, it is the address of vector number.
|
||||
xchg rcx, [rsp] ; Save rcx into stack and save vector number into rcx
|
||||
and rcx, 0FFh
|
||||
cmp ecx, 32 ; Intel reserved vector for exceptions?
|
||||
jae NoErrorCode
|
||||
bt mErrorCodeFlag, ecx
|
||||
@@ -168,6 +114,8 @@ NoErrorCode:
|
||||
@@:
|
||||
push rbp
|
||||
mov rbp, rsp
|
||||
push 0 ; clear EXCEPTION_HANDLER_CONTEXT.OldIdtHandler
|
||||
push 0 ; clear EXCEPTION_HANDLER_CONTEXT.ExceptionDataFlag
|
||||
|
||||
;
|
||||
; Stack:
|
||||
@@ -389,6 +337,29 @@ NoErrorCode:
|
||||
mov rsp, rbp
|
||||
pop rbp
|
||||
add rsp, 16
|
||||
cmp qword ptr [rsp - 32], 0 ; check EXCEPTION_HANDLER_CONTEXT.OldIdtHandler
|
||||
jz DoReturn
|
||||
cmp qword ptr [rsp - 40], 1 ; check EXCEPTION_HANDLER_CONTEXT.ExceptionDataFlag
|
||||
jz ErrorCode
|
||||
jmp qword ptr [rsp - 32]
|
||||
ErrorCode:
|
||||
sub rsp, 8
|
||||
jmp qword ptr [rsp - 24]
|
||||
|
||||
DoReturn:
|
||||
cmp mDoFarReturnFlag, 0 ; Check if need to do far return instead of IRET
|
||||
jz DoIret
|
||||
push rax
|
||||
mov rax, rsp ; save old RSP to rax
|
||||
mov rsp, [rsp + 20h]
|
||||
push [rax + 10h] ; save CS in new location
|
||||
push [rax + 8h] ; save EIP in new location
|
||||
push [rax + 18h] ; save EFLAGS in new location
|
||||
mov rax, [rax] ; restore rax
|
||||
popfq ; restore EFLAGS
|
||||
DB 48h ; prefix to composite "retq" with next "retf"
|
||||
retf ; far return
|
||||
DoIret:
|
||||
iretq
|
||||
|
||||
CommonInterruptEntry ENDP
|
||||
@@ -397,11 +368,22 @@ CommonInterruptEntry ENDP
|
||||
; GetTemplateAddressMap (&AddressMap);
|
||||
;-------------------------------------------------------------------------------------
|
||||
; comments here for definition of address map
|
||||
GetTemplateAddressMap PROC
|
||||
mov rax, offset Exception0Handle
|
||||
mov qword ptr [rcx], rax
|
||||
mov qword ptr [rcx+8h], Exception1Handle - Exception0Handle
|
||||
ret
|
||||
GetTemplateAddressMap ENDP
|
||||
AsmGetTemplateAddressMap PROC
|
||||
mov rax, offset AsmIdtVectorBegin
|
||||
mov qword ptr [rcx], rax
|
||||
mov qword ptr [rcx + 8h], (AsmIdtVectorEnd - AsmIdtVectorBegin) / 32
|
||||
mov rax, offset HookAfterStubHeaderBegin
|
||||
mov qword ptr [rcx + 10h], rax
|
||||
ret
|
||||
AsmGetTemplateAddressMap ENDP
|
||||
|
||||
;-------------------------------------------------------------------------------------
|
||||
; AsmVectorNumFixup (*VectorBase, VectorNum);
|
||||
;-------------------------------------------------------------------------------------
|
||||
AsmVectorNumFixup PROC
|
||||
mov rax, rdx
|
||||
mov [rcx + (@VectorNum - HookAfterStubHeaderBegin)], al
|
||||
ret
|
||||
AsmVectorNumFixup ENDP
|
||||
|
||||
END
|
||||
|
||||
Reference in New Issue
Block a user