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UefiPayloadPkg: Apply uncrustify changes

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REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3737

Apply uncrustify changes to .c/.h files in the UefiPayloadPkg package

Cc: Andrew Fish <afish@apple.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
This commit is contained in:
Michael Kubacki
2021-12-05 14:54:18 -08:00
committed by mergify[bot]
parent 053e878bfb
commit e5efcf8be8
76 changed files with 4281 additions and 4072 deletions
Download Patch File Download Diff File Expand all files Collapse all files

45
UefiPayloadPkg/Library/SpiFlashLib/PchSpi.c
View File

@@ -16,7 +16,7 @@
**/
UINT32
AcquireSpiBar0 (
IN UINTN PchSpiBase
IN UINTN PchSpiBase
)
{
return MmioRead32 (PchSpiBase + R_SPI_BASE) & ~(B_SPI_BAR0_MASK);
@@ -30,13 +30,11 @@ AcquireSpiBar0 (
**/
VOID
ReleaseSpiBar0 (
IN UINTN PchSpiBase
IN UINTN PchSpiBase
)
{
}
/**
This function is to enable/disable BIOS Write Protect in SMM phase.
@@ -45,22 +43,22 @@ ReleaseSpiBar0 (
**/
VOID
CpuSmmDisableBiosWriteProtect (
IN BOOLEAN EnableSmmSts
IN BOOLEAN EnableSmmSts
)
{
UINT32 Data32;
UINT32 Data32;
if(EnableSmmSts){
if (EnableSmmSts) {
//
// Disable BIOS Write Protect in SMM phase.
//
Data32 = MmioRead32 ((UINTN) (0xFED30880)) | (UINT32) (BIT0);
Data32 = MmioRead32 ((UINTN)(0xFED30880)) | (UINT32)(BIT0);
AsmWriteMsr32 (0x000001FE, Data32);
} else {
//
// Enable BIOS Write Protect in SMM phase
//
Data32 = MmioRead32 ((UINTN) (0xFED30880)) & (UINT32) (~BIT0);
Data32 = MmioRead32 ((UINTN)(0xFED30880)) & (UINT32)(~BIT0);
AsmWriteMsr32 (0x000001FE, Data32);
}
@@ -70,7 +68,6 @@ CpuSmmDisableBiosWriteProtect (
Data32 = MmioRead32 (0xFED30880);
}
/**
This function is a hook for Spi to disable BIOS Write Protect.
@@ -84,11 +81,10 @@ CpuSmmDisableBiosWriteProtect (
EFI_STATUS
EFIAPI
DisableBiosWriteProtect (
IN UINTN PchSpiBase,
IN UINT8 CpuSmmBwp
IN UINTN PchSpiBase,
IN UINT8 CpuSmmBwp
)
{
//
// Write clear BC_SYNC_SS prior to change WPD from 0 to 1.
//
@@ -116,15 +112,14 @@ DisableBiosWriteProtect (
VOID
EFIAPI
EnableBiosWriteProtect (
IN UINTN PchSpiBase,
IN UINT8 CpuSmmBwp
IN UINTN PchSpiBase,
IN UINT8 CpuSmmBwp
)
{
//
// Disable the access to the BIOS space for write cycles
//
MmioAnd8 (PchSpiBase + R_SPI_BCR, (UINT8) (~B_SPI_BCR_BIOSWE));
MmioAnd8 (PchSpiBase + R_SPI_BCR, (UINT8)(~B_SPI_BCR_BIOSWE));
if (CpuSmmBwp != 0) {
CpuSmmDisableBiosWriteProtect (FALSE);
@@ -142,16 +137,18 @@ EnableBiosWriteProtect (
**/
UINT8
SaveAndDisableSpiPrefetchCache (
IN UINTN PchSpiBase
IN UINTN PchSpiBase
)
{
UINT8 BiosCtlSave;
UINT8 BiosCtlSave;
BiosCtlSave = MmioRead8 (PchSpiBase + R_SPI_BCR) & B_SPI_BCR_SRC;
MmioAndThenOr32 (PchSpiBase + R_SPI_BCR, \
(UINT32) (~B_SPI_BCR_SRC), \
(UINT32) (V_SPI_BCR_SRC_PREF_DIS_CACHE_DIS << B_SPI_BCR_SRC));
MmioAndThenOr32 (
PchSpiBase + R_SPI_BCR, \
(UINT32)(~B_SPI_BCR_SRC), \
(UINT32)(V_SPI_BCR_SRC_PREF_DIS_CACHE_DIS << B_SPI_BCR_SRC)
);
return BiosCtlSave;
}
@@ -165,8 +162,8 @@ SaveAndDisableSpiPrefetchCache (
**/
VOID
SetSpiBiosControlRegister (
IN UINTN PchSpiBase,
IN UINT8 BiosCtlValue
IN UINTN PchSpiBase,
IN UINT8 BiosCtlValue
)
{
MmioAndThenOr8 (PchSpiBase + R_SPI_BCR, (UINT8) ~B_SPI_BCR_SRC, BiosCtlValue);

179
UefiPayloadPkg/Library/SpiFlashLib/RegsSpi.h
View File

@@ -9,121 +9,112 @@
#ifndef REGS_SPI_H_
#define REGS_SPI_H_
#define R_SPI_BASE 0x10 ///< 32-bit Memory Base Address Register
#define B_SPI_BAR0_MASK 0x0FFF
#define R_SPI_BCR 0xDC ///< BIOS Control Register
#define B_SPI_BCR_SRC (BIT3 | BIT2) ///< SPI Read Configuration (SRC)
#define V_SPI_BCR_SRC_PREF_DIS_CACHE_DIS 0x04 ///< Prefetch Disable, Cache Disable
#define B_SPI_BCR_SYNC_SS BIT8
#define B_SPI_BCR_BIOSWE BIT0 ///< Write Protect Disable (WPD)
#define R_SPI_BASE 0x10 ///< 32-bit Memory Base Address Register
#define B_SPI_BAR0_MASK 0x0FFF
#define R_SPI_BCR 0xDC ///< BIOS Control Register
#define B_SPI_BCR_SRC (BIT3 | BIT2) ///< SPI Read Configuration (SRC)
#define V_SPI_BCR_SRC_PREF_DIS_CACHE_DIS 0x04 ///< Prefetch Disable, Cache Disable
#define B_SPI_BCR_SYNC_SS BIT8
#define B_SPI_BCR_BIOSWE BIT0 ///< Write Protect Disable (WPD)
///
/// SPI Host Interface Registers
#define R_SPI_HSFS 0x04 ///< Hardware Sequencing Flash Status and Control Register(32bits)
#define B_SPI_HSFS_FDBC_MASK 0x3F000000 ///< Flash Data Byte Count ( <= 64), Count = (Value in this field) + 1.
#define N_SPI_HSFS_FDBC 24
#define B_SPI_HSFS_CYCLE_MASK 0x001E0000 ///< Flash Cycle.
#define N_SPI_HSFS_CYCLE 17
#define V_SPI_HSFS_CYCLE_READ 0 ///< Flash Cycle Read
#define V_SPI_HSFS_CYCLE_WRITE 2 ///< Flash Cycle Write
#define V_SPI_HSFS_CYCLE_4K_ERASE 3 ///< Flash Cycle 4K Block Erase
#define V_SPI_HSFS_CYCLE_64K_ERASE 4 ///< Flash Cycle 64K Sector Erase
#define V_SPI_HSFS_CYCLE_READ_SFDP 5 ///< Flash Cycle Read SFDP
#define V_SPI_HSFS_CYCLE_READ_JEDEC_ID 6 ///< Flash Cycle Read JEDEC ID
#define V_SPI_HSFS_CYCLE_WRITE_STATUS 7 ///< Flash Cycle Write Status
#define V_SPI_HSFS_CYCLE_READ_STATUS 8 ///< Flash Cycle Read Status
#define B_SPI_HSFS_CYCLE_FGO BIT16 ///< Flash Cycle Go.
#define B_SPI_HSFS_FDV BIT14 ///< Flash Descriptor Valid
#define B_SPI_HSFS_SCIP BIT5 ///< SPI Cycle in Progress
#define B_SPI_HSFS_FCERR BIT1 ///< Flash Cycle Error
#define B_SPI_HSFS_FDONE BIT0 ///< Flash Cycle Done
#define R_SPI_HSFS 0x04 ///< Hardware Sequencing Flash Status and Control Register(32bits)
#define B_SPI_HSFS_FDBC_MASK 0x3F000000 ///< Flash Data Byte Count ( <= 64), Count = (Value in this field) + 1.
#define N_SPI_HSFS_FDBC 24
#define B_SPI_HSFS_CYCLE_MASK 0x001E0000 ///< Flash Cycle.
#define N_SPI_HSFS_CYCLE 17
#define V_SPI_HSFS_CYCLE_READ 0 ///< Flash Cycle Read
#define V_SPI_HSFS_CYCLE_WRITE 2 ///< Flash Cycle Write
#define V_SPI_HSFS_CYCLE_4K_ERASE 3 ///< Flash Cycle 4K Block Erase
#define V_SPI_HSFS_CYCLE_64K_ERASE 4 ///< Flash Cycle 64K Sector Erase
#define V_SPI_HSFS_CYCLE_READ_SFDP 5 ///< Flash Cycle Read SFDP
#define V_SPI_HSFS_CYCLE_READ_JEDEC_ID 6 ///< Flash Cycle Read JEDEC ID
#define V_SPI_HSFS_CYCLE_WRITE_STATUS 7 ///< Flash Cycle Write Status
#define V_SPI_HSFS_CYCLE_READ_STATUS 8 ///< Flash Cycle Read Status
#define B_SPI_HSFS_CYCLE_FGO BIT16 ///< Flash Cycle Go.
#define B_SPI_HSFS_FDV BIT14 ///< Flash Descriptor Valid
#define B_SPI_HSFS_SCIP BIT5 ///< SPI Cycle in Progress
#define B_SPI_HSFS_FCERR BIT1 ///< Flash Cycle Error
#define B_SPI_HSFS_FDONE BIT0 ///< Flash Cycle Done
#define R_SPI_FADDR 0x08 ///< SPI Flash Address
#define B_SPI_FADDR_MASK 0x07FFFFFF ///< SPI Flash Address Mask (0~26bit)
#define R_SPI_FADDR 0x08 ///< SPI Flash Address
#define B_SPI_FADDR_MASK 0x07FFFFFF ///< SPI Flash Address Mask (0~26bit)
#define R_SPI_FDATA00 0x10 ///< SPI Data 00 (32 bits)
#define R_SPI_FRAP 0x50 ///< SPI Flash Regions Access Permissions Register
#define B_SPI_FRAP_BRWA_PLATFORM BIT12 // < Region write access for Region4 PlatformData
#define B_SPI_FRAP_BRWA_GBE BIT11 // < Region write access for Region3 GbE
#define B_SPI_FRAP_BRWA_SEC BIT10 ///< Region Write Access for Region2 SEC
#define B_SPI_FRAP_BRWA_BIOS BIT9 ///< Region Write Access for Region1 BIOS
#define B_SPI_FRAP_BRWA_FLASHD BIT8 ///< Region Write Access for Region0 Flash Descriptor
#define B_SPI_FRAP_BRRA_PLATFORM BIT4 ///< Region read access for Region4 PlatformData
#define B_SPI_FRAP_BRRA_GBE BIT3 ///< Region read access for Region3 GbE
#define B_SPI_FRAP_BRRA_SEC BIT2 ///< Region Read Access for Region2 SEC
#define B_SPI_FRAP_BRRA_BIOS BIT1 ///< Region Read Access for Region1 BIOS
#define B_SPI_FRAP_BRRA_FLASHD BIT0 ///< Region Read Access for Region0 Flash Descriptor
#define R_SPI_FDATA00 0x10 ///< SPI Data 00 (32 bits)
#define R_SPI_FREG0_FLASHD 0x54 ///< Flash Region 0 (Flash Descriptor) (32bits)
#define B_SPI_FREG0_LIMIT_MASK 0x7FFF0000 ///< Size, [30:16] here represents limit[26:12]
#define N_SPI_FREG0_LIMIT 4 ///< Bit 30:16 identifies address bits [26:12]
#define B_SPI_FREG0_BASE_MASK 0x00007FFF ///< Base, [14:0] here represents base [26:12]
#define N_SPI_FREG0_BASE 12 ///< Bit 14:0 identifies address bits [26:2]
#define R_SPI_FRAP 0x50 ///< SPI Flash Regions Access Permissions Register
#define B_SPI_FRAP_BRWA_PLATFORM BIT12 //< Region write access for Region4 PlatformData
#define B_SPI_FRAP_BRWA_GBE BIT11 //< Region write access for Region3 GbE
#define B_SPI_FRAP_BRWA_SEC BIT10 ///< Region Write Access for Region2 SEC
#define B_SPI_FRAP_BRWA_BIOS BIT9 ///< Region Write Access for Region1 BIOS
#define B_SPI_FRAP_BRWA_FLASHD BIT8 ///< Region Write Access for Region0 Flash Descriptor
#define B_SPI_FRAP_BRRA_PLATFORM BIT4 ///< Region read access for Region4 PlatformData
#define B_SPI_FRAP_BRRA_GBE BIT3 ///< Region read access for Region3 GbE
#define B_SPI_FRAP_BRRA_SEC BIT2 ///< Region Read Access for Region2 SEC
#define B_SPI_FRAP_BRRA_BIOS BIT1 ///< Region Read Access for Region1 BIOS
#define B_SPI_FRAP_BRRA_FLASHD BIT0 ///< Region Read Access for Region0 Flash Descriptor
#define R_SPI_FREG1_BIOS 0x58 ///< Flash Region 1 (BIOS) (32bits)
#define B_SPI_FREG1_LIMIT_MASK 0x7FFF0000 ///< Size, [30:16] here represents limit[26:12]
#define N_SPI_FREG1_LIMIT 4 ///< Bit 30:16 identifies address bits [26:12]
#define B_SPI_FREG1_BASE_MASK 0x00007FFF ///< Base, [14:0] here represents base [26:12]
#define N_SPI_FREG1_BASE 12 ///< Bit 14:0 identifies address bits [26:2]
#define R_SPI_FREG2_SEC 0x5C ///< Flash Region 2 (SEC) (32bits)
#define B_SPI_FREG2_LIMIT_MASK 0x7FFF0000 ///< Size, [30:16] here represents limit[26:12]
#define N_SPI_FREG2_LIMIT 4 // < Bit 30:16 identifies address bits [26:12]
#define B_SPI_FREG2_BASE_MASK 0x00007FFF ///< Base, [14:0] here represents base [26:12]
#define N_SPI_FREG2_BASE 12 // < Bit 14:0 identifies address bits [26:2]
#define R_SPI_FREG0_FLASHD 0x54 ///< Flash Region 0 (Flash Descriptor) (32bits)
#define B_SPI_FREG0_LIMIT_MASK 0x7FFF0000 ///< Size, [30:16] here represents limit[26:12]
#define N_SPI_FREG0_LIMIT 4 ///< Bit 30:16 identifies address bits [26:12]
#define B_SPI_FREG0_BASE_MASK 0x00007FFF ///< Base, [14:0] here represents base [26:12]
#define N_SPI_FREG0_BASE 12 ///< Bit 14:0 identifies address bits [26:2]
#define R_SPI_FREG3_GBE 0x60 // < Flash Region 3(GbE)(32bits)
#define B_SPI_FREG3_LIMIT_MASK 0x7FFF0000 ///< Size, [30:16] here represents limit[26:12]
#define N_SPI_FREG3_LIMIT 4 // < Bit 30:16 identifies address bits [26:12]
#define B_SPI_FREG3_BASE_MASK 0x00007FFF ///< Base, [14:0] here represents base [26:12]
#define N_SPI_FREG3_BASE 12 // < Bit 14:0 identifies address bits [26:2]
#define R_SPI_FREG1_BIOS 0x58 ///< Flash Region 1 (BIOS) (32bits)
#define B_SPI_FREG1_LIMIT_MASK 0x7FFF0000 ///< Size, [30:16] here represents limit[26:12]
#define N_SPI_FREG1_LIMIT 4 ///< Bit 30:16 identifies address bits [26:12]
#define B_SPI_FREG1_BASE_MASK 0x00007FFF ///< Base, [14:0] here represents base [26:12]
#define N_SPI_FREG1_BASE 12 ///< Bit 14:0 identifies address bits [26:2]
#define R_SPI_FREG4_PLATFORM_DATA 0x64 ///< Flash Region 4 (Platform Data) (32bits)
#define B_SPI_FREG4_LIMIT_MASK 0x7FFF0000 ///< Size, [30:16] here represents limit[26:12]
#define N_SPI_FREG4_LIMIT 4 ///< Bit 30:16 identifies address bits [26:12]
#define B_SPI_FREG4_BASE_MASK 0x00007FFF ///< Base, [14:0] here represents base [26:12]
#define N_SPI_FREG4_BASE 12 ///< Bit 14:0 identifies address bits [26:2]
#define R_SPI_FREG2_SEC 0x5C ///< Flash Region 2 (SEC) (32bits)
#define B_SPI_FREG2_LIMIT_MASK 0x7FFF0000 ///< Size, [30:16] here represents limit[26:12]
#define N_SPI_FREG2_LIMIT 4 //< Bit 30:16 identifies address bits [26:12]
#define B_SPI_FREG2_BASE_MASK 0x00007FFF ///< Base, [14:0] here represents base [26:12]
#define N_SPI_FREG2_BASE 12 //< Bit 14:0 identifies address bits [26:2]
#define S_SPI_FREGX 4 ///< Size of Flash Region register
#define B_SPI_FREGX_LIMIT_MASK 0x7FFF0000 ///< Flash Region Limit [30:16] represents [26:12], [11:0] are assumed to be FFFh
#define N_SPI_FREGX_LIMIT 16 ///< Region limit bit position
#define N_SPI_FREGX_LIMIT_REPR 12 ///< Region limit bit represents position
#define B_SPI_FREGX_BASE_MASK 0x00007FFF ///< Flash Region Base, [14:0] represents [26:12]
#define R_SPI_FREG3_GBE 0x60 //< Flash Region 3(GbE)(32bits)
#define B_SPI_FREG3_LIMIT_MASK 0x7FFF0000 ///< Size, [30:16] here represents limit[26:12]
#define N_SPI_FREG3_LIMIT 4 //< Bit 30:16 identifies address bits [26:12]
#define B_SPI_FREG3_BASE_MASK 0x00007FFF ///< Base, [14:0] here represents base [26:12]
#define N_SPI_FREG3_BASE 12 //< Bit 14:0 identifies address bits [26:2]
#define R_SPI_FDOC 0xB4 ///< Flash Descriptor Observability Control Register (32 bits)
#define B_SPI_FDOC_FDSS_MASK (BIT14 | BIT13 | BIT12) ///< Flash Descriptor Section Select
#define V_SPI_FDOC_FDSS_FSDM 0x0000 ///< Flash Signature and Descriptor Map
#define V_SPI_FDOC_FDSS_COMP 0x1000 ///< Component
#define B_SPI_FDOC_FDSI_MASK 0x0FFC ///< Flash Descriptor Section Index
#define R_SPI_FREG4_PLATFORM_DATA 0x64 ///< Flash Region 4 (Platform Data) (32bits)
#define B_SPI_FREG4_LIMIT_MASK 0x7FFF0000 ///< Size, [30:16] here represents limit[26:12]
#define N_SPI_FREG4_LIMIT 4 ///< Bit 30:16 identifies address bits [26:12]
#define B_SPI_FREG4_BASE_MASK 0x00007FFF ///< Base, [14:0] here represents base [26:12]
#define N_SPI_FREG4_BASE 12 ///< Bit 14:0 identifies address bits [26:2]
#define R_SPI_FDOD 0xB8 ///< Flash Descriptor Observability Data Register (32 bits)
#define R_SPI_LVSCC 0xC4 ///< Vendor Specific Component Capabilities for Component 0 (32 bits)
#define B_SPI_LVSCC_EO_64K BIT29 ///< < 64k Erase valid (EO_64k_valid)
#define S_SPI_FREGX 4 ///< Size of Flash Region register
#define B_SPI_FREGX_LIMIT_MASK 0x7FFF0000 ///< Flash Region Limit [30:16] represents [26:12], [11:0] are assumed to be FFFh
#define N_SPI_FREGX_LIMIT 16 ///< Region limit bit position
#define N_SPI_FREGX_LIMIT_REPR 12 ///< Region limit bit represents position
#define B_SPI_FREGX_BASE_MASK 0x00007FFF ///< Flash Region Base, [14:0] represents [26:12]
#define R_SPI_UVSCC 0xC8 ///< Vendor Specific Component Capabilities for Component 1 (32 bits)
#define R_SPI_FDBAR_FLASH_MAP0 0x14 ///< Flash MAP 0
#define N_SPI_FDBAR_NC 8 ///< < Number Of Components
#define B_SPI_FDBAR_NC 0x00000300 ///< Number Of Components
#define R_SPI_FDOC 0xB4 ///< Flash Descriptor Observability Control Register (32 bits)
#define B_SPI_FDOC_FDSS_MASK (BIT14 | BIT13 | BIT12) ///< Flash Descriptor Section Select
#define V_SPI_FDOC_FDSS_FSDM 0x0000 ///< Flash Signature and Descriptor Map
#define V_SPI_FDOC_FDSS_COMP 0x1000 ///< Component
#define B_SPI_FDOC_FDSI_MASK 0x0FFC ///< Flash Descriptor Section Index
#define R_SPI_FDOD 0xB8 ///< Flash Descriptor Observability Data Register (32 bits)
#define R_SPI_LVSCC 0xC4 ///<Vendor Specific Component Capabilities for Component 0 (32 bits)
#define B_SPI_LVSCC_EO_64K BIT29 ///<< 64k Erase valid (EO_64k_valid)
#define R_SPI_UVSCC 0xC8 ///< Vendor Specific Component Capabilities for Component 1 (32 bits)
#define R_SPI_FDBAR_FLASH_MAP0 0x14 ///< Flash MAP 0
#define N_SPI_FDBAR_NC 8 ///<< Number Of Components
#define B_SPI_FDBAR_NC 0x00000300 ///< Number Of Components
#define R_SPI_FDBAR_FLASH_MAP1 0x18 ///< Flash MAP 1
#define B_SPI_FDBAR_FPSBA 0x00FF0000 ///< Flash Strap Base Address
#define R_SPI_FDBAR_FLASH_MAP1 0x18 ///< Flash MAP 1
#define B_SPI_FDBAR_FPSBA 0x00FF0000 ///< Flash Strap Base Address
//
// Flash Component Base Address (FCBA) from Flash Region 0
//
#define R_SPI_FCBA_FLCOMP 0x00 ///< Flash Components Register
#define B_SPI_FLCOMP_COMP1_MASK 0x0F ///< Flash Component 1 Density
#define R_SPI_FCBA_FLCOMP 0x00 ///< Flash Components Register
#define B_SPI_FLCOMP_COMP1_MASK 0x0F ///< Flash Component 1 Density
#endif

53
UefiPayloadPkg/Library/SpiFlashLib/SpiCommon.h
View File

@@ -28,8 +28,8 @@
/// Wait Time = 6 seconds = 6000000 microseconds
/// Wait Period = 10 microseconds
///
#define WAIT_TIME 6000000 ///< Wait Time = 6 seconds = 6000000 microseconds
#define WAIT_PERIOD 10 ///< Wait Period = 10 microseconds
#define WAIT_TIME 6000000 ///< Wait Time = 6 seconds = 6000000 microseconds
#define WAIT_PERIOD 10 ///< Wait Period = 10 microseconds
///
/// Flash cycle Type
@@ -60,20 +60,19 @@ typedef enum {
#define SC_SPI_PRIVATE_DATA_SIGNATURE SIGNATURE_32 ('P', 'S', 'P', 'I')
typedef struct {
UINTN Signature;
EFI_HANDLE Handle;
UINT32 AcpiTmrReg;
UINTN PchSpiBase;
UINT16 RegionPermission;
UINT32 SfdpVscc0Value;
UINT32 SfdpVscc1Value;
UINT32 StrapBaseAddress;
UINT8 NumberOfComponents;
UINT16 Flags;
UINT32 Component1StartAddr;
UINTN Signature;
EFI_HANDLE Handle;
UINT32 AcpiTmrReg;
UINTN PchSpiBase;
UINT16 RegionPermission;
UINT32 SfdpVscc0Value;
UINT32 SfdpVscc1Value;
UINT32 StrapBaseAddress;
UINT8 NumberOfComponents;
UINT16 Flags;
UINT32 Component1StartAddr;
} SPI_INSTANCE;
/**
Acquire SPI MMIO BAR
@@ -84,10 +83,9 @@ typedef struct {
**/
UINT32
AcquireSpiBar0 (
IN UINTN PchSpiBase
IN UINTN PchSpiBase
);
/**
Release SPI MMIO BAR. Do nothing.
@@ -98,10 +96,9 @@ AcquireSpiBar0 (
**/
VOID
ReleaseSpiBar0 (
IN UINTN PchSpiBase
IN UINTN PchSpiBase
);
/**
This function is a hook for Spi to disable BIOS Write Protect
@@ -115,8 +112,8 @@ ReleaseSpiBar0 (
EFI_STATUS
EFIAPI
DisableBiosWriteProtect (
IN UINTN PchSpiBase,
IN UINT8 CpuSmmBwp
IN UINTN PchSpiBase,
IN UINT8 CpuSmmBwp
);
/**
@@ -131,11 +128,10 @@ DisableBiosWriteProtect (
VOID
EFIAPI
EnableBiosWriteProtect (
IN UINTN PchSpiBase,
IN UINT8 CpuSmmBwp
IN UINTN PchSpiBase,
IN UINT8 CpuSmmBwp
);
/**
This function disables SPI Prefetching and caching,
and returns previous BIOS Control Register value before disabling.
@@ -147,7 +143,7 @@ EnableBiosWriteProtect (
**/
UINT8
SaveAndDisableSpiPrefetchCache (
IN UINTN PchSpiBase
IN UINTN PchSpiBase
);
/**
@@ -161,11 +157,10 @@ SaveAndDisableSpiPrefetchCache (
**/
VOID
SetSpiBiosControlRegister (
IN UINTN PchSpiBase,
IN UINT8 BiosCtlValue
IN UINTN PchSpiBase,
IN UINT8 BiosCtlValue
);
/**
This function sends the programmed SPI command to the slave device.
@@ -201,8 +196,8 @@ SendSpiCmd (
**/
BOOLEAN
WaitForSpiCycleComplete (
IN UINT32 PchSpiBar0,
IN BOOLEAN ErrorCheck
IN UINT32 PchSpiBar0,
IN BOOLEAN ErrorCheck
);
#endif

402
UefiPayloadPkg/Library/SpiFlashLib/SpiFlashLib.c
View File

@@ -7,7 +7,7 @@
**/
#include "SpiCommon.h"
SPI_INSTANCE *mSpiInstance = NULL;
SPI_INSTANCE *mSpiInstance = NULL;
/**
Get SPI Instance from library global data..
@@ -17,20 +17,20 @@ SPI_INSTANCE *mSpiInstance = NULL;
SPI_INSTANCE *
GetSpiInstance (
VOID
)
)
{
if (mSpiInstance == NULL) {
mSpiInstance = AllocatePool (sizeof(SPI_INSTANCE));
mSpiInstance = AllocatePool (sizeof (SPI_INSTANCE));
if (mSpiInstance == NULL) {
return NULL;
}
ZeroMem (mSpiInstance, sizeof(SPI_INSTANCE));
ZeroMem (mSpiInstance, sizeof (SPI_INSTANCE));
}
return mSpiInstance;
}
/**
Initialize an SPI library.
@@ -43,11 +43,11 @@ SpiConstructor (
VOID
)
{
UINT32 ScSpiBar0;
UINT8 Comp0Density;
SPI_INSTANCE *SpiInstance;
EFI_HOB_GUID_TYPE *GuidHob;
SPI_FLASH_INFO *SpiFlashInfo;
UINT32 ScSpiBar0;
UINT8 Comp0Density;
SPI_INSTANCE *SpiInstance;
EFI_HOB_GUID_TYPE *GuidHob;
SPI_FLASH_INFO *SpiFlashInfo;
//
// Find SPI flash hob
@@ -57,7 +57,8 @@ SpiConstructor (
ASSERT (FALSE);
return EFI_NOT_FOUND;
}
SpiFlashInfo = (SPI_FLASH_INFO *) GET_GUID_HOB_DATA (GuidHob);
SpiFlashInfo = (SPI_FLASH_INFO *)GET_GUID_HOB_DATA (GuidHob);
//
// Initialize the SPI instance
@@ -66,10 +67,11 @@ SpiConstructor (
if (SpiInstance == NULL) {
return EFI_NOT_FOUND;
}
DEBUG ((DEBUG_INFO, "SpiInstance = %08X\n", SpiInstance));
SpiInstance->Signature = SC_SPI_PRIVATE_DATA_SIGNATURE;
SpiInstance->Handle = NULL;
SpiInstance->Signature = SC_SPI_PRIVATE_DATA_SIGNATURE;
SpiInstance->Handle = NULL;
//
// Check the SPI address
@@ -77,9 +79,11 @@ SpiConstructor (
if ((SpiFlashInfo->SpiAddress.AddressSpaceId != EFI_ACPI_3_0_PCI_CONFIGURATION_SPACE) ||
(SpiFlashInfo->SpiAddress.RegisterBitWidth != 32) ||
(SpiFlashInfo->SpiAddress.RegisterBitOffset != 0) ||
(SpiFlashInfo->SpiAddress.AccessSize != EFI_ACPI_3_0_DWORD)){
(SpiFlashInfo->SpiAddress.AccessSize != EFI_ACPI_3_0_DWORD))
{
DEBUG ((DEBUG_ERROR, "SPI FLASH HOB is not expected. need check the hob or enhance SPI flash driver.\n"));
}
SpiInstance->PchSpiBase = (UINT32)(UINTN)SpiFlashInfo->SpiAddress.Address;
SpiInstance->Flags = SpiFlashInfo->Flags;
DEBUG ((DEBUG_INFO, "PchSpiBase at 0x%x\n", SpiInstance->PchSpiBase));
@@ -106,34 +110,34 @@ SpiConstructor (
//
MmioAndThenOr32 (
ScSpiBar0 + R_SPI_FDOC,
(UINT32) (~(B_SPI_FDOC_FDSS_MASK | B_SPI_FDOC_FDSI_MASK)),
(UINT32) (V_SPI_FDOC_FDSS_FSDM | R_SPI_FDBAR_FLASH_MAP0)
(UINT32)(~(B_SPI_FDOC_FDSS_MASK | B_SPI_FDOC_FDSI_MASK)),
(UINT32)(V_SPI_FDOC_FDSS_FSDM | R_SPI_FDBAR_FLASH_MAP0)
);
//
// Copy Zero based Number Of Components
//
SpiInstance->NumberOfComponents = (UINT8) ((MmioRead16 (ScSpiBar0 + R_SPI_FDOD) & B_SPI_FDBAR_NC) >> N_SPI_FDBAR_NC);
SpiInstance->NumberOfComponents = (UINT8)((MmioRead16 (ScSpiBar0 + R_SPI_FDOD) & B_SPI_FDBAR_NC) >> N_SPI_FDBAR_NC);
MmioAndThenOr32 (
ScSpiBar0 + R_SPI_FDOC,
(UINT32) (~(B_SPI_FDOC_FDSS_MASK | B_SPI_FDOC_FDSI_MASK)),
(UINT32) (V_SPI_FDOC_FDSS_COMP | R_SPI_FCBA_FLCOMP)
(UINT32)(~(B_SPI_FDOC_FDSS_MASK | B_SPI_FDOC_FDSI_MASK)),
(UINT32)(V_SPI_FDOC_FDSS_COMP | R_SPI_FCBA_FLCOMP)
);
//
// Copy Component 0 Density
//
Comp0Density = (UINT8) MmioRead32 (ScSpiBar0 + R_SPI_FDOD) & B_SPI_FLCOMP_COMP1_MASK;
SpiInstance->Component1StartAddr = (UINT32) (SIZE_512KB << Comp0Density);
Comp0Density = (UINT8)MmioRead32 (ScSpiBar0 + R_SPI_FDOD) & B_SPI_FLCOMP_COMP1_MASK;
SpiInstance->Component1StartAddr = (UINT32)(SIZE_512KB << Comp0Density);
//
// Select FLASH_MAP1 to get Flash SC Strap Base Address
//
MmioAndThenOr32 (
(ScSpiBar0 + R_SPI_FDOC),
(UINT32) (~(B_SPI_FDOC_FDSS_MASK | B_SPI_FDOC_FDSI_MASK)),
(UINT32) (V_SPI_FDOC_FDSS_FSDM | R_SPI_FDBAR_FLASH_MAP1)
(UINT32)(~(B_SPI_FDOC_FDSS_MASK | B_SPI_FDOC_FDSI_MASK)),
(UINT32)(V_SPI_FDOC_FDSS_FSDM | R_SPI_FDBAR_FLASH_MAP1)
);
SpiInstance->StrapBaseAddress = MmioRead32 (ScSpiBar0 + R_SPI_FDOD) & B_SPI_FDBAR_FPSBA;
@@ -146,7 +150,6 @@ SpiConstructor (
return EFI_SUCCESS;
}
/**
Read data from the flash part.
@@ -169,7 +172,7 @@ SpiFlashRead (
OUT UINT8 *Buffer
)
{
EFI_STATUS Status;
EFI_STATUS Status;
Status = SendSpiCmd (FlashRegionType, FlashCycleRead, Address, ByteCount, Buffer);
return Status;
@@ -196,7 +199,7 @@ SpiFlashWrite (
IN UINT8 *Buffer
)
{
EFI_STATUS Status;
EFI_STATUS Status;
Status = SendSpiCmd (FlashRegionType, FlashCycleWrite, Address, ByteCount, Buffer);
return Status;
@@ -221,7 +224,7 @@ SpiFlashErase (
IN UINT32 ByteCount
)
{
EFI_STATUS Status;
EFI_STATUS Status;
Status = SendSpiCmd (FlashRegionType, FlashCycleErase, Address, ByteCount, NULL);
return Status;
@@ -242,14 +245,14 @@ SpiFlashErase (
EFI_STATUS
EFIAPI
SpiFlashReadSfdp (
IN UINT8 ComponentNumber,
IN UINT32 ByteCount,
OUT UINT8 *SfdpData
IN UINT8 ComponentNumber,
IN UINT32 ByteCount,
OUT UINT8 *SfdpData
)
{
EFI_STATUS Status;
UINT32 Address;
SPI_INSTANCE *SpiInstance;
EFI_STATUS Status;
UINT32 Address;
SPI_INSTANCE *SpiInstance;
SpiInstance = GetSpiInstance ();
if (SpiInstance == NULL) {
@@ -285,14 +288,14 @@ SpiFlashReadSfdp (
EFI_STATUS
EFIAPI
SpiFlashReadJedecId (
IN UINT8 ComponentNumber,
IN UINT32 ByteCount,
OUT UINT8 *JedecId
IN UINT8 ComponentNumber,
IN UINT32 ByteCount,
OUT UINT8 *JedecId
)
{
EFI_STATUS Status;
UINT32 Address;
SPI_INSTANCE *SpiInstance;
EFI_STATUS Status;
UINT32 Address;
SPI_INSTANCE *SpiInstance;
SpiInstance = GetSpiInstance ();
if (SpiInstance == NULL) {
@@ -326,11 +329,11 @@ SpiFlashReadJedecId (
EFI_STATUS
EFIAPI
SpiFlashWriteStatus (
IN UINT32 ByteCount,
IN UINT8 *StatusValue
IN UINT32 ByteCount,
IN UINT8 *StatusValue
)
{
EFI_STATUS Status;
EFI_STATUS Status;
Status = SendSpiCmd (0, FlashCycleWriteStatus, 0, ByteCount, StatusValue);
return Status;
@@ -349,11 +352,11 @@ SpiFlashWriteStatus (
EFI_STATUS
EFIAPI
SpiFlashReadStatus (
IN UINT32 ByteCount,
OUT UINT8 *StatusValue
IN UINT32 ByteCount,
OUT UINT8 *StatusValue
)
{
EFI_STATUS Status;
EFI_STATUS Status;
Status = SendSpiCmd (0, FlashCycleReadStatus, 0, ByteCount, StatusValue);
return Status;
@@ -374,14 +377,14 @@ SpiFlashReadStatus (
EFI_STATUS
EFIAPI
SpiReadPchSoftStrap (
IN UINT32 SoftStrapAddr,
IN UINT32 ByteCount,
OUT UINT8 *SoftStrapValue
IN UINT32 SoftStrapAddr,
IN UINT32 ByteCount,
OUT UINT8 *SoftStrapValue
)
{
UINT32 StrapFlashAddr;
EFI_STATUS Status;
SPI_INSTANCE *SpiInstance;
UINT32 StrapFlashAddr;
EFI_STATUS Status;
SPI_INSTANCE *SpiInstance;
SpiInstance = GetSpiInstance ();
if (SpiInstance == NULL) {
@@ -421,28 +424,28 @@ SendSpiCmd (
IN OUT UINT8 *Buffer
)
{
EFI_STATUS Status;
UINT32 Index;
UINTN SpiBaseAddress;
UINT32 ScSpiBar0;
UINT32 LimitAddress;
UINT32 HardwareSpiAddr;
UINT16 PermissionBit;
UINT32 SpiDataCount;
UINT32 FlashCycle;
UINT8 BiosCtlSave;
SPI_INSTANCE *SpiInstance;
UINT32 Data32;
EFI_STATUS Status;
UINT32 Index;
UINTN SpiBaseAddress;
UINT32 ScSpiBar0;
UINT32 LimitAddress;
UINT32 HardwareSpiAddr;
UINT16 PermissionBit;
UINT32 SpiDataCount;
UINT32 FlashCycle;
UINT8 BiosCtlSave;
SPI_INSTANCE *SpiInstance;
UINT32 Data32;
SpiInstance = GetSpiInstance ();
if (SpiInstance == NULL) {
return EFI_DEVICE_ERROR;
}
Status = EFI_SUCCESS;
SpiBaseAddress = SpiInstance->PchSpiBase;
ScSpiBar0 = AcquireSpiBar0 (SpiBaseAddress);
BiosCtlSave = 0;
Status = EFI_SUCCESS;
SpiBaseAddress = SpiInstance->PchSpiBase;
ScSpiBar0 = AcquireSpiBar0 (SpiBaseAddress);
BiosCtlSave = 0;
SpiInstance->RegionPermission = MmioRead16 (ScSpiBar0 + R_SPI_FRAP);
//
@@ -453,6 +456,7 @@ SendSpiCmd (
if (EFI_ERROR (Status)) {
goto SendSpiCmdEnd;
}
BiosCtlSave = SaveAndDisableSpiPrefetchCache (SpiBaseAddress);
}
@@ -467,76 +471,81 @@ SendSpiCmd (
HardwareSpiAddr = Address;
if ((FlashCycleType == FlashCycleRead) ||
(FlashCycleType == FlashCycleWrite) ||
(FlashCycleType == FlashCycleErase)) {
(FlashCycleType == FlashCycleErase))
{
switch (FlashRegionType) {
case FlashRegionDescriptor:
if (FlashCycleType == FlashCycleRead) {
PermissionBit = B_SPI_FRAP_BRRA_FLASHD;
} else {
PermissionBit = B_SPI_FRAP_BRWA_FLASHD;
}
Data32 = MmioRead32 (ScSpiBar0 + R_SPI_FREG0_FLASHD);
HardwareSpiAddr += (Data32 & B_SPI_FREG0_BASE_MASK) << N_SPI_FREG0_BASE;
LimitAddress = (Data32 & B_SPI_FREG0_LIMIT_MASK) >> N_SPI_FREG0_LIMIT;
break;
case FlashRegionDescriptor:
if (FlashCycleType == FlashCycleRead) {
PermissionBit = B_SPI_FRAP_BRRA_FLASHD;
} else {
PermissionBit = B_SPI_FRAP_BRWA_FLASHD;
}
case FlashRegionBios:
if (FlashCycleType == FlashCycleRead) {
PermissionBit = B_SPI_FRAP_BRRA_BIOS;
} else {
PermissionBit = B_SPI_FRAP_BRWA_BIOS;
}
Data32 = MmioRead32 (ScSpiBar0 + R_SPI_FREG1_BIOS);
HardwareSpiAddr += (Data32 & B_SPI_FREG1_BASE_MASK) << N_SPI_FREG1_BASE;
LimitAddress = (Data32 & B_SPI_FREG1_LIMIT_MASK) >> N_SPI_FREG1_LIMIT;
break;
Data32 = MmioRead32 (ScSpiBar0 + R_SPI_FREG0_FLASHD);
HardwareSpiAddr += (Data32 & B_SPI_FREG0_BASE_MASK) << N_SPI_FREG0_BASE;
LimitAddress = (Data32 & B_SPI_FREG0_LIMIT_MASK) >> N_SPI_FREG0_LIMIT;
break;
case FlashRegionMe:
if (FlashCycleType == FlashCycleRead) {
PermissionBit = B_SPI_FRAP_BRRA_SEC;
} else {
PermissionBit = B_SPI_FRAP_BRWA_SEC;
}
Data32 = MmioRead32 (ScSpiBar0 + R_SPI_FREG2_SEC);
HardwareSpiAddr += (Data32 & B_SPI_FREG2_BASE_MASK) << N_SPI_FREG2_BASE;
LimitAddress = (Data32 & B_SPI_FREG2_LIMIT_MASK) >> N_SPI_FREG2_LIMIT;
break;
case FlashRegionBios:
if (FlashCycleType == FlashCycleRead) {
PermissionBit = B_SPI_FRAP_BRRA_BIOS;
} else {
PermissionBit = B_SPI_FRAP_BRWA_BIOS;
}
case FlashRegionGbE:
if (FlashCycleType == FlashCycleRead) {
PermissionBit = B_SPI_FRAP_BRRA_GBE;
} else {
PermissionBit = B_SPI_FRAP_BRWA_GBE;
}
Data32 = MmioRead32 (ScSpiBar0 + R_SPI_FREG3_GBE);
HardwareSpiAddr += (Data32 & B_SPI_FREG3_BASE_MASK) << N_SPI_FREG3_BASE;
LimitAddress = (Data32 & B_SPI_FREG3_LIMIT_MASK) >> N_SPI_FREG3_LIMIT;
break;
Data32 = MmioRead32 (ScSpiBar0 + R_SPI_FREG1_BIOS);
HardwareSpiAddr += (Data32 & B_SPI_FREG1_BASE_MASK) << N_SPI_FREG1_BASE;
LimitAddress = (Data32 & B_SPI_FREG1_LIMIT_MASK) >> N_SPI_FREG1_LIMIT;
break;
case FlashRegionPlatformData:
if (FlashCycleType == FlashCycleRead) {
PermissionBit = B_SPI_FRAP_BRRA_PLATFORM;
} else {
PermissionBit = B_SPI_FRAP_BRWA_PLATFORM;
}
Data32 = MmioRead32 (ScSpiBar0 + R_SPI_FREG4_PLATFORM_DATA);
HardwareSpiAddr += (Data32 & B_SPI_FREG4_BASE_MASK) << N_SPI_FREG4_BASE;
LimitAddress = (Data32 & B_SPI_FREG4_LIMIT_MASK) >> N_SPI_FREG4_LIMIT;
break;
case FlashRegionMe:
if (FlashCycleType == FlashCycleRead) {
PermissionBit = B_SPI_FRAP_BRRA_SEC;
} else {
PermissionBit = B_SPI_FRAP_BRWA_SEC;
}
case FlashRegionAll:
//
// FlashRegionAll indicates address is relative to flash device
// No error checking for this case
//
LimitAddress = 0;
PermissionBit = 0;
break;
Data32 = MmioRead32 (ScSpiBar0 + R_SPI_FREG2_SEC);
HardwareSpiAddr += (Data32 & B_SPI_FREG2_BASE_MASK) << N_SPI_FREG2_BASE;
LimitAddress = (Data32 & B_SPI_FREG2_LIMIT_MASK) >> N_SPI_FREG2_LIMIT;
break;
default:
Status = EFI_UNSUPPORTED;
goto SendSpiCmdEnd;
case FlashRegionGbE:
if (FlashCycleType == FlashCycleRead) {
PermissionBit = B_SPI_FRAP_BRRA_GBE;
} else {
PermissionBit = B_SPI_FRAP_BRWA_GBE;
}
Data32 = MmioRead32 (ScSpiBar0 + R_SPI_FREG3_GBE);
HardwareSpiAddr += (Data32 & B_SPI_FREG3_BASE_MASK) << N_SPI_FREG3_BASE;
LimitAddress = (Data32 & B_SPI_FREG3_LIMIT_MASK) >> N_SPI_FREG3_LIMIT;
break;
case FlashRegionPlatformData:
if (FlashCycleType == FlashCycleRead) {
PermissionBit = B_SPI_FRAP_BRRA_PLATFORM;
} else {
PermissionBit = B_SPI_FRAP_BRWA_PLATFORM;
}
Data32 = MmioRead32 (ScSpiBar0 + R_SPI_FREG4_PLATFORM_DATA);
HardwareSpiAddr += (Data32 & B_SPI_FREG4_BASE_MASK) << N_SPI_FREG4_BASE;
LimitAddress = (Data32 & B_SPI_FREG4_LIMIT_MASK) >> N_SPI_FREG4_LIMIT;
break;
case FlashRegionAll:
//
// FlashRegionAll indicates address is relative to flash device
// No error checking for this case
//
LimitAddress = 0;
PermissionBit = 0;
break;
default:
Status = EFI_UNSUPPORTED;
goto SendSpiCmdEnd;
}
if ((LimitAddress != 0) && (Address > LimitAddress)) {
@@ -559,47 +568,48 @@ SendSpiCmd (
//
FlashCycle = 0;
switch (FlashCycleType) {
case FlashCycleRead:
FlashCycle = (UINT32) (V_SPI_HSFS_CYCLE_READ << N_SPI_HSFS_CYCLE);
break;
case FlashCycleRead:
FlashCycle = (UINT32)(V_SPI_HSFS_CYCLE_READ << N_SPI_HSFS_CYCLE);
break;
case FlashCycleWrite:
FlashCycle = (UINT32) (V_SPI_HSFS_CYCLE_WRITE << N_SPI_HSFS_CYCLE);
break;
case FlashCycleWrite:
FlashCycle = (UINT32)(V_SPI_HSFS_CYCLE_WRITE << N_SPI_HSFS_CYCLE);
break;
case FlashCycleErase:
if (((ByteCount % SIZE_4KB) != 0) || ((HardwareSpiAddr % SIZE_4KB) != 0)) {
DEBUG ((DEBUG_ERROR, "Erase and erase size must be 4KB aligned. \n"));
case FlashCycleErase:
if (((ByteCount % SIZE_4KB) != 0) || ((HardwareSpiAddr % SIZE_4KB) != 0)) {
DEBUG ((DEBUG_ERROR, "Erase and erase size must be 4KB aligned. \n"));
ASSERT (FALSE);
Status = EFI_INVALID_PARAMETER;
goto SendSpiCmdEnd;
}
break;
case FlashCycleReadSfdp:
FlashCycle = (UINT32)(V_SPI_HSFS_CYCLE_READ_SFDP << N_SPI_HSFS_CYCLE);
break;
case FlashCycleReadJedecId:
FlashCycle = (UINT32)(V_SPI_HSFS_CYCLE_READ_JEDEC_ID << N_SPI_HSFS_CYCLE);
break;
case FlashCycleWriteStatus:
FlashCycle = (UINT32)(V_SPI_HSFS_CYCLE_WRITE_STATUS << N_SPI_HSFS_CYCLE);
break;
case FlashCycleReadStatus:
FlashCycle = (UINT32)(V_SPI_HSFS_CYCLE_READ_STATUS << N_SPI_HSFS_CYCLE);
break;
default:
//
// Unrecognized Operation
//
ASSERT (FALSE);
Status = EFI_INVALID_PARAMETER;
goto SendSpiCmdEnd;
}
break;
case FlashCycleReadSfdp:
FlashCycle = (UINT32) (V_SPI_HSFS_CYCLE_READ_SFDP << N_SPI_HSFS_CYCLE);
break;
case FlashCycleReadJedecId:
FlashCycle = (UINT32) (V_SPI_HSFS_CYCLE_READ_JEDEC_ID << N_SPI_HSFS_CYCLE);
break;
case FlashCycleWriteStatus:
FlashCycle = (UINT32) (V_SPI_HSFS_CYCLE_WRITE_STATUS << N_SPI_HSFS_CYCLE);
break;
case FlashCycleReadStatus:
FlashCycle = (UINT32) (V_SPI_HSFS_CYCLE_READ_STATUS << N_SPI_HSFS_CYCLE);
break;
default:
//
// Unrecognized Operation
//
ASSERT (FALSE);
Status = EFI_INVALID_PARAMETER;
goto SendSpiCmdEnd;
break;
break;
}
do {
@@ -613,8 +623,9 @@ SendSpiCmd (
// per operation
//
if (HardwareSpiAddr + ByteCount > ((HardwareSpiAddr + BIT8) &~(BIT8 - 1))) {
SpiDataCount = (((UINT32) (HardwareSpiAddr) + BIT8) &~(BIT8 - 1)) - (UINT32) (HardwareSpiAddr);
SpiDataCount = (((UINT32)(HardwareSpiAddr) + BIT8) &~(BIT8 - 1)) - (UINT32)(HardwareSpiAddr);
}
//
// Calculate the number of bytes to shift in/out during the SPI data cycle.
// Valid settings for the number of bytes during each data portion of the
@@ -630,7 +641,8 @@ SendSpiCmd (
if (FlashCycleType == FlashCycleErase) {
if (((ByteCount / SIZE_64KB) != 0) &&
((ByteCount % SIZE_64KB) == 0) &&
((HardwareSpiAddr % SIZE_64KB) == 0)) {
((HardwareSpiAddr % SIZE_64KB) == 0))
{
if (HardwareSpiAddr < SpiInstance->Component1StartAddr) {
//
// Check whether Component0 support 64k Erase
@@ -653,10 +665,11 @@ SendSpiCmd (
} else {
SpiDataCount = SIZE_4KB;
}
if (SpiDataCount == SIZE_4KB) {
FlashCycle = (UINT32) (V_SPI_HSFS_CYCLE_4K_ERASE << N_SPI_HSFS_CYCLE);
FlashCycle = (UINT32)(V_SPI_HSFS_CYCLE_4K_ERASE << N_SPI_HSFS_CYCLE);
} else {
FlashCycle = (UINT32) (V_SPI_HSFS_CYCLE_64K_ERASE << N_SPI_HSFS_CYCLE);
FlashCycle = (UINT32)(V_SPI_HSFS_CYCLE_64K_ERASE << N_SPI_HSFS_CYCLE);
}
}
@@ -676,7 +689,7 @@ SendSpiCmd (
// Use Dword write if Data Count is 8, 16, 24, 32, 40, 48, 56, 64
//
for (Index = 0; Index < SpiDataCount; Index += sizeof (UINT32)) {
MmioWrite32 (ScSpiBar0 + R_SPI_FDATA00 + Index, *(UINT32 *) (Buffer + Index));
MmioWrite32 (ScSpiBar0 + R_SPI_FDATA00 + Index, *(UINT32 *)(Buffer + Index));
}
}
}
@@ -684,15 +697,15 @@ SendSpiCmd (
//
// Set the Flash Address
//
MmioWrite32 (ScSpiBar0 + R_SPI_FADDR, (UINT32) (HardwareSpiAddr & B_SPI_FADDR_MASK));
MmioWrite32 (ScSpiBar0 + R_SPI_FADDR, (UINT32)(HardwareSpiAddr & B_SPI_FADDR_MASK));
//
// Set Data count, Flash cycle, and Set Go bit to start a cycle
//
MmioAndThenOr32 (
ScSpiBar0 + R_SPI_HSFS,
(UINT32) (~(B_SPI_HSFS_FDBC_MASK | B_SPI_HSFS_CYCLE_MASK)),
(UINT32) (((SpiDataCount - 1) << N_SPI_HSFS_FDBC) | FlashCycle | B_SPI_HSFS_CYCLE_FGO)
(UINT32)(~(B_SPI_HSFS_FDBC_MASK | B_SPI_HSFS_CYCLE_MASK)),
(UINT32)(((SpiDataCount - 1) << N_SPI_HSFS_FDBC) | FlashCycle | B_SPI_HSFS_CYCLE_FGO)
);
//
@@ -709,7 +722,8 @@ SendSpiCmd (
if ((FlashCycleType == FlashCycleRead) ||
(FlashCycleType == FlashCycleReadSfdp) ||
(FlashCycleType == FlashCycleReadJedecId) ||
(FlashCycleType == FlashCycleReadStatus)) {
(FlashCycleType == FlashCycleReadStatus))
{
if ((SpiDataCount & 0x07) != 0) {
//
// Use Byte read if Data Count is 0, 1, 2, 3, 4, 5, 6, 7
@@ -722,7 +736,7 @@ SendSpiCmd (
// Use Dword read if Data Count is 8, 16, 24, 32, 40, 48, 56, 64
//
for (Index = 0; Index < SpiDataCount; Index += sizeof (UINT32)) {
*(UINT32 *) (Buffer + Index) = MmioRead32 (ScSpiBar0 + R_SPI_FDATA00 + Index);
*(UINT32 *)(Buffer + Index) = MmioRead32 (ScSpiBar0 + R_SPI_FDATA00 + Index);
}
}
}
@@ -737,7 +751,7 @@ SendSpiCmdEnd:
/// Restore the settings for SPI Prefetching and Caching and enable BIOS Write Protect
///
if ((FlashCycleType == FlashCycleWrite) || (FlashCycleType == FlashCycleErase)) {
EnableBiosWriteProtect (SpiBaseAddress, mSpiInstance->Flags & FLAGS_SPI_DISABLE_SMM_WRITE_PROTECT);
EnableBiosWriteProtect (SpiBaseAddress, mSpiInstance->Flags & FLAGS_SPI_DISABLE_SMM_WRITE_PROTECT);
SetSpiBiosControlRegister (SpiBaseAddress, BiosCtlSave);
}
@@ -758,13 +772,13 @@ SendSpiCmdEnd:
**/
BOOLEAN
WaitForSpiCycleComplete (
IN UINT32 ScSpiBar0,
IN BOOLEAN ErrorCheck
IN UINT32 ScSpiBar0,
IN BOOLEAN ErrorCheck
)
{
UINT64 WaitTicks;
UINT64 WaitCount;
UINT32 Data32;
UINT64 WaitTicks;
UINT64 WaitCount;
UINT32 Data32;
//
// Convert the wait period allowed into to tick count
@@ -783,8 +797,10 @@ WaitForSpiCycleComplete (
return TRUE;
}
}
MicroSecondDelay ( WAIT_PERIOD);
MicroSecondDelay (WAIT_PERIOD);
}
return FALSE;
}
@@ -807,32 +823,34 @@ SpiGetRegionAddress (
OUT UINT32 *RegionSize OPTIONAL
)
{
UINT32 ScSpiBar0;
UINT32 ReadValue;
UINT32 Base;
SPI_INSTANCE *SpiInstance;
UINT32 ScSpiBar0;
UINT32 ReadValue;
UINT32 Base;
SPI_INSTANCE *SpiInstance;
if (FlashRegionType >= FlashRegionMax) {
return EFI_INVALID_PARAMETER;
}
SpiInstance = GetSpiInstance();
SpiInstance = GetSpiInstance ();
if (SpiInstance == NULL) {
return EFI_DEVICE_ERROR;
}
if (FlashRegionType == FlashRegionAll) {
if (BaseAddress != NULL) {
*BaseAddress = 0;
*BaseAddress = 0;
}
if (RegionSize != NULL) {
*RegionSize = SpiInstance->Component1StartAddr;
*RegionSize = SpiInstance->Component1StartAddr;
}
return EFI_SUCCESS;
}
ScSpiBar0 = AcquireSpiBar0 (SpiInstance->PchSpiBase);
ReadValue = MmioRead32 (ScSpiBar0 + R_SPI_FREG0_FLASHD + S_SPI_FREGX * (UINT32) FlashRegionType);
ReadValue = MmioRead32 (ScSpiBar0 + R_SPI_FREG0_FLASHD + S_SPI_FREGX * (UINT32)FlashRegionType);
ReleaseSpiBar0 (SpiInstance->PchSpiBase);
//
@@ -849,7 +867,7 @@ SpiGetRegionAddress (
if (RegionSize != NULL) {
*RegionSize = ((((ReadValue & B_SPI_FREGX_LIMIT_MASK) >> N_SPI_FREGX_LIMIT) + 1) <<
N_SPI_FREGX_LIMIT_REPR) - Base;
N_SPI_FREGX_LIMIT_REPR) - Base;
}
return EFI_SUCCESS;