From e8aa4c6546ad5b04a1100fa2618e424f58e354f5 Mon Sep 17 00:00:00 2001
From: "Wu, MingliangX" <mingliangx.wu@intel.com>
Date: Mon, 21 Aug 2023 16:50:25 +0800
Subject: [PATCH] UefiCpuPkg/ResetVector: Cache Disable should not be set by
 default in CR0

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4511

With 64 bit build we are seeing the CD in control register CR 0 set.
This causes the NEM to disabled for some specific bios profiles.

Cc: Eric Dong <eric.dong@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Debkumar De <debkumar.de@intel.com>
Cc: Catharine West <catharine.west@intel.com>
Signed-off-by: Wu, Mingliang <mingliangx.wu@intel.com>
---
 UefiCpuPkg/ResetVector/Vtf0/Ia16/Real16ToFlat32.asm | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/UefiCpuPkg/ResetVector/Vtf0/Ia16/Real16ToFlat32.asm b/UefiCpuPkg/ResetVector/Vtf0/Ia16/Real16ToFlat32.asm
index f59fc6ead4..4af2e875c3 100644
--- a/UefiCpuPkg/ResetVector/Vtf0/Ia16/Real16ToFlat32.asm
+++ b/UefiCpuPkg/ResetVector/Vtf0/Ia16/Real16ToFlat32.asm
@@ -7,7 +7,7 @@
 ;
 ;------------------------------------------------------------------------------
 
-%define SEC_DEFAULT_CR0  0x40000023
+%define SEC_DEFAULT_CR0  0x00000023
 %define SEC_DEFAULT_CR4  0x640
 
 BITS    16