diff --git a/ArmPkg/Drivers/ArmGic/AArch64/ArmGicArchLib.c b/ArmPkg/Drivers/ArmGic/AArch64/ArmGicArchLib.c
index 9da69b2131..88fa4621e6 100644
--- a/ArmPkg/Drivers/ArmGic/AArch64/ArmGicArchLib.c
+++ b/ArmPkg/Drivers/ArmGic/AArch64/ArmGicArchLib.c
@@ -23,6 +23,8 @@ ArmGicGetSupportedArchRevision (
   VOID
   )
 {
+  UINT32    IccSre;
+
   // Ideally we would like to use the GICC IIDR Architecture version here, but
   // this does not seem to be very reliable as the implementation could easily
   // get it wrong. It is more reliable to check if the GICv3 System Register
@@ -37,8 +39,12 @@ ArmGicGetSupportedArchRevision (
     // Note: We do not need to set ICC_SRE_EL2.Enable because the OS is started
     // at the same exception level.
     // It is the OS responsibility to set this bit.
-    ArmGicV3SetControlSystemRegisterEnable (ArmGicV3GetControlSystemRegisterEnable () | ICC_SRE_EL2_SRE);
-    if (ArmGicV3GetControlSystemRegisterEnable () & ICC_SRE_EL2_SRE) {
+    IccSre = ArmGicV3GetControlSystemRegisterEnable ();
+    if (!(IccSre & ICC_SRE_EL2_SRE)) {
+      ArmGicV3SetControlSystemRegisterEnable (IccSre | ICC_SRE_EL2_SRE);
+      IccSre = ArmGicV3GetControlSystemRegisterEnable ();
+    }
+    if (IccSre & ICC_SRE_EL2_SRE) {
       return ARM_GIC_ARCH_REVISION_3;
     }
   }
diff --git a/ArmPkg/Drivers/ArmGic/Arm/ArmGicArchLib.c b/ArmPkg/Drivers/ArmGic/Arm/ArmGicArchLib.c
index f360a40583..9ef56efeaa 100644
--- a/ArmPkg/Drivers/ArmGic/Arm/ArmGicArchLib.c
+++ b/ArmPkg/Drivers/ArmGic/Arm/ArmGicArchLib.c
@@ -23,6 +23,8 @@ ArmGicGetSupportedArchRevision (
   VOID
   )
 {
+  UINT32    IccSre;
+
   // Ideally we would like to use the GICC IIDR Architecture version here, but
   // this does not seem to be very reliable as the implementation could easily
   // get it wrong. It is more reliable to check if the GICv3 System Register
@@ -37,8 +39,12 @@ ArmGicGetSupportedArchRevision (
     // Note: We do not need to set ICC_SRE_EL2.Enable because the OS is started
     // at the same exception level.
     // It is the OS responsibility to set this bit.
-    ArmGicV3SetControlSystemRegisterEnable (ArmGicV3GetControlSystemRegisterEnable () | ICC_SRE_EL2_SRE);
-    if (ArmGicV3GetControlSystemRegisterEnable () & ICC_SRE_EL2_SRE) {
+    IccSre = ArmGicV3GetControlSystemRegisterEnable ();
+    if (!(IccSre & ICC_SRE_EL2_SRE)) {
+      ArmGicV3SetControlSystemRegisterEnable (IccSre| ICC_SRE_EL2_SRE);
+      IccSre = ArmGicV3GetControlSystemRegisterEnable ();
+    }
+    if (IccSre & ICC_SRE_EL2_SRE) {
       return ARM_GIC_ARCH_REVISION_3;
     }
   }