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Revert "OvmfPkg/PlatformPei: reorder the 32-bit PCI window vs. the PCIEXBAR on q35"

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This reverts commit 75136b2954.

The original fix for <https://bugzilla.tianocore.org/show_bug.cgi?id=1814>
triggered a bug / incorrect assumption in QEMU.

QEMU assumes that the PCIEXBAR is below the 32-bit PCI window, not above
it. When the firmware doesn't satisfy this assumption, QEMU generates an
\_SB.PCI0._CRS object in the ACPI DSDT that does not reflect the
firmware's 32-bit MMIO BAR assignments. This causes OSes to re-assign
32-bit MMIO BARs.

Working around the problem in the firmware looks less problematic than
fixing QEMU. Revert the original changes first, before implementing an
alternative fix.

Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=1859
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Philippe Mathieu-Daude <philmd@redhat.com>
Acked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
This commit is contained in:
Laszlo Ersek
2019-05-29 11:51:26 +02:00
parent 305cd4f783
commit eb4d62b077
4 changed files with 17 additions and 7 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
OvmfPkg/OvmfPkgIa32.dsc
View File

@@ -490,7 +490,10 @@
# This PCD is used to set the base address of the PCI express hierarchy. It # This PCD is used to set the base address of the PCI express hierarchy. It
# is only consulted when OVMF runs on Q35. In that case it is programmed into # is only consulted when OVMF runs on Q35. In that case it is programmed into
# the PCIEXBAR register. # the PCIEXBAR register.
gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000 #
# On Q35 machine types that QEMU intends to support in the long term, QEMU
# never lets the RAM below 4 GB exceed 2 GB.
gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x80000000
!ifdef $(SOURCE_DEBUG_ENABLE) !ifdef $(SOURCE_DEBUG_ENABLE)
gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdDebugLoadImageMethod|0x2 gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdDebugLoadImageMethod|0x2

5
OvmfPkg/OvmfPkgIa32X64.dsc
View File

@@ -495,7 +495,10 @@
# This PCD is used to set the base address of the PCI express hierarchy. It # This PCD is used to set the base address of the PCI express hierarchy. It
# is only consulted when OVMF runs on Q35. In that case it is programmed into # is only consulted when OVMF runs on Q35. In that case it is programmed into
# the PCIEXBAR register. # the PCIEXBAR register.
gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000 #
# On Q35 machine types that QEMU intends to support in the long term, QEMU
# never lets the RAM below 4 GB exceed 2 GB.
gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x80000000
!ifdef $(SOURCE_DEBUG_ENABLE) !ifdef $(SOURCE_DEBUG_ENABLE)
gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdDebugLoadImageMethod|0x2 gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdDebugLoadImageMethod|0x2

5
OvmfPkg/OvmfPkgX64.dsc
View File

@@ -495,7 +495,10 @@
# This PCD is used to set the base address of the PCI express hierarchy. It # This PCD is used to set the base address of the PCI express hierarchy. It
# is only consulted when OVMF runs on Q35. In that case it is programmed into # is only consulted when OVMF runs on Q35. In that case it is programmed into
# the PCIEXBAR register. # the PCIEXBAR register.
gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000 #
# On Q35 machine types that QEMU intends to support in the long term, QEMU
# never lets the RAM below 4 GB exceed 2 GB.
gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x80000000
!ifdef $(SOURCE_DEBUG_ENABLE) !ifdef $(SOURCE_DEBUG_ENABLE)
gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdDebugLoadImageMethod|0x2 gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdDebugLoadImageMethod|0x2

9
OvmfPkg/PlatformPei/Platform.c
View File

@@ -184,13 +184,14 @@ MemMapInitialization (
PciBase = (TopOfLowRam < BASE_2GB) ? BASE_2GB : TopOfLowRam; PciBase = (TopOfLowRam < BASE_2GB) ? BASE_2GB : TopOfLowRam;
if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) { if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
// //
// The 32-bit PCI host aperture is expected to fall between the top of // The MMCONFIG area is expected to fall between the top of low RAM and
// low RAM and the base of the MMCONFIG area. // the base of the 32-bit PCI host aperture.
// //
PciExBarBase = FixedPcdGet64 (PcdPciExpressBaseAddress); PciExBarBase = FixedPcdGet64 (PcdPciExpressBaseAddress);
ASSERT (PciBase < PciExBarBase); ASSERT (TopOfLowRam <= PciExBarBase);
ASSERT (PciExBarBase <= MAX_UINT32 - SIZE_256MB); ASSERT (PciExBarBase <= MAX_UINT32 - SIZE_256MB);
PciSize = (UINT32)(PciExBarBase - PciBase); PciBase = (UINT32)(PciExBarBase + SIZE_256MB);
PciSize = 0xFC000000 - PciBase;
} else { } else {
PciSize = 0xFC000000 - PciBase; PciSize = 0xFC000000 - PciBase;
} }