ArmPlatformPkg/LcdGraphicsOutputDxe: move headers into driver directory
The HdLcd.h and PL111Lcd.h header files are internal headers that should not be used by other drivers. So move them from Include/Drivers into the driver directory instead. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
This commit is contained in:
Ard Biesheuvel
@@ -18,8 +18,7 @@
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#include <Library/MemoryAllocationLib.h>
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#include <Library/PcdLib.h>
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#include <Drivers/HdLcd.h>
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#include "HdLcd.h"
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#include "LcdGraphicsOutputDxe.h"
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/**********************************************************************
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89
ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/HdLcd.h
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89
ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/HdLcd.h
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@@ -0,0 +1,89 @@
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/** @file HDLcd.h
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Copyright (c) 2011-2012, ARM Ltd. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#ifndef _HDLCD_H_
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#define _HDLCD_H_
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//
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// HDLCD Controller Register Offsets
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//
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#define HDLCD_REG_VERSION ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x000)
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#define HDLCD_REG_INT_RAWSTAT ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x010)
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#define HDLCD_REG_INT_CLEAR ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x014)
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#define HDLCD_REG_INT_MASK ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x018)
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#define HDLCD_REG_INT_STATUS ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x01C)
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#define HDLCD_REG_FB_BASE ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x100)
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#define HDLCD_REG_FB_LINE_LENGTH ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x104)
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#define HDLCD_REG_FB_LINE_COUNT ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x108)
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#define HDLCD_REG_FB_LINE_PITCH ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x10C)
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#define HDLCD_REG_BUS_OPTIONS ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x110)
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#define HDLCD_REG_V_SYNC ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x200)
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#define HDLCD_REG_V_BACK_PORCH ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x204)
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#define HDLCD_REG_V_DATA ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x208)
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#define HDLCD_REG_V_FRONT_PORCH ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x20C)
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#define HDLCD_REG_H_SYNC ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x210)
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#define HDLCD_REG_H_BACK_PORCH ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x214)
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#define HDLCD_REG_H_DATA ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x218)
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#define HDLCD_REG_H_FRONT_PORCH ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x21C)
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#define HDLCD_REG_POLARITIES ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x220)
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#define HDLCD_REG_COMMAND ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x230)
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#define HDLCD_REG_PIXEL_FORMAT ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x240)
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#define HDLCD_REG_RED_SELECT ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x244)
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#define HDLCD_REG_GREEN_SELECT ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x248)
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#define HDLCD_REG_BLUE_SELECT ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x24C)
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//
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// HDLCD Values of registers
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//
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// HDLCD Interrupt mask, clear and status register
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#define HDLCD_DMA_END BIT0 /* DMA has finished reading a frame */
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#define HDLCD_BUS_ERROR BIT1 /* DMA bus error */
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#define HDLCD_SYNC BIT2 /* Vertical sync */
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#define HDLCD_UNDERRUN BIT3 /* No Data available while DATAEN active */
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// CLCD_CONTROL Control register
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#define HDLCD_DISABLE 0
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#define HDLCD_ENABLE BIT0
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// Bus Options
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#define HDLCD_BURST_1 BIT0
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#define HDLCD_BURST_2 BIT1
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#define HDLCD_BURST_4 BIT2
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#define HDLCD_BURST_8 BIT3
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#define HDLCD_BURST_16 BIT4
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// Polarities - HIGH
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#define HDLCD_VSYNC_HIGH BIT0
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#define HDLCD_HSYNC_HIGH BIT1
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#define HDLCD_DATEN_HIGH BIT2
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#define HDLCD_DATA_HIGH BIT3
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#define HDLCD_PXCLK_HIGH BIT4
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// Polarities - LOW (for completion and for ease of understanding the hardware settings)
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#define HDLCD_VSYNC_LOW 0
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#define HDLCD_HSYNC_LOW 0
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#define HDLCD_DATEN_LOW 0
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#define HDLCD_DATA_LOW 0
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#define HDLCD_PXCLK_LOW 0
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// Pixel Format
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#define HDLCD_LITTLE_ENDIAN (0 << 31)
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#define HDLCD_BIG_ENDIAN (1 << 31)
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// Number of bytes per pixel
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#define HDLCD_4BYTES_PER_PIXEL ((4 - 1) << 3)
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#endif /* _HDLCD_H_ */
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@@ -15,9 +15,8 @@
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#include <Library/IoLib.h>
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#include <Library/MemoryAllocationLib.h>
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#include <Drivers/PL111Lcd.h>
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#include "LcdGraphicsOutputDxe.h"
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#include "PL111Lcd.h"
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/**********************************************************************
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*
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149
ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111Lcd.h
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149
ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111Lcd.h
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@@ -0,0 +1,149 @@
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/** @file PL111Lcd.h
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Copyright (c) 2011, ARM Ltd. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#ifndef _PL111LCD_H__
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#define _PL111LCD_H__
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/**********************************************************************
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*
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* This header file contains all the bits of the PL111 that are
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* platform independent.
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*
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**********************************************************************/
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// Controller Register Offsets
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#define PL111_REG_LCD_TIMING_0 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x000)
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#define PL111_REG_LCD_TIMING_1 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x004)
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#define PL111_REG_LCD_TIMING_2 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x008)
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#define PL111_REG_LCD_TIMING_3 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x00C)
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#define PL111_REG_LCD_UP_BASE ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x010)
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#define PL111_REG_LCD_LP_BASE ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x014)
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#define PL111_REG_LCD_CONTROL ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x018)
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#define PL111_REG_LCD_IMSC ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x01C)
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#define PL111_REG_LCD_RIS ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x020)
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#define PL111_REG_LCD_MIS ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x024)
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#define PL111_REG_LCD_ICR ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x028)
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#define PL111_REG_LCD_UP_CURR ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x02C)
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#define PL111_REG_LCD_LP_CURR ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x030)
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#define PL111_REG_LCD_PALETTE ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x200)
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// Identification Register Offsets
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#define PL111_REG_CLCD_PERIPH_ID_0 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFE0)
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#define PL111_REG_CLCD_PERIPH_ID_1 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFE4)
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#define PL111_REG_CLCD_PERIPH_ID_2 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFE8)
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#define PL111_REG_CLCD_PERIPH_ID_3 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFEC)
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#define PL111_REG_CLCD_P_CELL_ID_0 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFF0)
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#define PL111_REG_CLCD_P_CELL_ID_1 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFF4)
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#define PL111_REG_CLCD_P_CELL_ID_2 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFF8)
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#define PL111_REG_CLCD_P_CELL_ID_3 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFFC)
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#define PL111_CLCD_PERIPH_ID_0 0x11
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#define PL111_CLCD_PERIPH_ID_1 0x11
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#define PL111_CLCD_PERIPH_ID_2 0x04
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#define PL111_CLCD_PERIPH_ID_3 0x00
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#define PL111_CLCD_P_CELL_ID_0 0x0D
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#define PL111_CLCD_P_CELL_ID_1 0xF0
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#define PL111_CLCD_P_CELL_ID_2 0x05
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#define PL111_CLCD_P_CELL_ID_3 0xB1
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/**********************************************************************/
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// Register components (register bits)
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// This should make life easier to program specific settings in the different registers
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// by simplifying the setting up of the individual bits of each register
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// and then assembling the final register value.
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/**********************************************************************/
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// Register: PL111_REG_LCD_TIMING_0
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#define HOR_AXIS_PANEL(hbp,hfp,hsw,hor_res) (UINT32)(((UINT32)(hbp) << 24) | ((UINT32)(hfp) << 16) | ((UINT32)(hsw) << 8) | (((UINT32)((hor_res)/16)-1) << 2))
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// Register: PL111_REG_LCD_TIMING_1
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#define VER_AXIS_PANEL(vbp,vfp,vsw,ver_res) (UINT32)(((UINT32)(vbp) << 24) | ((UINT32)(vfp) << 16) | ((UINT32)(vsw) << 10) | ((ver_res)-1))
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// Register: PL111_REG_LCD_TIMING_2
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#define PL111_BIT_SHIFT_PCD_HI 27
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#define PL111_BIT_SHIFT_BCD 26
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#define PL111_BIT_SHIFT_CPL 16
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#define PL111_BIT_SHIFT_IOE 14
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#define PL111_BIT_SHIFT_IPC 13
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#define PL111_BIT_SHIFT_IHS 12
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#define PL111_BIT_SHIFT_IVS 11
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#define PL111_BIT_SHIFT_ACB 6
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#define PL111_BIT_SHIFT_CLKSEL 5
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#define PL111_BIT_SHIFT_PCD_LO 0
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#define PL111_BCD (1 << 26)
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#define PL111_IPC (1 << 13)
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#define PL111_IHS (1 << 12)
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#define PL111_IVS (1 << 11)
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#define CLK_SIG_POLARITY(hor_res) (UINT32)(PL111_BCD | PL111_IPC | PL111_IHS | PL111_IVS | (((hor_res)-1) << 16))
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// Register: PL111_REG_LCD_TIMING_3
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#define PL111_BIT_SHIFT_LEE 16
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#define PL111_BIT_SHIFT_LED 0
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#define PL111_CTRL_WATERMARK (1 << 16)
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#define PL111_CTRL_LCD_V_COMP (1 << 12)
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#define PL111_CTRL_LCD_PWR (1 << 11)
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#define PL111_CTRL_BEPO (1 << 10)
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#define PL111_CTRL_BEBO (1 << 9)
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#define PL111_CTRL_BGR (1 << 8)
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#define PL111_CTRL_LCD_DUAL (1 << 7)
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#define PL111_CTRL_LCD_MONO_8 (1 << 6)
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#define PL111_CTRL_LCD_TFT (1 << 5)
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#define PL111_CTRL_LCD_BW (1 << 4)
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#define PL111_CTRL_LCD_1BPP (0 << 1)
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#define PL111_CTRL_LCD_2BPP (1 << 1)
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#define PL111_CTRL_LCD_4BPP (2 << 1)
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#define PL111_CTRL_LCD_8BPP (3 << 1)
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#define PL111_CTRL_LCD_16BPP (4 << 1)
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#define PL111_CTRL_LCD_24BPP (5 << 1)
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#define PL111_CTRL_LCD_16BPP_565 (6 << 1)
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#define PL111_CTRL_LCD_12BPP_444 (7 << 1)
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#define PL111_CTRL_LCD_BPP(Bpp) ((Bpp) << 1)
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#define PL111_CTRL_LCD_EN 1
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/**********************************************************************/
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// Register: PL111_REG_LCD_TIMING_0
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#define PL111_LCD_TIMING_0_HBP(hbp) (((hbp) & 0xFF) << 24)
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#define PL111_LCD_TIMING_0_HFP(hfp) (((hfp) & 0xFF) << 16)
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#define PL111_LCD_TIMING_0_HSW(hsw) (((hsw) & 0xFF) << 8)
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#define PL111_LCD_TIMING_0_PPL(ppl) (((hsw) & 0x3F) << 2)
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// Register: PL111_REG_LCD_TIMING_1
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#define PL111_LCD_TIMING_1_VBP(vbp) (((vbp) & 0xFF) << 24)
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#define PL111_LCD_TIMING_1_VFP(vfp) (((vfp) & 0xFF) << 16)
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#define PL111_LCD_TIMING_1_VSW(vsw) (((vsw) & 0x3F) << 10)
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#define PL111_LCD_TIMING_1_LPP(lpp) ((lpp) & 0xFC)
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// Register: PL111_REG_LCD_TIMING_2
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#define PL111_BIT_MASK_PCD_HI 0xF8000000
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#define PL111_BIT_MASK_BCD 0x04000000
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#define PL111_BIT_MASK_CPL 0x03FF0000
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#define PL111_BIT_MASK_IOE 0x00004000
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#define PL111_BIT_MASK_IPC 0x00002000
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#define PL111_BIT_MASK_IHS 0x00001000
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#define PL111_BIT_MASK_IVS 0x00000800
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#define PL111_BIT_MASK_ACB 0x000007C0
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#define PL111_BIT_MASK_CLKSEL 0x00000020
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#define PL111_BIT_MASK_PCD_LO 0x0000001F
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// Register: PL111_REG_LCD_TIMING_3
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#define PL111_BIT_MASK_LEE 0x00010000
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#define PL111_BIT_MASK_LED 0x0000007F
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#endif /* _PL111LCD_H__ */
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