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Update to make end-of-line consistent for all source files in MdePkg. There are no other updates besides that change.

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git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@9141 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
qhuang8
2009-08-19 14:02:07 +00:00
parent 792a153467
commit ebd04fc2e5
38 changed files with 5771 additions and 5771 deletions
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206
MdePkg/Include/Arm/ProcessorBind.h
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@ -1,118 +1,118 @@
/** @file
Processor or Compiler specific defines and types for ARM.
Copyright (c) 2006 - 2009, Intel Corporation
Portions copyright (c) 2008-2009 Apple Inc. All rights reserved.
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef __PROCESSOR_BIND_H__
#define __PROCESSOR_BIND_H__
///
/// Define the processor type so other code can make processor based choices
///
#define MDE_CPU_ARM
//
// Make sure we are useing the correct packing rules per EFI specification
//
#ifndef __GNUC__
#pragma pack()
#endif
#if _MSC_EXTENSIONS
//
// use Microsoft* C complier dependent interger width types
//
typedef unsigned __int64 UINT64;
typedef __int64 INT64;
typedef unsigned __int32 UINT32;
typedef __int32 INT32;
typedef unsigned short UINT16;
typedef unsigned short CHAR16;
typedef short INT16;
typedef unsigned char BOOLEAN;
typedef unsigned char UINT8;
typedef char CHAR8;
typedef char INT8;
#else
//
// Assume standard ARM alignment.
// Need to check portability of long long
//
typedef unsigned long long UINT64;
typedef long long INT64;
typedef unsigned int UINT32;
typedef int INT32;
typedef unsigned short UINT16;
typedef unsigned short CHAR16;
typedef short INT16;
typedef unsigned char BOOLEAN;
typedef unsigned char UINT8;
typedef char CHAR8;
typedef char INT8;
#endif
/** @file
Processor or Compiler specific defines and types for ARM.
Copyright (c) 2006 - 2009, Intel Corporation
Portions copyright (c) 2008-2009 Apple Inc. All rights reserved.
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef __PROCESSOR_BIND_H__
#define __PROCESSOR_BIND_H__
///
/// Define the processor type so other code can make processor based choices
///
#define MDE_CPU_ARM
//
// Make sure we are useing the correct packing rules per EFI specification
//
#ifndef __GNUC__
#pragma pack()
#endif
#if _MSC_EXTENSIONS
//
// use Microsoft* C complier dependent interger width types
//
typedef unsigned __int64 UINT64;
typedef __int64 INT64;
typedef unsigned __int32 UINT32;
typedef __int32 INT32;
typedef unsigned short UINT16;
typedef unsigned short CHAR16;
typedef short INT16;
typedef unsigned char BOOLEAN;
typedef unsigned char UINT8;
typedef char CHAR8;
typedef char INT8;
#else
//
// Assume standard ARM alignment.
// Need to check portability of long long
//
typedef unsigned long long UINT64;
typedef long long INT64;
typedef unsigned int UINT32;
typedef int INT32;
typedef unsigned short UINT16;
typedef unsigned short CHAR16;
typedef short INT16;
typedef unsigned char BOOLEAN;
typedef unsigned char UINT8;
typedef char CHAR8;
typedef char INT8;
#endif
///
/// Unsigned value of native width. (4 bytes on supported 32-bit processor instructions,
/// 8 bytes on supported 64-bit processor instructions)
///
typedef UINT32 UINTN;
typedef UINT32 UINTN;
///
/// Signed value of native width. (4 bytes on supported 32-bit processor instructions,
/// 8 bytes on supported 64-bit processor instructions)
///
typedef INT32 INTN;
//
// Processor specific defines
//
typedef INT32 INTN;
//
// Processor specific defines
//
///
/// A value of native width with the highest bit set.
///
#define MAX_BIT 0x80000000
#define MAX_BIT 0x80000000
///
/// A value of native width with the two highest bits set.
///
#define MAX_2_BITS 0xC0000000
///
/// Maximum legal ARM address
///
#define MAX_ADDRESS 0xFFFFFFFF
///
/// The stack alignment required for ARM
///
#define CPU_STACK_ALIGNMENT sizeof(UINT64)
//
// Modifier to ensure that all protocol member functions and EFI intrinsics
// use the correct C calling convention. All protocol member functions and
// EFI intrinsics are required to modify thier member functions with EFIAPI.
//
#define EFIAPI
#if defined(__GNUC__)
///
/// For GNU assembly code, .global or .globl can declare global symbols.
/// Define this macro to unify the usage.
///
#define ASM_GLOBAL .globl
#endif
#define MAX_2_BITS 0xC0000000
///
/// Maximum legal ARM address
///
#define MAX_ADDRESS 0xFFFFFFFF
///
/// The stack alignment required for ARM
///
#define CPU_STACK_ALIGNMENT sizeof(UINT64)
//
// Modifier to ensure that all protocol member functions and EFI intrinsics
// use the correct C calling convention. All protocol member functions and
// EFI intrinsics are required to modify thier member functions with EFIAPI.
//
#define EFIAPI
#if defined(__GNUC__)
///
/// For GNU assembly code, .global or .globl can declare global symbols.
/// Define this macro to unify the usage.
///
#define ASM_GLOBAL .globl
#endif
/**
Return the pointer to the first instruction of a function given a function pointer.
On ARM CPU architectures, these two pointer values are the same,
@ -123,6 +123,6 @@ typedef INT32 INTN;
@return The pointer to the first instruction of a function given a function pointer.
**/
#define FUNCTION_ENTRY_POINT(FunctionPointer) (FunctionPointer)
#endif
#define FUNCTION_ENTRY_POINT(FunctionPointer) (FunctionPointer)
#endif

42
MdePkg/Include/Library/BaseLib.h
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@ -3,7 +3,7 @@
functions, and CPU architecture-specific functions.
Copyright (c) 2006 - 2008, Intel Corporation<BR>
Portions Copyright (c) 2008-2009 Apple Inc.<BR>
Portions Copyright (c) 2008-2009 Apple Inc.<BR>
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@ -126,26 +126,26 @@ typedef struct {
#endif // defined (MDE_CPU_EBC)
#if defined (MDE_CPU_ARM)
typedef struct {
UINT32 R3; ///< Copy of R13
UINT32 R4;
UINT32 R5;
UINT32 R6;
UINT32 R7;
UINT32 R8;
UINT32 R9;
UINT32 R10;
UINT32 R11;
UINT32 R12;
UINT32 R14;
} BASE_LIBRARY_JUMP_BUFFER;
#define BASE_LIBRARY_JUMP_BUFFER_ALIGNMENT 4
#endif // defined (MDE_CPU_ARM)
#if defined (MDE_CPU_ARM)
typedef struct {
UINT32 R3; ///< Copy of R13
UINT32 R4;
UINT32 R5;
UINT32 R6;
UINT32 R7;
UINT32 R8;
UINT32 R9;
UINT32 R10;
UINT32 R11;
UINT32 R12;
UINT32 R14;
} BASE_LIBRARY_JUMP_BUFFER;
#define BASE_LIBRARY_JUMP_BUFFER_ALIGNMENT 4
#endif // defined (MDE_CPU_ARM)
//
// String Services
//

10
MdePkg/Include/Library/PeCoffLib.h
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@ -6,7 +6,7 @@
and can be ported easily to any environment.
Copyright (c) 2006 - 2008, Intel Corporation<BR>
Portions Copyright (c) 2008-2009 Apple Inc.<BR>
Portions Copyright (c) 2008-2009 Apple Inc.<BR>
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@ -192,10 +192,10 @@ typedef struct {
/// otherwise, the entry remains to be 0.
///
PHYSICAL_ADDRESS HiiResourceData;
///
/// Private storage for implementation specific data.
///
UINT64 Context;
///
/// Private storage for implementation specific data.
///
UINT64 Context;
} PE_COFF_LOADER_IMAGE_CONTEXT;
/**

106
MdePkg/Include/Protocol/DebugSupport.h
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@ -6,7 +6,7 @@
processor and handle context save and restore operations.
Copyright (c) 2006 - 2009, Intel Corporation<BR>
Portions Copyright (c) 2008-2009 Apple Inc.<BR>
Portions Copyright (c) 2008-2009 Apple Inc.<BR>
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@ -472,61 +472,61 @@ typedef struct {
UINT64 Ip;
} EFI_SYSTEM_CONTEXT_EBC;
///
/// ARM processor exception types
///
#define EXCEPT_ARM_RESET 0
#define EXCEPT_ARM_UNDEFINED_INSTRUCTION 1
#define EXCEPT_ARM_SOFTWARE_INTERRUPT 2
#define EXCEPT_ARM_PREFETCH_ABORT 3
#define EXCEPT_ARM_DATA_ABORT 4
#define EXCEPT_ARM_RESERVED 5
#define EXCEPT_ARM_IRQ 6
#define EXCEPT_ARM_FIQ 7
///
/// For coding convenience, define the maximum valid ARM exception.
///
#define MAX_ARM_EXCEPTION EXCEPT_ARM_FIQ
///
/// ARM processor context definition
///
typedef struct {
UINT32 R0;
UINT32 R1;
UINT32 R2;
UINT32 R3;
UINT32 R4;
UINT32 R5;
UINT32 R6;
UINT32 R7;
UINT32 R8;
UINT32 R9;
UINT32 R10;
UINT32 R11;
UINT32 R12;
UINT32 SP;
UINT32 LR;
UINT32 PC;
UINT32 CPSR;
UINT32 DFSR;
UINT32 DFAR;
UINT32 IFSR;
UINT32 IFAR;
} EFI_SYSTEM_CONTEXT_ARM;
///
/// Universal EFI_SYSTEM_CONTEXT definition
///
///
/// ARM processor exception types
///
#define EXCEPT_ARM_RESET 0
#define EXCEPT_ARM_UNDEFINED_INSTRUCTION 1
#define EXCEPT_ARM_SOFTWARE_INTERRUPT 2
#define EXCEPT_ARM_PREFETCH_ABORT 3
#define EXCEPT_ARM_DATA_ABORT 4
#define EXCEPT_ARM_RESERVED 5
#define EXCEPT_ARM_IRQ 6
#define EXCEPT_ARM_FIQ 7
///
/// For coding convenience, define the maximum valid ARM exception.
///
#define MAX_ARM_EXCEPTION EXCEPT_ARM_FIQ
///
/// ARM processor context definition
///
typedef struct {
UINT32 R0;
UINT32 R1;
UINT32 R2;
UINT32 R3;
UINT32 R4;
UINT32 R5;
UINT32 R6;
UINT32 R7;
UINT32 R8;
UINT32 R9;
UINT32 R10;
UINT32 R11;
UINT32 R12;
UINT32 SP;
UINT32 LR;
UINT32 PC;
UINT32 CPSR;
UINT32 DFSR;
UINT32 DFAR;
UINT32 IFSR;
UINT32 IFAR;
} EFI_SYSTEM_CONTEXT_ARM;
///
/// Universal EFI_SYSTEM_CONTEXT definition
///
typedef union {
EFI_SYSTEM_CONTEXT_EBC *SystemContextEbc;
EFI_SYSTEM_CONTEXT_IA32 *SystemContextIa32;
EFI_SYSTEM_CONTEXT_X64 *SystemContextX64;
EFI_SYSTEM_CONTEXT_IPF *SystemContextIpf;
EFI_SYSTEM_CONTEXT_ARM *SystemContextArm;
EFI_SYSTEM_CONTEXT_ARM *SystemContextArm;
} EFI_SYSTEM_CONTEXT;
//
@ -566,8 +566,8 @@ typedef enum {
IsaIa32 = IMAGE_FILE_MACHINE_I386, ///< 0x014C
IsaX64 = IMAGE_FILE_MACHINE_X64, ///< 0x8664
IsaIpf = IMAGE_FILE_MACHINE_IA64, ///< 0x0200
IsaEbc = IMAGE_FILE_MACHINE_EBC, ///< 0x0EBC
IsaArm = IMAGE_FILE_MACHINE_ARMTHUMB_MIXED ///< 0x01c2
IsaEbc = IMAGE_FILE_MACHINE_EBC, ///< 0x0EBC
IsaArm = IMAGE_FILE_MACHINE_ARMTHUMB_MIXED ///< 0x01c2
} EFI_INSTRUCTION_SET_ARCHITECTURE;

26
MdePkg/Include/Uefi/UefiBaseType.h
View File

@ -2,7 +2,7 @@
Defines data types and constants introduced in UEFI.
Copyright (c) 2006 - 2008, Intel Corporation<BR>
Portions Copyright (c) 2008-2009 Apple Inc.<BR>
Portions Copyright (c) 2008-2009 Apple Inc.<BR>
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@ -198,11 +198,11 @@ typedef union {
///
#define EFI_IMAGE_MACHINE_X64 0x8664
///
/// PE32+ Machine type for ARM mixed ARM and Thumb/Thumb2 images
///
#define EFI_IMAGE_MACHINE_ARMTHUMB_MIXED 0x01C2
///
/// PE32+ Machine type for ARM mixed ARM and Thumb/Thumb2 images
///
#define EFI_IMAGE_MACHINE_ARMTHUMB_MIXED 0x01C2
#if defined (MDE_CPU_IA32)
@ -225,13 +225,13 @@ typedef union {
#define EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) ((Machine) == EFI_IMAGE_MACHINE_IA32)
#elif defined (MDE_CPU_ARM)
#define EFI_IMAGE_MACHINE_TYPE_SUPPORTED(Machine) \
(((Machine) == EFI_IMAGE_MACHINE_ARMTHUMB_MIXED) || ((Machine) == EFI_IMAGE_MACHINE_EBC))
#define EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) ((Machine) == EFI_IMAGE_MACHINE_ARMTHUMB_MIXED)
#elif defined (MDE_CPU_ARM)
#define EFI_IMAGE_MACHINE_TYPE_SUPPORTED(Machine) \
(((Machine) == EFI_IMAGE_MACHINE_ARMTHUMB_MIXED) || ((Machine) == EFI_IMAGE_MACHINE_EBC))
#define EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) ((Machine) == EFI_IMAGE_MACHINE_ARMTHUMB_MIXED)
#elif defined (MDE_CPU_EBC)
///

8
MdePkg/Include/Uefi/UefiSpec.h
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@ -6,7 +6,7 @@
by this include file.
Copyright (c) 2006 - 2008, Intel Corporation<BR>
Portions Copyright (c) 2008-2009 Apple Inc.<BR>
Portions Copyright (c) 2008-2009 Apple Inc.<BR>
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@ -2061,7 +2061,7 @@ typedef struct {
#define EFI_REMOVABLE_MEDIA_FILE_NAME_IA32 L"\\EFI\\BOOT\\BOOTIA32.EFI"
#define EFI_REMOVABLE_MEDIA_FILE_NAME_IA64 L"\\EFI\\BOOT\\BOOTIA64.EFI"
#define EFI_REMOVABLE_MEDIA_FILE_NAME_X64 L"\\EFI\\BOOT\\BOOTX64.EFI"
#define EFI_REMOVABLE_MEDIA_FILE_NAME_ARM L"\\EFI\\BOOT\\BOOTARM.EFI"
#define EFI_REMOVABLE_MEDIA_FILE_NAME_ARM L"\\EFI\\BOOT\\BOOTARM.EFI"
#if defined (MDE_CPU_IA32)
#define EFI_REMOVABLE_MEDIA_FILE_NAME EFI_REMOVABLE_MEDIA_FILE_NAME_IA32
@ -2070,8 +2070,8 @@ typedef struct {
#elif defined (MDE_CPU_X64)
#define EFI_REMOVABLE_MEDIA_FILE_NAME EFI_REMOVABLE_MEDIA_FILE_NAME_X64
#elif defined (MDE_CPU_EBC)
#elif defined (MDE_CPU_ARM)
#define EFI_REMOVABLE_MEDIA_FILE_NAME EFI_REMOVABLE_MEDIA_FILE_NAME_ARM
#elif defined (MDE_CPU_ARM)
#define EFI_REMOVABLE_MEDIA_FILE_NAME EFI_REMOVABLE_MEDIA_FILE_NAME_ARM
#else
#error Unknown Processor Type
#endif

8
MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf
View File

@ -5,7 +5,7 @@
# This library assumes there are no chipset dependencies required to maintain caches.
#
# Copyright (c) 2007 - 2008, Intel Corporation<BR>
# Portions Copyright (c) 2008-2009 Apple Inc.<BR>
# Portions Copyright (c) 2008-2009 Apple Inc.<BR>
#
# All rights reserved. This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
@ -42,9 +42,9 @@
[Sources.EBC]
EbcCache.c
[Sources.ARM]
ArmCache.c
[Sources.ARM]
ArmCache.c
[Packages]
MdePkg/MdePkg.dec

72
MdePkg/Library/BaseCpuLib/Ia32/CpuFlushTlbGcc.c
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@ -1,36 +1,36 @@
/** @file
CpuFlushTlb function for Ia32/X64 GCC.
Copyright (c) 2006 - 2008, Intel Corporation<BR>
Portions copyright (c) 2008-2009 Apple Inc.<BR>
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
/**
Flushes all the Translation Lookaside Buffers(TLB) entries in a CPU.
Flushes all the Translation Lookaside Buffers(TLB) entries in a CPU.
**/
VOID
EFIAPI
CpuFlushTlb (
VOID
)
{
__asm__ __volatile__ (
"movl %%cr3, %0\n\t"
"movl %0, %%cr3 "
: "r" // %0
);
}
/** @file
CpuFlushTlb function for Ia32/X64 GCC.
Copyright (c) 2006 - 2008, Intel Corporation<BR>
Portions copyright (c) 2008-2009 Apple Inc.<BR>
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
/**
Flushes all the Translation Lookaside Buffers(TLB) entries in a CPU.
Flushes all the Translation Lookaside Buffers(TLB) entries in a CPU.
**/
VOID
EFIAPI
CpuFlushTlb (
VOID
)
{
__asm__ __volatile__ (
"movl %%cr3, %0\n\t"
"movl %0, %%cr3 "
: "r" // %0
);
}

66
MdePkg/Library/BaseCpuLib/Ia32/CpuSleepGcc.c
View File

@ -1,33 +1,33 @@
/** @file
CpuSleep function for Ia32/X64 GCC.
Copyright (c) 2006 - 2008, Intel Corporation<BR>
Portions copyright (c) 2008-2009 Apple Inc.<BR>
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
/**
Places the CPU in a sleep state until an interrupt is received.
Places the CPU in a sleep state until an interrupt is received. If interrupts
are disabled prior to calling this function, then the CPU will be placed in a
sleep state indefinitely.
**/
VOID
EFIAPI
CpuSleep (
VOID
)
{
__asm__ __volatile__ ("hlt"::: "memory");
}
/** @file
CpuSleep function for Ia32/X64 GCC.
Copyright (c) 2006 - 2008, Intel Corporation<BR>
Portions copyright (c) 2008-2009 Apple Inc.<BR>
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
/**
Places the CPU in a sleep state until an interrupt is received.
Places the CPU in a sleep state until an interrupt is received. If interrupts
are disabled prior to calling this function, then the CPU will be placed in a
sleep state indefinitely.
**/
VOID
EFIAPI
CpuSleep (
VOID
)
{
__asm__ __volatile__ ("hlt"::: "memory");
}

860
MdePkg/Library/BaseIoLibIntrinsic/IoLibArm.c
View File

@ -1,430 +1,430 @@
/** @file
I/O Library for ARM.
Copyright (c) 2006 - 2009, Intel Corporation<BR>
Portions copyright (c) 2008-2009 Apple Inc.<BR>
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
//
// Include common header file for this module.
//
#include "BaseIoLibIntrinsicInternal.h"
/**
Reads an 8-bit I/O port.
Reads the 8-bit I/O port specified by Port. The 8-bit read value is returned.
This function must guarantee that all I/O read and write operations are
serialized.
If 8-bit I/O port operations are not supported, then ASSERT().
@param Port The I/O port to read.
@return The value read.
**/
UINT8
EFIAPI
IoRead8 (
IN UINTN Port
)
{
ASSERT (FALSE);
return 0;
}
/**
Writes an 8-bit I/O port.
Writes the 8-bit I/O port specified by Port with the value specified by Value
and returns Value. This function must guarantee that all I/O read and write
operations are serialized.
If 8-bit I/O port operations are not supported, then ASSERT().
@param Port The I/O port to write.
@param Value The value to write to the I/O port.
@return The value written the I/O port.
**/
UINT8
EFIAPI
IoWrite8 (
IN UINTN Port,
IN UINT8 Value
)
{
ASSERT (FALSE);
return Value;
}
/**
Reads a 16-bit I/O port.
Reads the 16-bit I/O port specified by Port. The 16-bit read value is returned.
This function must guarantee that all I/O read and write operations are
serialized.
If 16-bit I/O port operations are not supported, then ASSERT().
@param Port The I/O port to read.
@return The value read.
**/
UINT16
EFIAPI
IoRead16 (
IN UINTN Port
)
{
ASSERT (FALSE);
return 0;
}
/**
Writes a 16-bit I/O port.
Writes the 16-bit I/O port specified by Port with the value specified by Value
and returns Value. This function must guarantee that all I/O read and write
operations are serialized.
If 16-bit I/O port operations are not supported, then ASSERT().
@param Port The I/O port to write.
@param Value The value to write to the I/O port.
@return The value written the I/O port.
**/
UINT16
EFIAPI
IoWrite16 (
IN UINTN Port,
IN UINT16 Value
)
{
ASSERT (FALSE);
return Value;
}
/**
Reads a 32-bit I/O port.
Reads the 32-bit I/O port specified by Port. The 32-bit read value is returned.
This function must guarantee that all I/O read and write operations are
serialized.
If 32-bit I/O port operations are not supported, then ASSERT().
@param Port The I/O port to read.
@return The value read.
**/
UINT32
EFIAPI
IoRead32 (
IN UINTN Port
)
{
ASSERT (FALSE);
return 0;
}
/**
Writes a 32-bit I/O port.
Writes the 32-bit I/O port specified by Port with the value specified by Value
and returns Value. This function must guarantee that all I/O read and write
operations are serialized.
If 32-bit I/O port operations are not supported, then ASSERT().
@param Port The I/O port to write.
@param Value The value to write to the I/O port.
@return The value written the I/O port.
**/
UINT32
EFIAPI
IoWrite32 (
IN UINTN Port,
IN UINT32 Value
)
{
ASSERT (FALSE);
return Value;
}
/**
Reads a 64-bit I/O port.
Reads the 64-bit I/O port specified by Port. The 64-bit read value is returned.
This function must guarantee that all I/O read and write operations are
serialized.
If 64-bit I/O port operations are not supported, then ASSERT().
If Port is not aligned on a 64-bit boundary, then ASSERT().
@param Port The I/O port to read.
@return The value read.
**/
UINT64
EFIAPI
IoRead64 (
IN UINTN Port
)
{
ASSERT (FALSE);
return 0;
}
/**
Writes a 64-bit I/O port.
Writes the 64-bit I/O port specified by Port with the value specified by Value
and returns Value. This function must guarantee that all I/O read and write
operations are serialized.
If 64-bit I/O port operations are not supported, then ASSERT().
If Port is not aligned on a 64-bit boundary, then ASSERT().
@param Port The I/O port to write.
@param Value The value to write to the I/O port.
@return The value written the I/O port.
**/
UINT64
EFIAPI
IoWrite64 (
IN UINTN Port,
IN UINT64 Value
)
{
ASSERT (FALSE);
return 0;
}
/**
Reads an 8-bit MMIO register.
Reads the 8-bit MMIO register specified by Address. The 8-bit read value is
returned. This function must guarantee that all MMIO read and write
operations are serialized.
If 8-bit MMIO register operations are not supported, then ASSERT().
@param Address The MMIO register to read.
@return The value read.
**/
UINT8
EFIAPI
MmioRead8 (
IN UINTN Address
)
{
UINT8 Value;
Value = *(volatile UINT8*)Address;
return Value;
}
/**
Writes an 8-bit MMIO register.
Writes the 8-bit MMIO register specified by Address with the value specified
by Value and returns Value. This function must guarantee that all MMIO read
and write operations are serialized.
If 8-bit MMIO register operations are not supported, then ASSERT().
@param Address The MMIO register to write.
@param Value The value to write to the MMIO register.
**/
UINT8
EFIAPI
MmioWrite8 (
IN UINTN Address,
IN UINT8 Value
)
{
*(volatile UINT8*)Address = Value;
return Value;
}
/**
Reads a 16-bit MMIO register.
Reads the 16-bit MMIO register specified by Address. The 16-bit read value is
returned. This function must guarantee that all MMIO read and write
operations are serialized.
If 16-bit MMIO register operations are not supported, then ASSERT().
@param Address The MMIO register to read.
@return The value read.
**/
UINT16
EFIAPI
MmioRead16 (
IN UINTN Address
)
{
UINT16 Value;
ASSERT ((Address & 1) == 0);
Value = *(volatile UINT16*)Address;
return Value;
}
/**
Writes a 16-bit MMIO register.
Writes the 16-bit MMIO register specified by Address with the value specified
by Value and returns Value. This function must guarantee that all MMIO read
and write operations are serialized.
If 16-bit MMIO register operations are not supported, then ASSERT().
@param Address The MMIO register to write.
@param Value The value to write to the MMIO register.
**/
UINT16
EFIAPI
MmioWrite16 (
IN UINTN Address,
IN UINT16 Value
)
{
ASSERT ((Address & 1) == 0);
*(volatile UINT16*)Address = Value;
return Value;
}
/**
Reads a 32-bit MMIO register.
Reads the 32-bit MMIO register specified by Address. The 32-bit read value is
returned. This function must guarantee that all MMIO read and write
operations are serialized.
If 32-bit MMIO register operations are not supported, then ASSERT().
@param Address The MMIO register to read.
@return The value read.
**/
UINT32
EFIAPI
MmioRead32 (
IN UINTN Address
)
{
UINT32 Value;
ASSERT ((Address & 3) == 0);
Value = *(volatile UINT32*)Address;
return Value;
}
/**
Writes a 32-bit MMIO register.
Writes the 32-bit MMIO register specified by Address with the value specified
by Value and returns Value. This function must guarantee that all MMIO read
and write operations are serialized.
If 32-bit MMIO register operations are not supported, then ASSERT().
@param Address The MMIO register to write.
@param Value The value to write to the MMIO register.
**/
UINT32
EFIAPI
MmioWrite32 (
IN UINTN Address,
IN UINT32 Value
)
{
ASSERT ((Address & 3) == 0);
*(volatile UINT32*)Address = Value;
return Value;
}
/**
Reads a 64-bit MMIO register.
Reads the 64-bit MMIO register specified by Address. The 64-bit read value is
returned. This function must guarantee that all MMIO read and write
operations are serialized.
If 64-bit MMIO register operations are not supported, then ASSERT().
@param Address The MMIO register to read.
@return The value read.
**/
UINT64
EFIAPI
MmioRead64 (
IN UINTN Address
)
{
UINT64 Value;
ASSERT ((Address & 7) == 0);
Value = *(volatile UINT64*)Address;
return Value;
}
/**
Writes a 64-bit MMIO register.
Writes the 64-bit MMIO register specified by Address with the value specified
by Value and returns Value. This function must guarantee that all MMIO read
and write operations are serialized.
If 64-bit MMIO register operations are not supported, then ASSERT().
@param Address The MMIO register to write.
@param Value The value to write to the MMIO register.
**/
UINT64
EFIAPI
MmioWrite64 (
IN UINTN Address,
IN UINT64 Value
)
{
ASSERT ((Address & 7) == 0);
*(volatile UINT64*)Address = Value;
return Value;
}
/** @file
I/O Library for ARM.
Copyright (c) 2006 - 2009, Intel Corporation<BR>
Portions copyright (c) 2008-2009 Apple Inc.<BR>
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
//
// Include common header file for this module.
//
#include "BaseIoLibIntrinsicInternal.h"
/**
Reads an 8-bit I/O port.
Reads the 8-bit I/O port specified by Port. The 8-bit read value is returned.
This function must guarantee that all I/O read and write operations are
serialized.
If 8-bit I/O port operations are not supported, then ASSERT().
@param Port The I/O port to read.
@return The value read.
**/
UINT8
EFIAPI
IoRead8 (
IN UINTN Port
)
{
ASSERT (FALSE);
return 0;
}
/**
Writes an 8-bit I/O port.
Writes the 8-bit I/O port specified by Port with the value specified by Value
and returns Value. This function must guarantee that all I/O read and write
operations are serialized.
If 8-bit I/O port operations are not supported, then ASSERT().
@param Port The I/O port to write.
@param Value The value to write to the I/O port.
@return The value written the I/O port.
**/
UINT8
EFIAPI
IoWrite8 (
IN UINTN Port,
IN UINT8 Value
)
{
ASSERT (FALSE);
return Value;
}
/**
Reads a 16-bit I/O port.
Reads the 16-bit I/O port specified by Port. The 16-bit read value is returned.
This function must guarantee that all I/O read and write operations are
serialized.
If 16-bit I/O port operations are not supported, then ASSERT().
@param Port The I/O port to read.
@return The value read.
**/
UINT16
EFIAPI
IoRead16 (
IN UINTN Port
)
{
ASSERT (FALSE);
return 0;
}
/**
Writes a 16-bit I/O port.
Writes the 16-bit I/O port specified by Port with the value specified by Value
and returns Value. This function must guarantee that all I/O read and write
operations are serialized.
If 16-bit I/O port operations are not supported, then ASSERT().
@param Port The I/O port to write.
@param Value The value to write to the I/O port.
@return The value written the I/O port.
**/
UINT16
EFIAPI
IoWrite16 (
IN UINTN Port,
IN UINT16 Value
)
{
ASSERT (FALSE);
return Value;
}
/**
Reads a 32-bit I/O port.
Reads the 32-bit I/O port specified by Port. The 32-bit read value is returned.
This function must guarantee that all I/O read and write operations are
serialized.
If 32-bit I/O port operations are not supported, then ASSERT().
@param Port The I/O port to read.
@return The value read.
**/
UINT32
EFIAPI
IoRead32 (
IN UINTN Port
)
{
ASSERT (FALSE);
return 0;
}
/**
Writes a 32-bit I/O port.
Writes the 32-bit I/O port specified by Port with the value specified by Value
and returns Value. This function must guarantee that all I/O read and write
operations are serialized.
If 32-bit I/O port operations are not supported, then ASSERT().
@param Port The I/O port to write.
@param Value The value to write to the I/O port.
@return The value written the I/O port.
**/
UINT32
EFIAPI
IoWrite32 (
IN UINTN Port,
IN UINT32 Value
)
{
ASSERT (FALSE);
return Value;
}
/**
Reads a 64-bit I/O port.
Reads the 64-bit I/O port specified by Port. The 64-bit read value is returned.
This function must guarantee that all I/O read and write operations are
serialized.
If 64-bit I/O port operations are not supported, then ASSERT().
If Port is not aligned on a 64-bit boundary, then ASSERT().
@param Port The I/O port to read.
@return The value read.
**/
UINT64
EFIAPI
IoRead64 (
IN UINTN Port
)
{
ASSERT (FALSE);
return 0;
}
/**
Writes a 64-bit I/O port.
Writes the 64-bit I/O port specified by Port with the value specified by Value
and returns Value. This function must guarantee that all I/O read and write
operations are serialized.
If 64-bit I/O port operations are not supported, then ASSERT().
If Port is not aligned on a 64-bit boundary, then ASSERT().
@param Port The I/O port to write.
@param Value The value to write to the I/O port.
@return The value written the I/O port.
**/
UINT64
EFIAPI
IoWrite64 (
IN UINTN Port,
IN UINT64 Value
)
{
ASSERT (FALSE);
return 0;
}
/**
Reads an 8-bit MMIO register.
Reads the 8-bit MMIO register specified by Address. The 8-bit read value is
returned. This function must guarantee that all MMIO read and write
operations are serialized.
If 8-bit MMIO register operations are not supported, then ASSERT().
@param Address The MMIO register to read.
@return The value read.
**/
UINT8
EFIAPI
MmioRead8 (
IN UINTN Address
)
{
UINT8 Value;
Value = *(volatile UINT8*)Address;
return Value;
}
/**
Writes an 8-bit MMIO register.
Writes the 8-bit MMIO register specified by Address with the value specified
by Value and returns Value. This function must guarantee that all MMIO read
and write operations are serialized.
If 8-bit MMIO register operations are not supported, then ASSERT().
@param Address The MMIO register to write.
@param Value The value to write to the MMIO register.
**/
UINT8
EFIAPI
MmioWrite8 (
IN UINTN Address,
IN UINT8 Value
)
{
*(volatile UINT8*)Address = Value;
return Value;
}
/**
Reads a 16-bit MMIO register.
Reads the 16-bit MMIO register specified by Address. The 16-bit read value is
returned. This function must guarantee that all MMIO read and write
operations are serialized.
If 16-bit MMIO register operations are not supported, then ASSERT().
@param Address The MMIO register to read.
@return The value read.
**/
UINT16
EFIAPI
MmioRead16 (
IN UINTN Address
)
{
UINT16 Value;
ASSERT ((Address & 1) == 0);
Value = *(volatile UINT16*)Address;
return Value;
}
/**
Writes a 16-bit MMIO register.
Writes the 16-bit MMIO register specified by Address with the value specified
by Value and returns Value. This function must guarantee that all MMIO read
and write operations are serialized.
If 16-bit MMIO register operations are not supported, then ASSERT().
@param Address The MMIO register to write.
@param Value The value to write to the MMIO register.
**/
UINT16
EFIAPI
MmioWrite16 (
IN UINTN Address,
IN UINT16 Value
)
{
ASSERT ((Address & 1) == 0);
*(volatile UINT16*)Address = Value;
return Value;
}
/**
Reads a 32-bit MMIO register.
Reads the 32-bit MMIO register specified by Address. The 32-bit read value is
returned. This function must guarantee that all MMIO read and write
operations are serialized.
If 32-bit MMIO register operations are not supported, then ASSERT().
@param Address The MMIO register to read.
@return The value read.
**/
UINT32
EFIAPI
MmioRead32 (
IN UINTN Address
)
{
UINT32 Value;
ASSERT ((Address & 3) == 0);
Value = *(volatile UINT32*)Address;
return Value;
}
/**
Writes a 32-bit MMIO register.
Writes the 32-bit MMIO register specified by Address with the value specified
by Value and returns Value. This function must guarantee that all MMIO read
and write operations are serialized.
If 32-bit MMIO register operations are not supported, then ASSERT().
@param Address The MMIO register to write.
@param Value The value to write to the MMIO register.
**/
UINT32
EFIAPI
MmioWrite32 (
IN UINTN Address,
IN UINT32 Value
)
{
ASSERT ((Address & 3) == 0);
*(volatile UINT32*)Address = Value;
return Value;
}
/**
Reads a 64-bit MMIO register.
Reads the 64-bit MMIO register specified by Address. The 64-bit read value is
returned. This function must guarantee that all MMIO read and write
operations are serialized.
If 64-bit MMIO register operations are not supported, then ASSERT().
@param Address The MMIO register to read.
@return The value read.
**/
UINT64
EFIAPI
MmioRead64 (
IN UINTN Address
)
{
UINT64 Value;
ASSERT ((Address & 7) == 0);
Value = *(volatile UINT64*)Address;
return Value;
}
/**
Writes a 64-bit MMIO register.
Writes the 64-bit MMIO register specified by Address with the value specified
by Value and returns Value. This function must guarantee that all MMIO read
and write operations are serialized.
If 64-bit MMIO register operations are not supported, then ASSERT().
@param Address The MMIO register to write.
@param Value The value to write to the MMIO register.
**/
UINT64
EFIAPI
MmioWrite64 (
IN UINTN Address,
IN UINT64 Value
)
{
ASSERT ((Address & 7) == 0);
*(volatile UINT64*)Address = Value;
return Value;
}

72
MdePkg/Library/BaseLib/Arm/CpuBreakpoint.S
View File

@ -1,36 +1,36 @@
#------------------------------------------------------------------------------
#
# CpuBreakpoint() for ARM
#
# Copyright (c) 2006 - 2009, Intel Corporation<BR>
# Portions copyright (c) 2008-2009 Apple Inc.<BR>
# All rights reserved. This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#------------------------------------------------------------------------------
.text
.align 2
.globl ASM_PFX(CpuBreakpoint)
#/**
# Generates a breakpoint on the CPU.
#
# Generates a breakpoint on the CPU. The breakpoint must be implemented such
# that code can resume normal execution after the breakpoint.
#
#**/
#VOID
#EFIAPI
#CpuBreakpoint (
# VOID
# );
#
ASM_PFX(CpuBreakpoint):
swi 0xdbdbdb
bx lr
#------------------------------------------------------------------------------
#
# CpuBreakpoint() for ARM
#
# Copyright (c) 2006 - 2009, Intel Corporation<BR>
# Portions copyright (c) 2008-2009 Apple Inc.<BR>
# All rights reserved. This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#------------------------------------------------------------------------------
.text
.align 2
.globl ASM_PFX(CpuBreakpoint)
#/**
# Generates a breakpoint on the CPU.
#
# Generates a breakpoint on the CPU. The breakpoint must be implemented such
# that code can resume normal execution after the breakpoint.
#
#**/
#VOID
#EFIAPI
#CpuBreakpoint (
# VOID
# );
#
ASM_PFX(CpuBreakpoint):
swi 0xdbdbdb
bx lr

76
MdePkg/Library/BaseLib/Arm/CpuBreakpoint.asm
View File

@ -1,38 +1,38 @@
;------------------------------------------------------------------------------
;
; CpuBreakpoint() for ARM
;
; Copyright (c) 2006 - 2009, Intel Corporation<BR>
; Portions copyright (c) 2008-2009 Apple Inc.<BR>
; All rights reserved. This program and the accompanying materials
; are licensed and made available under the terms and conditions of the BSD License
; which accompanies this distribution. The full text of the license may be found at
; http://opensource.org/licenses/bsd-license.php
;
; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
;
;------------------------------------------------------------------------------
EXPORT CpuBreakpoint
AREA Cpu_Breakpoint, CODE, READONLY
;/**
; Generates a breakpoint on the CPU.
;
; Generates a breakpoint on the CPU. The breakpoint must be implemented such
; that code can resume normal execution after the breakpoint.
;
;**/
;VOID
;EFIAPI
;CpuBreakpoint (
; VOID
; );
;
CpuBreakpoint
swi 0xdbdbdb
bx lr
END
;------------------------------------------------------------------------------
;
; CpuBreakpoint() for ARM
;
; Copyright (c) 2006 - 2009, Intel Corporation<BR>
; Portions copyright (c) 2008-2009 Apple Inc.<BR>
; All rights reserved. This program and the accompanying materials
; are licensed and made available under the terms and conditions of the BSD License
; which accompanies this distribution. The full text of the license may be found at
; http://opensource.org/licenses/bsd-license.php
;
; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
;
;------------------------------------------------------------------------------
EXPORT CpuBreakpoint
AREA Cpu_Breakpoint, CODE, READONLY
;/**
; Generates a breakpoint on the CPU.
;
; Generates a breakpoint on the CPU. The breakpoint must be implemented such
; that code can resume normal execution after the breakpoint.
;
;**/
;VOID
;EFIAPI
;CpuBreakpoint (
; VOID
; );
;
CpuBreakpoint
swi 0xdbdbdb
bx lr
END

82
MdePkg/Library/BaseLib/Arm/CpuPause.asm
View File

@ -1,41 +1,41 @@
;------------------------------------------------------------------------------
;
; CpuPause() for ARM
;
; Copyright (c) 2006 - 2009, Intel Corporation<BR>
; Portions copyright (c) 2008-2009 Apple Inc.<BR>
; All rights reserved. This program and the accompanying materials
; are licensed and made available under the terms and conditions of the BSD License
; which accompanies this distribution. The full text of the license may be found at
; http://opensource.org/licenses/bsd-license.php
;
; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
;
;------------------------------------------------------------------------------
EXPORT CpuPause
AREA cpu_pause, CODE, READONLY
;/**
; Requests CPU to pause for a short period of time.
;
; Requests CPU to pause for a short period of time. Typically used in MP
; systems to prevent memory starvation while waiting for a spin lock.
;
;**/
;VOID
;EFIAPI
;CpuPause (
; VOID
; );
;
CpuPause
NOP
NOP
NOP
NOP
NOP
BX LR
END
;------------------------------------------------------------------------------
;
; CpuPause() for ARM
;
; Copyright (c) 2006 - 2009, Intel Corporation<BR>
; Portions copyright (c) 2008-2009 Apple Inc.<BR>
; All rights reserved. This program and the accompanying materials
; are licensed and made available under the terms and conditions of the BSD License
; which accompanies this distribution. The full text of the license may be found at
; http://opensource.org/licenses/bsd-license.php
;
; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
;
;------------------------------------------------------------------------------
EXPORT CpuPause
AREA cpu_pause, CODE, READONLY
;/**
; Requests CPU to pause for a short period of time.
;
; Requests CPU to pause for a short period of time. Typically used in MP
; systems to prevent memory starvation while waiting for a spin lock.
;
;**/
;VOID
;EFIAPI
;CpuPause (
; VOID
; );
;
CpuPause
NOP
NOP
NOP
NOP
NOP
BX LR
END

70
MdePkg/Library/BaseLib/Arm/DisableInterrupts.S
View File

@ -1,35 +1,35 @@
#------------------------------------------------------------------------------
#
# DisableInterrupts() for ARM
#
# Copyright (c) 2006 - 2009, Intel Corporation<BR>
# Portions copyright (c) 2008-2009 Apple Inc.<BR>
# All rights reserved. This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#------------------------------------------------------------------------------
.text
.p2align 2
.globl ASM_PFX(DisableInterrupts)
#/**
# Disables CPU interrupts.
#
#**/
#VOID
#EFIAPI
#DisableInterrupts (
# VOID
# );
#
ASM_PFX(DisableInterrupts):
mrs R0,CPSR
orr R0,R0,#0x80 @Disable IRQ interrupts
msr CPSR_c,R0
bx LR
#------------------------------------------------------------------------------
#
# DisableInterrupts() for ARM
#
# Copyright (c) 2006 - 2009, Intel Corporation<BR>
# Portions copyright (c) 2008-2009 Apple Inc.<BR>
# All rights reserved. This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#------------------------------------------------------------------------------
.text
.p2align 2
.globl ASM_PFX(DisableInterrupts)
#/**
# Disables CPU interrupts.
#
#**/
#VOID
#EFIAPI
#DisableInterrupts (
# VOID
# );
#
ASM_PFX(DisableInterrupts):
mrs R0,CPSR
orr R0,R0,#0x80 @Disable IRQ interrupts
msr CPSR_c,R0
bx LR

74
MdePkg/Library/BaseLib/Arm/DisableInterrupts.asm
View File

@ -1,37 +1,37 @@
;------------------------------------------------------------------------------
;
; DisableInterrupts() for ARM
;
; Copyright (c) 2006 - 2009, Intel Corporation<BR>
; Portions copyright (c) 2008-2009 Apple Inc.<BR>
; All rights reserved. This program and the accompanying materials
; are licensed and made available under the terms and conditions of the BSD License
; which accompanies this distribution. The full text of the license may be found at
; http://opensource.org/licenses/bsd-license.php
;
; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
;
;------------------------------------------------------------------------------
EXPORT DisableInterrupts
AREA Interrupt_disable, CODE, READONLY
;/**
; Disables CPU interrupts.
;
;**/
;VOID
;EFIAPI
;DisableInterrupts (
; VOID
; );
;
DisableInterrupts
MRS R0,CPSR
ORR R0,R0,#0x80 ;Disable IRQ interrupts
MSR CPSR_c,R0
BX LR
END
;------------------------------------------------------------------------------
;
; DisableInterrupts() for ARM
;
; Copyright (c) 2006 - 2009, Intel Corporation<BR>
; Portions copyright (c) 2008-2009 Apple Inc.<BR>
; All rights reserved. This program and the accompanying materials
; are licensed and made available under the terms and conditions of the BSD License
; which accompanies this distribution. The full text of the license may be found at
; http://opensource.org/licenses/bsd-license.php
;
; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
;
;------------------------------------------------------------------------------
EXPORT DisableInterrupts
AREA Interrupt_disable, CODE, READONLY
;/**
; Disables CPU interrupts.
;
;**/
;VOID
;EFIAPI
;DisableInterrupts (
; VOID
; );
;
DisableInterrupts
MRS R0,CPSR
ORR R0,R0,#0x80 ;Disable IRQ interrupts
MSR CPSR_c,R0
BX LR
END

72
MdePkg/Library/BaseLib/Arm/EnableInterrupts.S
View File

@ -1,36 +1,36 @@
#------------------------------------------------------------------------------
#
# EnableInterrupts() for ARM
#
# Copyright (c) 2006 - 2009, Intel Corporation<BR>
# Portions copyright (c) 2008-2009 Apple Inc.<BR>
# All rights reserved. This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#------------------------------------------------------------------------------
.text
.p2align 2
.globl ASM_PFX(EnableInterrupts)
#/**
# Enables CPU interrupts.
#
#**/
#VOID
#EFIAPI
#EnableInterrupts (
# VOID
# );
#
ASM_PFX(EnableInterrupts):
mrs R0,CPSR
bic R0,R0,#0x80 @Enable IRQ interrupts
msr CPSR_c,R0
bx LR
#------------------------------------------------------------------------------
#
# EnableInterrupts() for ARM
#
# Copyright (c) 2006 - 2009, Intel Corporation<BR>
# Portions copyright (c) 2008-2009 Apple Inc.<BR>
# All rights reserved. This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#------------------------------------------------------------------------------
.text
.p2align 2
.globl ASM_PFX(EnableInterrupts)
#/**
# Enables CPU interrupts.
#
#**/
#VOID
#EFIAPI
#EnableInterrupts (
# VOID
# );
#
ASM_PFX(EnableInterrupts):
mrs R0,CPSR
bic R0,R0,#0x80 @Enable IRQ interrupts
msr CPSR_c,R0
bx LR

74
MdePkg/Library/BaseLib/Arm/EnableInterrupts.asm
View File

@ -1,37 +1,37 @@
;------------------------------------------------------------------------------
;
; EnableInterrupts() for ARM
;
; Copyright (c) 2006 - 2009, Intel Corporation<BR>
; Portions copyright (c) 2008-2009 Apple Inc.<BR>
; All rights reserved. This program and the accompanying materials
; are licensed and made available under the terms and conditions of the BSD License
; which accompanies this distribution. The full text of the license may be found at
; http://opensource.org/licenses/bsd-license.php
;
; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
;
;------------------------------------------------------------------------------
EXPORT EnableInterrupts
AREA Interrupt_enable, CODE, READONLY
;/**
; Enables CPU interrupts.
;
;**/
;VOID
;EFIAPI
;EnableInterrupts (
; VOID
; );
;
EnableInterrupts
MRS R0,CPSR
BIC R0,R0,#0x80 ;Enable IRQ interrupts
MSR CPSR_c,R0
BX LR
END
;------------------------------------------------------------------------------
;
; EnableInterrupts() for ARM
;
; Copyright (c) 2006 - 2009, Intel Corporation<BR>
; Portions copyright (c) 2008-2009 Apple Inc.<BR>
; All rights reserved. This program and the accompanying materials
; are licensed and made available under the terms and conditions of the BSD License
; which accompanies this distribution. The full text of the license may be found at
; http://opensource.org/licenses/bsd-license.php
;
; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
;
;------------------------------------------------------------------------------
EXPORT EnableInterrupts
AREA Interrupt_enable, CODE, READONLY
;/**
; Enables CPU interrupts.
;
;**/
;VOID
;EFIAPI
;EnableInterrupts (
; VOID
; );
;
EnableInterrupts
MRS R0,CPSR
BIC R0,R0,#0x80 ;Enable IRQ interrupts
MSR CPSR_c,R0
BX LR
END

122
MdePkg/Library/BaseLib/Arm/GccInline.c
View File

@ -1,61 +1,61 @@
/** @file
GCC inline implementation of BaseLib processor specific functions.
Copyright (c) 2006 - 2007, Intel Corporation<BR>
Portions copyright (c) 2008-2009 Apple Inc.<BR>
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include "BaseLibInternals.h"
/**
Requests CPU to pause for a short period of time.
Requests CPU to pause for a short period of time. Typically used in MP
systems to prevent memory starvation while waiting for a spin lock.
**/
VOID
EFIAPI
CpuPause (
VOID
)
{
__asm__ __volatile__ (
"nop\n\t"
"nop\n\t"
"nop\n\t"
"nop\n\t"
"nop\n\t"
);
}
VOID
EFIAPI
InternalSwitchStackAsm (
SWITCH_STACK_ENTRY_POINT EntryPoint,
VOID *Context,
VOID *Context2,
VOID *NewStack
)
{
__asm__ __volatile__ (
"mov lr, %0\n\t"
"mov sp, %3\n\t"
"mov %r0, %1\n\t"
"mov %r1, %2\n\t"
"bx lr\n\t"
: /* no output operand */
: "r" (EntryPoint),
"r" (Context),
"r" (Context2),
"r" (NewStack)
);
}
/** @file
GCC inline implementation of BaseLib processor specific functions.
Copyright (c) 2006 - 2007, Intel Corporation<BR>
Portions copyright (c) 2008-2009 Apple Inc.<BR>
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include "BaseLibInternals.h"
/**
Requests CPU to pause for a short period of time.
Requests CPU to pause for a short period of time. Typically used in MP
systems to prevent memory starvation while waiting for a spin lock.
**/
VOID
EFIAPI
CpuPause (
VOID
)
{
__asm__ __volatile__ (
"nop\n\t"
"nop\n\t"
"nop\n\t"
"nop\n\t"
"nop\n\t"
);
}
VOID
EFIAPI
InternalSwitchStackAsm (
SWITCH_STACK_ENTRY_POINT EntryPoint,
VOID *Context,
VOID *Context2,
VOID *NewStack
)
{
__asm__ __volatile__ (
"mov lr, %0\n\t"
"mov sp, %3\n\t"
"mov %r0, %1\n\t"
"mov %r1, %2\n\t"
"bx lr\n\t"
: /* no output operand */
: "r" (EntryPoint),
"r" (Context),
"r" (Context2),
"r" (NewStack)
);
}

86
MdePkg/Library/BaseLib/Arm/GetInterruptsState.S
View File

@ -1,43 +1,43 @@
#------------------------------------------------------------------------------
#
# GetInterruptState() function for ARM
#
# Copyright (c) 2006 - 2009, Intel Corporation<BR>
# Portions copyright (c) 2008-2009 Apple Inc.<BR>
# All rights reserved. This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#------------------------------------------------------------------------------
.text
.p2align 2
.globl _GetInterruptState
#/**
# Retrieves the current CPU interrupt state.
#
# Returns TRUE is interrupts are currently enabled. Otherwise
# returns FALSE.
#
# @retval TRUE CPU interrupts are enabled.
# @retval FALSE CPU interrupts are disabled.
#
#**/
#
#BOOLEAN
#EFIAPI
#GetInterruptState (
# VOID
# );
#
_GetInterruptState:
mrs R0, CPSR
tst R0, #0x80 @Check if IRQ is enabled.
moveq R0, #1
movne R0, #0
bx LR
#------------------------------------------------------------------------------
#
# GetInterruptState() function for ARM
#
# Copyright (c) 2006 - 2009, Intel Corporation<BR>
# Portions copyright (c) 2008-2009 Apple Inc.<BR>
# All rights reserved. This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#------------------------------------------------------------------------------
.text
.p2align 2
.globl _GetInterruptState
#/**
# Retrieves the current CPU interrupt state.
#
# Returns TRUE is interrupts are currently enabled. Otherwise
# returns FALSE.
#
# @retval TRUE CPU interrupts are enabled.
# @retval FALSE CPU interrupts are disabled.
#
#**/
#
#BOOLEAN
#EFIAPI
#GetInterruptState (
# VOID
# );
#
_GetInterruptState:
mrs R0, CPSR
tst R0, #0x80 @Check if IRQ is enabled.
moveq R0, #1
movne R0, #0
bx LR

90
MdePkg/Library/BaseLib/Arm/GetInterruptsState.asm
View File

@ -1,45 +1,45 @@
;------------------------------------------------------------------------------
;
; GetInterruptState() function for ARM
;
; Copyright (c) 2006 - 2009, Intel Corporation<BR>
; Portions copyright (c) 2008-2009 Apple Inc.<BR>
; All rights reserved. This program and the accompanying materials
; are licensed and made available under the terms and conditions of the BSD License
; which accompanies this distribution. The full text of the license may be found at
; http://opensource.org/licenses/bsd-license.php
;
; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
;
;------------------------------------------------------------------------------
EXPORT GetInterruptState
AREA Interrupt_enable, CODE, READONLY
;/**
; Retrieves the current CPU interrupt state.
;
; Returns TRUE is interrupts are currently enabled. Otherwise
; returns FALSE.
;
; @retval TRUE CPU interrupts are enabled.
; @retval FALSE CPU interrupts are disabled.
;
;**/
;
;BOOLEAN
;EFIAPI
;GetInterruptState (
; VOID
; );
;
GetInterruptState
MRS R0, CPSR
TST R0, #0x80 ;Check if IRQ is enabled.
MOVEQ R0, #1
MOVNE R0, #0
BX LR
END
;------------------------------------------------------------------------------
;
; GetInterruptState() function for ARM
;
; Copyright (c) 2006 - 2009, Intel Corporation<BR>
; Portions copyright (c) 2008-2009 Apple Inc.<BR>
; All rights reserved. This program and the accompanying materials
; are licensed and made available under the terms and conditions of the BSD License
; which accompanies this distribution. The full text of the license may be found at
; http://opensource.org/licenses/bsd-license.php
;
; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
;
;------------------------------------------------------------------------------
EXPORT GetInterruptState
AREA Interrupt_enable, CODE, READONLY
;/**
; Retrieves the current CPU interrupt state.
;
; Returns TRUE is interrupts are currently enabled. Otherwise
; returns FALSE.
;
; @retval TRUE CPU interrupts are enabled.
; @retval FALSE CPU interrupts are disabled.
;
;**/
;
;BOOLEAN
;EFIAPI
;GetInterruptState (
; VOID
; );
;
GetInterruptState
MRS R0, CPSR
TST R0, #0x80 ;Check if IRQ is enabled.
MOVEQ R0, #1
MOVNE R0, #0
BX LR
END

118
MdePkg/Library/BaseLib/Arm/InternalSwitchStack.c
View File

@ -1,59 +1,59 @@
/** @file
SwitchStack() function for ARM.
Copyright (c) 2006 - 2007, Intel Corporation<BR>
Portions copyright (c) 2008-2009 Apple Inc.<BR>
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include "BaseLibInternals.h"
/**
Transfers control to a function starting with a new stack.
Transfers control to the function specified by EntryPoint using the
new stack specified by NewStack and passing in the parameters specified
by Context1 and Context2. Context1 and Context2 are optional and may
be NULL. The function EntryPoint must never return.
Marker will be ignored on IA-32, x64, and EBC.
IPF CPUs expect one additional parameter of type VOID * that specifies
the new backing store pointer.
If EntryPoint is NULL, then ASSERT().
If NewStack is NULL, then ASSERT().
@param EntryPoint A pointer to function to call with the new stack.
@param Context1 A pointer to the context to pass into the EntryPoint
function.
@param Context2 A pointer to the context to pass into the EntryPoint
function.
@param NewStack A pointer to the new stack to use for the EntryPoint
function.
@param Marker VA_LIST marker for the variable argument list.
**/
VOID
EFIAPI
InternalSwitchStack (
IN SWITCH_STACK_ENTRY_POINT EntryPoint,
IN VOID *Context1, OPTIONAL
IN VOID *Context2, OPTIONAL
IN VOID *NewStack,
IN VA_LIST Marker
)
{
//
// Stack should be aligned with CPU_STACK_ALIGNMENT
//
ASSERT (((UINTN)NewStack & (CPU_STACK_ALIGNMENT - 1)) == 0);
InternalSwitchStackAsm (EntryPoint, Context1, Context2, NewStack);
}
/** @file
SwitchStack() function for ARM.
Copyright (c) 2006 - 2007, Intel Corporation<BR>
Portions copyright (c) 2008-2009 Apple Inc.<BR>
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include "BaseLibInternals.h"
/**
Transfers control to a function starting with a new stack.
Transfers control to the function specified by EntryPoint using the
new stack specified by NewStack and passing in the parameters specified
by Context1 and Context2. Context1 and Context2 are optional and may
be NULL. The function EntryPoint must never return.
Marker will be ignored on IA-32, x64, and EBC.
IPF CPUs expect one additional parameter of type VOID * that specifies
the new backing store pointer.
If EntryPoint is NULL, then ASSERT().
If NewStack is NULL, then ASSERT().
@param EntryPoint A pointer to function to call with the new stack.
@param Context1 A pointer to the context to pass into the EntryPoint
function.
@param Context2 A pointer to the context to pass into the EntryPoint
function.
@param NewStack A pointer to the new stack to use for the EntryPoint
function.
@param Marker VA_LIST marker for the variable argument list.
**/
VOID
EFIAPI
InternalSwitchStack (
IN SWITCH_STACK_ENTRY_POINT EntryPoint,
IN VOID *Context1, OPTIONAL
IN VOID *Context2, OPTIONAL
IN VOID *NewStack,
IN VA_LIST Marker
)
{
//
// Stack should be aligned with CPU_STACK_ALIGNMENT
//
ASSERT (((UINTN)NewStack & (CPU_STACK_ALIGNMENT - 1)) == 0);
InternalSwitchStackAsm (EntryPoint, Context1, Context2, NewStack);
}

140
MdePkg/Library/BaseLib/Arm/SetJumpLongJump.S
View File

@ -1,70 +1,70 @@
#------------------------------------------------------------------------------
#
# Copyright (c) 2006 - 2009, Intel Corporation<BR>
# Portions copyright (c) 2008-2009 Apple Inc.<BR>
# All rights reserved. This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#------------------------------------------------------------------------------
.text
.p2align 2
.globl ASM_PFX(SetJump)
.globl ASM_PFX(InternalLongJump)
#/**
# Saves the current CPU context that can be restored with a call to LongJump() and returns 0.#
#
# Saves the current CPU context in the buffer specified by JumpBuffer and returns 0. The initial
# call to SetJump() must always return 0. Subsequent calls to LongJump() cause a non-zero
# value to be returned by SetJump().
#
# If JumpBuffer is NULL, then ASSERT().
# For IPF CPUs, if JumpBuffer is not aligned on a 16-byte boundary, then ASSERT().
#
# @param JumpBuffer A pointer to CPU context buffer.
#
#**/
#
#UINTN
#EFIAPI
#SetJump (
# IN BASE_LIBRARY_JUMP_BUFFER *JumpBuffer // R0
# );
#
ASM_PFX(SetJump):
mov r3, r13
stmia r0, {r3-r12,r14}
eor r0, r0, r0
bx lr
#/**
# Restores the CPU context that was saved with SetJump().#
#
# Restores the CPU context from the buffer specified by JumpBuffer.
# This function never returns to the caller.
# Instead is resumes execution based on the state of JumpBuffer.
#
# @param JumpBuffer A pointer to CPU context buffer.
# @param Value The value to return when the SetJump() context is restored.
#
#**/
#VOID
#EFIAPI
#InternalLongJump (
# IN BASE_LIBRARY_JUMP_BUFFER *JumpBuffer, // R0
# IN UINTN Value // R1
# );
#
ASM_PFX(InternalLongJump):
ldmia r0, {r3-r12,r14}
mov r13, r3
mov r0, r1
bx lr
ASM_FUNCTION_REMOVE_IF_UNREFERENCED()
#------------------------------------------------------------------------------
#
# Copyright (c) 2006 - 2009, Intel Corporation<BR>
# Portions copyright (c) 2008-2009 Apple Inc.<BR>
# All rights reserved. This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#------------------------------------------------------------------------------
.text
.p2align 2
.globl ASM_PFX(SetJump)
.globl ASM_PFX(InternalLongJump)
#/**
# Saves the current CPU context that can be restored with a call to LongJump() and returns 0.#
#
# Saves the current CPU context in the buffer specified by JumpBuffer and returns 0. The initial
# call to SetJump() must always return 0. Subsequent calls to LongJump() cause a non-zero
# value to be returned by SetJump().
#
# If JumpBuffer is NULL, then ASSERT().
# For IPF CPUs, if JumpBuffer is not aligned on a 16-byte boundary, then ASSERT().
#
# @param JumpBuffer A pointer to CPU context buffer.
#
#**/
#
#UINTN
#EFIAPI
#SetJump (
# IN BASE_LIBRARY_JUMP_BUFFER *JumpBuffer // R0
# );
#
ASM_PFX(SetJump):
mov r3, r13
stmia r0, {r3-r12,r14}
eor r0, r0, r0
bx lr
#/**
# Restores the CPU context that was saved with SetJump().#
#
# Restores the CPU context from the buffer specified by JumpBuffer.
# This function never returns to the caller.
# Instead is resumes execution based on the state of JumpBuffer.
#
# @param JumpBuffer A pointer to CPU context buffer.
# @param Value The value to return when the SetJump() context is restored.
#
#**/
#VOID
#EFIAPI
#InternalLongJump (
# IN BASE_LIBRARY_JUMP_BUFFER *JumpBuffer, // R0
# IN UINTN Value // R1
# );
#
ASM_PFX(InternalLongJump):
ldmia r0, {r3-r12,r14}
mov r13, r3
mov r0, r1
bx lr
ASM_FUNCTION_REMOVE_IF_UNREFERENCED()

140
MdePkg/Library/BaseLib/Arm/SetJumpLongJump.asm
View File

@ -1,70 +1,70 @@
;------------------------------------------------------------------------------
;
; Copyright (c) 2006 - 2009, Intel Corporation<BR>
; Portions copyright (c) 2008-2009 Apple Inc.<BR>
; All rights reserved. This program and the accompanying materials
; are licensed and made available under the terms and conditions of the BSD License
; which accompanies this distribution. The full text of the license may be found at
; http://opensource.org/licenses/bsd-license.php
;
; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
;
;------------------------------------------------------------------------------
EXPORT SetJump
EXPORT InternalLongJump
AREA BaseLib, CODE, READONLY
;/**
; Saves the current CPU context that can be restored with a call to LongJump() and returns 0.;
;
; Saves the current CPU context in the buffer specified by JumpBuffer and returns 0. The initial
; call to SetJump() must always return 0. Subsequent calls to LongJump() cause a non-zero
; value to be returned by SetJump().
;
; If JumpBuffer is NULL, then ASSERT().
; For IPF CPUs, if JumpBuffer is not aligned on a 16-byte boundary, then ASSERT().
;
; @param JumpBuffer A pointer to CPU context buffer.
;
;**/
;
;UINTN
;EFIAPI
;SetJump (
; IN BASE_LIBRARY_JUMP_BUFFER *JumpBuffer // R0
; )
;
SetJump
MOV R3, R13
STM R0, {R3-R12,R14}
EOR R0, R0
BX LR
;/**
; Restores the CPU context that was saved with SetJump().;
;
; Restores the CPU context from the buffer specified by JumpBuffer.
; This function never returns to the caller.
; Instead is resumes execution based on the state of JumpBuffer.
;
; @param JumpBuffer A pointer to CPU context buffer.
; @param Value The value to return when the SetJump() context is restored.
;
;**/
;VOID
;EFIAPI
;InternalLongJump (
; IN BASE_LIBRARY_JUMP_BUFFER *JumpBuffer, // R0
; IN UINTN Value // R1
; );
;
InternalLongJump
LDM R0, {R3-R12,R14}
MOV R13, R3
MOV R0, R1
BX LR
END
;------------------------------------------------------------------------------
;
; Copyright (c) 2006 - 2009, Intel Corporation<BR>
; Portions copyright (c) 2008-2009 Apple Inc.<BR>
; All rights reserved. This program and the accompanying materials
; are licensed and made available under the terms and conditions of the BSD License
; which accompanies this distribution. The full text of the license may be found at
; http://opensource.org/licenses/bsd-license.php
;
; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
;
;------------------------------------------------------------------------------
EXPORT SetJump
EXPORT InternalLongJump
AREA BaseLib, CODE, READONLY
;/**
; Saves the current CPU context that can be restored with a call to LongJump() and returns 0.;
;
; Saves the current CPU context in the buffer specified by JumpBuffer and returns 0. The initial
; call to SetJump() must always return 0. Subsequent calls to LongJump() cause a non-zero
; value to be returned by SetJump().
;
; If JumpBuffer is NULL, then ASSERT().
; For IPF CPUs, if JumpBuffer is not aligned on a 16-byte boundary, then ASSERT().
;
; @param JumpBuffer A pointer to CPU context buffer.
;
;**/
;
;UINTN
;EFIAPI
;SetJump (
; IN BASE_LIBRARY_JUMP_BUFFER *JumpBuffer // R0
; )
;
SetJump
MOV R3, R13
STM R0, {R3-R12,R14}
EOR R0, R0
BX LR
;/**
; Restores the CPU context that was saved with SetJump().;
;
; Restores the CPU context from the buffer specified by JumpBuffer.
; This function never returns to the caller.
; Instead is resumes execution based on the state of JumpBuffer.
;
; @param JumpBuffer A pointer to CPU context buffer.
; @param Value The value to return when the SetJump() context is restored.
;
;**/
;VOID
;EFIAPI
;InternalLongJump (
; IN BASE_LIBRARY_JUMP_BUFFER *JumpBuffer, // R0
; IN UINTN Value // R1
; );
;
InternalLongJump
LDM R0, {R3-R12,R14}
MOV R13, R3
MOV R0, R1
BX LR
END

90
MdePkg/Library/BaseLib/Arm/SwitchStack.asm
View File

@ -1,45 +1,45 @@
;------------------------------------------------------------------------------
;
; Copyright (c) 2006 - 2009, Intel Corporation<BR>
; Portions copyright (c) 2008-2009 Apple Inc.<BR>
; All rights reserved. This program and the accompanying materials
; are licensed and made available under the terms and conditions of the BSD License
; which accompanies this distribution. The full text of the license may be found at
; http://opensource.org/licenses/bsd-license.php
;
; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
;
;------------------------------------------------------------------------------
EXPORT InternalSwitchStackAsm
AREA Switch_Stack, CODE, READONLY
;/**
; This allows the caller to switch the stack and goes to the new entry point
;
; @param EntryPoint Pointer to the location to enter
; @param Context Parameter to pass in
; @param Context2 Parameter2 to pass in
; @param NewStack New Location of the stack
;
; @return Nothing. Goes to the Entry Point passing in the new parameters
;
;**/
;VOID
;EFIAPI
;InternalSwitchStackAsm (
; SWITCH_STACK_ENTRY_POINT EntryPoint,
; VOID *Context,
; VOID *Context2,
; VOID *NewStack
; );
;
InternalSwitchStackAsm
MOV LR, R0
MOV SP, R3
MOV R0, R1
MOV R1, R2
BX LR
END
;------------------------------------------------------------------------------
;
; Copyright (c) 2006 - 2009, Intel Corporation<BR>
; Portions copyright (c) 2008-2009 Apple Inc.<BR>
; All rights reserved. This program and the accompanying materials
; are licensed and made available under the terms and conditions of the BSD License
; which accompanies this distribution. The full text of the license may be found at
; http://opensource.org/licenses/bsd-license.php
;
; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
;
;------------------------------------------------------------------------------
EXPORT InternalSwitchStackAsm
AREA Switch_Stack, CODE, READONLY
;/**
; This allows the caller to switch the stack and goes to the new entry point
;
; @param EntryPoint Pointer to the location to enter
; @param Context Parameter to pass in
; @param Context2 Parameter2 to pass in
; @param NewStack New Location of the stack
;
; @return Nothing. Goes to the Entry Point passing in the new parameters
;
;**/
;VOID
;EFIAPI
;InternalSwitchStackAsm (
; SWITCH_STACK_ENTRY_POINT EntryPoint,
; VOID *Context,
; VOID *Context2,
; VOID *NewStack
; );
;
InternalSwitchStackAsm
MOV LR, R0
MOV SP, R3
MOV R0, R1
MOV R1, R2
BX LR
END

504
MdePkg/Library/BaseLib/Arm/Unaligned.c
View File

@ -1,252 +1,252 @@
/** @file
Unaligned access functions of BaseLib for ARM.
volatile was added to work around optimization issues.
Copyright (c) 2006 - 2009, Intel Corporation<BR>
Portions Copyright (c) 2008-2009 Apple Inc.<BR>
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include "BaseLibInternals.h"
/**
Reads a 16-bit value from memory that may be unaligned.
This function returns the 16-bit value pointed to by Buffer. The function
guarantees that the read operation does not produce an alignment fault.
If the Buffer is NULL, then ASSERT().
@param Buffer Pointer to a 16-bit value that may be unaligned.
@return The 16-bit value read from Buffer.
**/
UINT16
EFIAPI
ReadUnaligned16 (
IN CONST UINT16 *Buffer
)
{
volatile UINT8 LowerByte;
volatile UINT8 HigherByte;
ASSERT (Buffer != NULL);
LowerByte = ((UINT8*)Buffer)[0];
HigherByte = ((UINT8*)Buffer)[1];
return (UINT16)(LowerByte | (HigherByte << 8));
}
/**
Writes a 16-bit value to memory that may be unaligned.
This function writes the 16-bit value specified by Value to Buffer. Value is
returned. The function guarantees that the write operation does not produce
an alignment fault.
If the Buffer is NULL, then ASSERT().
@param Buffer Pointer to a 16-bit value that may be unaligned.
@param Value 16-bit value to write to Buffer.
@return The 16-bit value to write to Buffer.
**/
UINT16
EFIAPI
WriteUnaligned16 (
OUT UINT16 *Buffer,
IN UINT16 Value
)
{
ASSERT (Buffer != NULL);
((volatile UINT8*)Buffer)[0] = (UINT8)Value;
((volatile UINT8*)Buffer)[1] = (UINT8)(Value >> 8);
return Value;
}
/**
Reads a 24-bit value from memory that may be unaligned.
This function returns the 24-bit value pointed to by Buffer. The function
guarantees that the read operation does not produce an alignment fault.
If the Buffer is NULL, then ASSERT().
@param Buffer Pointer to a 24-bit value that may be unaligned.
@return The 24-bit value read from Buffer.
**/
UINT32
EFIAPI
ReadUnaligned24 (
IN CONST UINT32 *Buffer
)
{
ASSERT (Buffer != NULL);
return (UINT32)(
ReadUnaligned16 ((UINT16*)Buffer) |
(((UINT8*)Buffer)[2] << 16)
);
}
/**
Writes a 24-bit value to memory that may be unaligned.
This function writes the 24-bit value specified by Value to Buffer. Value is
returned. The function guarantees that the write operation does not produce
an alignment fault.
If the Buffer is NULL, then ASSERT().
@param Buffer Pointer to a 24-bit value that may be unaligned.
@param Value 24-bit value to write to Buffer.
@return The 24-bit value to write to Buffer.
**/
UINT32
EFIAPI
WriteUnaligned24 (
OUT UINT32 *Buffer,
IN UINT32 Value
)
{
ASSERT (Buffer != NULL);
WriteUnaligned16 ((UINT16*)Buffer, (UINT16)Value);
*(UINT8*)((UINT16*)Buffer + 1) = (UINT8)(Value >> 16);
return Value;
}
/**
Reads a 32-bit value from memory that may be unaligned.
This function returns the 32-bit value pointed to by Buffer. The function
guarantees that the read operation does not produce an alignment fault.
If the Buffer is NULL, then ASSERT().
@param Buffer Pointer to a 32-bit value that may be unaligned.
@return The 32-bit value read from Buffer.
**/
UINT32
EFIAPI
ReadUnaligned32 (
IN CONST UINT32 *Buffer
)
{
UINT16 LowerBytes;
UINT16 HigherBytes;
ASSERT (Buffer != NULL);
LowerBytes = ReadUnaligned16 ((UINT16*) Buffer);
HigherBytes = ReadUnaligned16 ((UINT16*) Buffer + 1);
return (UINT32) (LowerBytes | (HigherBytes << 16));
}
/**
Writes a 32-bit value to memory that may be unaligned.
This function writes the 32-bit value specified by Value to Buffer. Value is
returned. The function guarantees that the write operation does not produce
an alignment fault.
If the Buffer is NULL, then ASSERT().
@param Buffer Pointer to a 32-bit value that may be unaligned.
@param Value 32-bit value to write to Buffer.
@return The 32-bit value to write to Buffer.
**/
UINT32
EFIAPI
WriteUnaligned32 (
OUT UINT32 *Buffer,
IN UINT32 Value
)
{
ASSERT (Buffer != NULL);
WriteUnaligned16 ((UINT16*)Buffer, (UINT16)Value);
WriteUnaligned16 ((UINT16*)Buffer + 1, (UINT16)(Value >> 16));
return Value;
}
/**
Reads a 64-bit value from memory that may be unaligned.
This function returns the 64-bit value pointed to by Buffer. The function
guarantees that the read operation does not produce an alignment fault.
If the Buffer is NULL, then ASSERT().
@param Buffer Pointer to a 64-bit value that may be unaligned.
@return The 64-bit value read from Buffer.
**/
UINT64
EFIAPI
ReadUnaligned64 (
IN CONST UINT64 *Buffer
)
{
UINT32 LowerBytes;
UINT32 HigherBytes;
ASSERT (Buffer != NULL);
LowerBytes = ReadUnaligned32 ((UINT32*) Buffer);
HigherBytes = ReadUnaligned32 ((UINT32*) Buffer + 1);
return (UINT64) (LowerBytes | LShiftU64 (HigherBytes, 32));
}
/**
Writes a 64-bit value to memory that may be unaligned.
This function writes the 64-bit value specified by Value to Buffer. Value is
returned. The function guarantees that the write operation does not produce
an alignment fault.
If the Buffer is NULL, then ASSERT().
@param Buffer Pointer to a 64-bit value that may be unaligned.
@param Value 64-bit value to write to Buffer.
@return The 64-bit value to write to Buffer.
**/
UINT64
EFIAPI
WriteUnaligned64 (
OUT UINT64 *Buffer,
IN UINT64 Value
)
{
ASSERT (Buffer != NULL);
WriteUnaligned32 ((UINT32*)Buffer, (UINT32)Value);
WriteUnaligned32 ((UINT32*)Buffer + 1, (UINT32)RShiftU64 (Value, 32));
return Value;
}
/** @file
Unaligned access functions of BaseLib for ARM.
volatile was added to work around optimization issues.
Copyright (c) 2006 - 2009, Intel Corporation<BR>
Portions Copyright (c) 2008-2009 Apple Inc.<BR>
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include "BaseLibInternals.h"
/**
Reads a 16-bit value from memory that may be unaligned.
This function returns the 16-bit value pointed to by Buffer. The function
guarantees that the read operation does not produce an alignment fault.
If the Buffer is NULL, then ASSERT().
@param Buffer Pointer to a 16-bit value that may be unaligned.
@return The 16-bit value read from Buffer.
**/
UINT16
EFIAPI
ReadUnaligned16 (
IN CONST UINT16 *Buffer
)
{
volatile UINT8 LowerByte;
volatile UINT8 HigherByte;
ASSERT (Buffer != NULL);
LowerByte = ((UINT8*)Buffer)[0];
HigherByte = ((UINT8*)Buffer)[1];
return (UINT16)(LowerByte | (HigherByte << 8));
}
/**
Writes a 16-bit value to memory that may be unaligned.
This function writes the 16-bit value specified by Value to Buffer. Value is
returned. The function guarantees that the write operation does not produce
an alignment fault.
If the Buffer is NULL, then ASSERT().
@param Buffer Pointer to a 16-bit value that may be unaligned.
@param Value 16-bit value to write to Buffer.
@return The 16-bit value to write to Buffer.
**/
UINT16
EFIAPI
WriteUnaligned16 (
OUT UINT16 *Buffer,
IN UINT16 Value
)
{
ASSERT (Buffer != NULL);
((volatile UINT8*)Buffer)[0] = (UINT8)Value;
((volatile UINT8*)Buffer)[1] = (UINT8)(Value >> 8);
return Value;
}
/**
Reads a 24-bit value from memory that may be unaligned.
This function returns the 24-bit value pointed to by Buffer. The function
guarantees that the read operation does not produce an alignment fault.
If the Buffer is NULL, then ASSERT().
@param Buffer Pointer to a 24-bit value that may be unaligned.
@return The 24-bit value read from Buffer.
**/
UINT32
EFIAPI
ReadUnaligned24 (
IN CONST UINT32 *Buffer
)
{
ASSERT (Buffer != NULL);
return (UINT32)(
ReadUnaligned16 ((UINT16*)Buffer) |
(((UINT8*)Buffer)[2] << 16)
);
}
/**
Writes a 24-bit value to memory that may be unaligned.
This function writes the 24-bit value specified by Value to Buffer. Value is
returned. The function guarantees that the write operation does not produce
an alignment fault.
If the Buffer is NULL, then ASSERT().
@param Buffer Pointer to a 24-bit value that may be unaligned.
@param Value 24-bit value to write to Buffer.
@return The 24-bit value to write to Buffer.
**/
UINT32
EFIAPI
WriteUnaligned24 (
OUT UINT32 *Buffer,
IN UINT32 Value
)
{
ASSERT (Buffer != NULL);
WriteUnaligned16 ((UINT16*)Buffer, (UINT16)Value);
*(UINT8*)((UINT16*)Buffer + 1) = (UINT8)(Value >> 16);
return Value;
}
/**
Reads a 32-bit value from memory that may be unaligned.
This function returns the 32-bit value pointed to by Buffer. The function
guarantees that the read operation does not produce an alignment fault.
If the Buffer is NULL, then ASSERT().
@param Buffer Pointer to a 32-bit value that may be unaligned.
@return The 32-bit value read from Buffer.
**/
UINT32
EFIAPI
ReadUnaligned32 (
IN CONST UINT32 *Buffer
)
{
UINT16 LowerBytes;
UINT16 HigherBytes;
ASSERT (Buffer != NULL);
LowerBytes = ReadUnaligned16 ((UINT16*) Buffer);
HigherBytes = ReadUnaligned16 ((UINT16*) Buffer + 1);
return (UINT32) (LowerBytes | (HigherBytes << 16));
}
/**
Writes a 32-bit value to memory that may be unaligned.
This function writes the 32-bit value specified by Value to Buffer. Value is
returned. The function guarantees that the write operation does not produce
an alignment fault.
If the Buffer is NULL, then ASSERT().
@param Buffer Pointer to a 32-bit value that may be unaligned.
@param Value 32-bit value to write to Buffer.
@return The 32-bit value to write to Buffer.
**/
UINT32
EFIAPI
WriteUnaligned32 (
OUT UINT32 *Buffer,
IN UINT32 Value
)
{
ASSERT (Buffer != NULL);
WriteUnaligned16 ((UINT16*)Buffer, (UINT16)Value);
WriteUnaligned16 ((UINT16*)Buffer + 1, (UINT16)(Value >> 16));
return Value;
}
/**
Reads a 64-bit value from memory that may be unaligned.
This function returns the 64-bit value pointed to by Buffer. The function
guarantees that the read operation does not produce an alignment fault.
If the Buffer is NULL, then ASSERT().
@param Buffer Pointer to a 64-bit value that may be unaligned.
@return The 64-bit value read from Buffer.
**/
UINT64
EFIAPI
ReadUnaligned64 (
IN CONST UINT64 *Buffer
)
{
UINT32 LowerBytes;
UINT32 HigherBytes;
ASSERT (Buffer != NULL);
LowerBytes = ReadUnaligned32 ((UINT32*) Buffer);
HigherBytes = ReadUnaligned32 ((UINT32*) Buffer + 1);
return (UINT64) (LowerBytes | LShiftU64 (HigherBytes, 32));
}
/**
Writes a 64-bit value to memory that may be unaligned.
This function writes the 64-bit value specified by Value to Buffer. Value is
returned. The function guarantees that the write operation does not produce
an alignment fault.
If the Buffer is NULL, then ASSERT().
@param Buffer Pointer to a 64-bit value that may be unaligned.
@param Value 64-bit value to write to Buffer.
@return The 64-bit value to write to Buffer.
**/
UINT64
EFIAPI
WriteUnaligned64 (
OUT UINT64 *Buffer,
IN UINT64 Value
)
{
ASSERT (Buffer != NULL);
WriteUnaligned32 ((UINT32*)Buffer, (UINT32)Value);
WriteUnaligned32 ((UINT32*)Buffer + 1, (UINT32)RShiftU64 (Value, 32));
return Value;
}

3516
MdePkg/Library/BaseLib/Ia32/GccInline.c
View File

File diff suppressed because it is too large Load Diff

3612
MdePkg/Library/BaseLib/X64/GccInline.c
View File

File diff suppressed because it is too large Load Diff

6
MdePkg/Library/BasePeCoffGetEntryPointLib/PeCoffGetEntryPoint.c
View File

@ -3,7 +3,7 @@
loaded into memory or is executing at it's linked address.
Copyright (c) 2006 - 2008, Intel Corporation<BR>
Portions Copyright (c) 2008-2009 Apple Inc.<BR>
Portions Copyright (c) 2008-2009 Apple Inc.<BR>
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@ -256,8 +256,8 @@ PeCoffLoaderGetPdbPointer (
return (VOID *) ((CHAR8 *)CodeViewEntryPointer + sizeof (EFI_IMAGE_DEBUG_CODEVIEW_NB10_ENTRY));
case CODEVIEW_SIGNATURE_RSDS:
return (VOID *) ((CHAR8 *)CodeViewEntryPointer + sizeof (EFI_IMAGE_DEBUG_CODEVIEW_RSDS_ENTRY));
case CODEVIEW_SIGNATURE_MTOC:
return (VOID *) ((CHAR8 *)CodeViewEntryPointer + sizeof (EFI_IMAGE_DEBUG_CODEVIEW_MTOC_ENTRY));
case CODEVIEW_SIGNATURE_MTOC:
return (VOID *) ((CHAR8 *)CodeViewEntryPointer + sizeof (EFI_IMAGE_DEBUG_CODEVIEW_MTOC_ENTRY));
default:
break;
}

180
MdePkg/Library/BasePeCoffLib/Arm/PeCoffLoaderEx.c
View File

@ -1,90 +1,90 @@
/** @file
Specific relocation fixups for ARM architecture.
Copyright (c) 2006 - 2009, Intel Corporation<BR>
Portions copyright (c) 2008-2009 Apple Inc.<BR>
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include "BasePeCoffLibInternals.h"
/**
Performs an ARM-based specific relocation fixup and is a no-op on other
instruction sets.
@param Reloc Pointer to the relocation record.
@param Fixup Pointer to the address to fix up.
@param FixupData Pointer to a buffer to log the fixups.
@param Adjust The offset to adjust the fixup.
@return Status code.
**/
RETURN_STATUS
PeCoffLoaderRelocateImageEx (
IN UINT16 *Reloc,
IN OUT CHAR8 *Fixup,
IN OUT CHAR8 **FixupData,
IN UINT64 Adjust
)
{
return RETURN_UNSUPPORTED;
}
/**
Returns TRUE if the machine type of PE/COFF image is supported. Supported
does not mean the image can be executed it means the PE/COFF loader supports
loading and relocating of the image type. It's up to the caller to support
the entry point.
The IA32/X64 version PE/COFF loader/relocater both support IA32, X64 and EBC images.
@param Machine Machine type from the PE Header.
@return TRUE if this PE/COFF loader can load the image
**/
BOOLEAN
PeCoffLoaderImageFormatSupported (
IN UINT16 Machine
)
{
if ((Machine == IMAGE_FILE_MACHINE_ARMTHUMB_MIXED) || (Machine == IMAGE_FILE_MACHINE_EBC)) {
return TRUE;
}
return FALSE;
}
/**
Performs an ARM-based specific re-relocation fixup and is a no-op on other
instruction sets. This is used to re-relocated the image into the EFI virtual
space for runtime calls.
@param Reloc Pointer to the relocation record.
@param Fixup Pointer to the address to fix up.
@param FixupData Pointer to a buffer to log the fixups.
@param Adjust The offset to adjust the fixup.
@return Status code.
**/
RETURN_STATUS
PeHotRelocateImageEx (
IN UINT16 *Reloc,
IN OUT CHAR8 *Fixup,
IN OUT CHAR8 **FixupData,
IN UINT64 Adjust
)
{
return RETURN_UNSUPPORTED;
}
/** @file
Specific relocation fixups for ARM architecture.
Copyright (c) 2006 - 2009, Intel Corporation<BR>
Portions copyright (c) 2008-2009 Apple Inc.<BR>
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include "BasePeCoffLibInternals.h"
/**
Performs an ARM-based specific relocation fixup and is a no-op on other
instruction sets.
@param Reloc Pointer to the relocation record.
@param Fixup Pointer to the address to fix up.
@param FixupData Pointer to a buffer to log the fixups.
@param Adjust The offset to adjust the fixup.
@return Status code.
**/
RETURN_STATUS
PeCoffLoaderRelocateImageEx (
IN UINT16 *Reloc,
IN OUT CHAR8 *Fixup,
IN OUT CHAR8 **FixupData,
IN UINT64 Adjust
)
{
return RETURN_UNSUPPORTED;
}
/**
Returns TRUE if the machine type of PE/COFF image is supported. Supported
does not mean the image can be executed it means the PE/COFF loader supports
loading and relocating of the image type. It's up to the caller to support
the entry point.
The IA32/X64 version PE/COFF loader/relocater both support IA32, X64 and EBC images.
@param Machine Machine type from the PE Header.
@return TRUE if this PE/COFF loader can load the image
**/
BOOLEAN
PeCoffLoaderImageFormatSupported (
IN UINT16 Machine
)
{
if ((Machine == IMAGE_FILE_MACHINE_ARMTHUMB_MIXED) || (Machine == IMAGE_FILE_MACHINE_EBC)) {
return TRUE;
}
return FALSE;
}
/**
Performs an ARM-based specific re-relocation fixup and is a no-op on other
instruction sets. This is used to re-relocated the image into the EFI virtual
space for runtime calls.
@param Reloc Pointer to the relocation record.
@param Fixup Pointer to the address to fix up.
@param FixupData Pointer to a buffer to log the fixups.
@param Adjust The offset to adjust the fixup.
@return Status code.
**/
RETURN_STATUS
PeHotRelocateImageEx (
IN UINT16 *Reloc,
IN OUT CHAR8 *Fixup,
IN OUT CHAR8 **FixupData,
IN UINT64 Adjust
)
{
return RETURN_UNSUPPORTED;
}

8
MdePkg/Library/BasePeCoffLib/BasePeCoff.c
View File

@ -3,7 +3,7 @@
only supports relocating IA32, x64, IPF, and EBC images.
Copyright (c) 2006 - 2008, Intel Corporation<BR>
Portions Copyright (c) 2008-2009 Apple Inc.<BR>
Portions Copyright (c) 2008-2009 Apple Inc.<BR>
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@ -1153,10 +1153,10 @@ PeCoffLoaderLoadImage (
ImageContext->PdbPointer = (CHAR8 *)ImageContext->CodeView + sizeof (EFI_IMAGE_DEBUG_CODEVIEW_RSDS_ENTRY);
break;
case CODEVIEW_SIGNATURE_MTOC:
case CODEVIEW_SIGNATURE_MTOC:
ImageContext->PdbPointer = (CHAR8 *)ImageContext->CodeView + sizeof (EFI_IMAGE_DEBUG_CODEVIEW_MTOC_ENTRY);
break;
break;
default:
break;
}

8
MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
View File

@ -5,7 +5,7 @@
# The X64 version library support loading IA32, X64 and EBC PE/COFF images.
#
# Copyright (c) 2006 - 2009, Intel Corporation.<BR>
# Portions Copyright (c) 2008-2009 Apple Inc.<BR>
# Portions Copyright (c) 2008-2009 Apple Inc.<BR>
#
# All rights reserved. This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
@ -40,9 +40,9 @@
[Sources.IPF]
Ipf/PeCoffLoaderEx.c
[Sources.ARM]
Arm/PeCoffLoaderEx.c
[Sources.ARM]
Arm/PeCoffLoaderEx.c
[Packages]
MdePkg/MdePkg.dec

18
MdePkg/Library/BasePrintLib/PrintLib.c
View File

@ -2,7 +2,7 @@
Base Print Library instance implementation.
Copyright (c) 2006 - 2008, Intel Corporation<BR>
Portions Copyright (c) 2008-2009 Apple Inc.<BR>
Portions Copyright (c) 2008-2009 Apple Inc.<BR>
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@ -15,14 +15,14 @@
#include "PrintLibInternal.h"
//
//
// Declare a VA_LIST global variable that is used in calls to BasePrintLibSPrintMarker()
// when the BASE_LIST parameter is valid and the VA_LIST parameter is ignored.
// A NULL VA_LIST can not be passed into BasePrintLibSPrintMarker() because some
// compilers define VA_LIST to be a structure.
//
// compilers define VA_LIST to be a structure.
//
VA_LIST gNullVaList;
#define ASSERT_UNICODE_BUFFER(Buffer) ASSERT ((((UINTN) (Buffer)) & 0x01) == 0)
/**
@ -118,7 +118,7 @@ UnicodeBSPrint (
{
ASSERT_UNICODE_BUFFER (StartOfBuffer);
ASSERT_UNICODE_BUFFER (FormatString);
return BasePrintLibSPrintMarker ((CHAR8 *)StartOfBuffer, BufferSize >> 1, FORMAT_UNICODE | OUTPUT_UNICODE, (CHAR8 *)FormatString, gNullVaList, Marker);
return BasePrintLibSPrintMarker ((CHAR8 *)StartOfBuffer, BufferSize >> 1, FORMAT_UNICODE | OUTPUT_UNICODE, (CHAR8 *)FormatString, gNullVaList, Marker);
}
/**
@ -259,7 +259,7 @@ UnicodeBSPrintAsciiFormat (
)
{
ASSERT_UNICODE_BUFFER (StartOfBuffer);
return BasePrintLibSPrintMarker ((CHAR8 *)StartOfBuffer, BufferSize >> 1, OUTPUT_UNICODE, FormatString, gNullVaList, Marker);
return BasePrintLibSPrintMarker ((CHAR8 *)StartOfBuffer, BufferSize >> 1, OUTPUT_UNICODE, FormatString, gNullVaList, Marker);
}
/**
@ -450,7 +450,7 @@ AsciiBSPrint (
IN BASE_LIST Marker
)
{
return BasePrintLibSPrintMarker (StartOfBuffer, BufferSize, 0, FormatString, gNullVaList, Marker);
return BasePrintLibSPrintMarker (StartOfBuffer, BufferSize, 0, FormatString, gNullVaList, Marker);
}
/**
@ -590,7 +590,7 @@ AsciiBSPrintUnicodeFormat (
)
{
ASSERT_UNICODE_BUFFER (FormatString);
return BasePrintLibSPrintMarker (StartOfBuffer, BufferSize, FORMAT_UNICODE, (CHAR8 *)FormatString, gNullVaList, Marker);
return BasePrintLibSPrintMarker (StartOfBuffer, BufferSize, FORMAT_UNICODE, (CHAR8 *)FormatString, gNullVaList, Marker);
}
/**

196
MdePkg/Library/BaseSynchronizationLib/Arm/Synchronization.c
View File

@ -1,98 +1,98 @@
/** @file
Implementation of synchronization functions. Still needs to be ported
Copyright (c) 2006 - 2009, Intel Corporation<BR>
Portions copyright (c) 2008-2009 Apple Inc.<BR>
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
UINT32
EFIAPI
InternalSyncCompareExchange32 (
IN volatile UINT32 *Value,
IN UINT32 CompareValue,
IN UINT32 ExchangeValue
)
{
return *Value != CompareValue ? *Value :
((*Value = ExchangeValue), CompareValue);
}
/**
Performs an atomic compare exchange operation on a 64-bit unsigned integer.
Performs an atomic compare exchange operation on the 64-bit unsigned integer specified
by Value. If Value is equal to CompareValue, then Value is set to ExchangeValue and
CompareValue is returned. If Value is not equal to CompareValue, then Value is returned.
The compare exchange operation must be performed using MP safe mechanisms.
@param Value A pointer to the 64-bit value for the compare exchange
operation.
@param CompareValue 64-bit value used in compare operation.
@param ExchangeValue 64-bit value used in exchange operation.
@return The original *Value before exchange.
**/
UINT64
EFIAPI
InternalSyncCompareExchange64 (
IN volatile UINT64 *Value,
IN UINT64 CompareValue,
IN UINT64 ExchangeValue
)
{
return *Value != CompareValue ? *Value :
((*Value = ExchangeValue), CompareValue);
}
/**
Performs an atomic increment of an 32-bit unsigned integer.
Performs an atomic increment of the 32-bit unsigned integer specified by
Value and returns the incremented value. The increment operation must be
performed using MP safe mechanisms. The state of the return value is not
guaranteed to be MP safe.
@param Value A pointer to the 32-bit value to increment.
@return The incremented value.
**/
UINT32
EFIAPI
InternalSyncIncrement (
IN volatile UINT32 *Value
)
{
return ++*Value;
}
/**
Performs an atomic decrement of an 32-bit unsigned integer.
Performs an atomic decrement of the 32-bit unsigned integer specified by
Value and returns the decrement value. The decrement operation must be
performed using MP safe mechanisms. The state of the return value is not
guaranteed to be MP safe.
@param Value A pointer to the 32-bit value to decrement.
@return The decrement value.
**/
UINT32
EFIAPI
InternalSyncDecrement (
IN volatile UINT32 *Value
)
{
return --*Value;
}
/** @file
Implementation of synchronization functions. Still needs to be ported
Copyright (c) 2006 - 2009, Intel Corporation<BR>
Portions copyright (c) 2008-2009 Apple Inc.<BR>
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
UINT32
EFIAPI
InternalSyncCompareExchange32 (
IN volatile UINT32 *Value,
IN UINT32 CompareValue,
IN UINT32 ExchangeValue
)
{
return *Value != CompareValue ? *Value :
((*Value = ExchangeValue), CompareValue);
}
/**
Performs an atomic compare exchange operation on a 64-bit unsigned integer.
Performs an atomic compare exchange operation on the 64-bit unsigned integer specified
by Value. If Value is equal to CompareValue, then Value is set to ExchangeValue and
CompareValue is returned. If Value is not equal to CompareValue, then Value is returned.
The compare exchange operation must be performed using MP safe mechanisms.
@param Value A pointer to the 64-bit value for the compare exchange
operation.
@param CompareValue 64-bit value used in compare operation.
@param ExchangeValue 64-bit value used in exchange operation.
@return The original *Value before exchange.
**/
UINT64
EFIAPI
InternalSyncCompareExchange64 (
IN volatile UINT64 *Value,
IN UINT64 CompareValue,
IN UINT64 ExchangeValue
)
{
return *Value != CompareValue ? *Value :
((*Value = ExchangeValue), CompareValue);
}
/**
Performs an atomic increment of an 32-bit unsigned integer.
Performs an atomic increment of the 32-bit unsigned integer specified by
Value and returns the incremented value. The increment operation must be
performed using MP safe mechanisms. The state of the return value is not
guaranteed to be MP safe.
@param Value A pointer to the 32-bit value to increment.
@return The incremented value.
**/
UINT32
EFIAPI
InternalSyncIncrement (
IN volatile UINT32 *Value
)
{
return ++*Value;
}
/**
Performs an atomic decrement of an 32-bit unsigned integer.
Performs an atomic decrement of the 32-bit unsigned integer specified by
Value and returns the decrement value. The decrement operation must be
performed using MP safe mechanisms. The state of the return value is not
guaranteed to be MP safe.
@param Value A pointer to the 32-bit value to decrement.
@return The decrement value.
**/
UINT32
EFIAPI
InternalSyncDecrement (
IN volatile UINT32 *Value
)
{
return --*Value;
}

386
MdePkg/Library/BaseSynchronizationLib/Ia32/GccInline.c
View File

@ -1,193 +1,193 @@
/** @file
GCC inline implementation of BaseSynchronizationLib processor specific functions.
Copyright (c) 2006 - 2009, Intel Corporation<BR>
Portions copyright (c) 2008-2009 Apple Inc.<BR>
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
/**
Performs an atomic increment of an 32-bit unsigned integer.
Performs an atomic increment of the 32-bit unsigned integer specified by
Value and returns the incremented value. The increment operation must be
performed using MP safe mechanisms. The state of the return value is not
guaranteed to be MP safe.
@param Value A pointer to the 32-bit value to increment.
@return The incremented value.
**/
UINT32
EFIAPI
InternalSyncIncrement (
IN volatile UINT32 *Value
)
{
UINT32 Result;
__asm__ __volatile__ (
"lock \n\t"
"incl %2 \n\t"
"movl %2, %%eax "
: "=a" (Result), // %0
"=m" (*Value) // %1
: "m" (*Value) // %2
: "memory",
"cc"
);
return Result;
}
/**
Performs an atomic decrement of an 32-bit unsigned integer.
Performs an atomic decrement of the 32-bit unsigned integer specified by
Value and returns the decremented value. The decrement operation must be
performed using MP safe mechanisms. The state of the return value is not
guaranteed to be MP safe.
@param Value A pointer to the 32-bit value to decrement.
@return The decremented value.
**/
UINT32
EFIAPI
InternalSyncDecrement (
IN volatile UINT32 *Value
)
{
UINT32 Result;
__asm__ __volatile__ (
"lock \n\t"
"decl %2 \n\t"
"movl %2, %%eax "
: "=a" (Result), // %0
"=m" (*Value) // %1
: "m" (*Value) // %2
: "memory",
"cc"
);
return Result;
}
/**
Performs an atomic compare exchange operation on a 32-bit unsigned integer.
Performs an atomic compare exchange operation on the 32-bit unsigned integer
specified by Value. If Value is equal to CompareValue, then Value is set to
ExchangeValue and CompareValue is returned. If Value is not equal to CompareValue,
then Value is returned. The compare exchange operation must be performed using
MP safe mechanisms.
@param Value A pointer to the 32-bit value for the compare exchange
operation.
@param CompareValue 32-bit value used in compare operation.
@param ExchangeValue 32-bit value used in exchange operation.
@return The original *Value before exchange.
**/
UINT32
EFIAPI
InternalSyncCompareExchange32 (
IN OUT volatile UINT32 *Value,
IN UINT32 CompareValue,
IN UINT32 ExchangeValue
)
{
// GCC 4.1 and forward supports atomic builtins
#if ((__GNUC__ > 4) || ((__GNUC__ == 4) && (__GNUC_MINOR__ >= 1)))
return __sync_val_compare_and_swap (Value, CompareValue, ExchangeValue);
#else
__asm__ __volatile__ (
" \n\t"
"lock \n\t"
"cmpxchgl %1, %2 \n\t"
: "=a" (CompareValue) // %0
: "q" (ExchangeValue), // %1
"m" (*Value),m // %2
"0" (CompareValue) // %4
: "memory",
"cc"
);
return CompareValue;
#endif
}
/**
Performs an atomic compare exchange operation on a 64-bit unsigned integer.
Performs an atomic compare exchange operation on the 64-bit unsigned integer specified
by Value. If Value is equal to CompareValue, then Value is set to ExchangeValue and
CompareValue is returned. If Value is not equal to CompareValue, then Value is returned.
The compare exchange operation must be performed using MP safe mechanisms.
@param Value A pointer to the 64-bit value for the compare exchange
operation.
@param CompareValue 64-bit value used in compare operation.
@param ExchangeValue 64-bit value used in exchange operation.
@return The original *Value before exchange.
**/
UINT64
EFIAPI
InternalSyncCompareExchange64 (
IN OUT volatile UINT64 *Value,
IN UINT64 CompareValue,
IN UINT64 ExchangeValue
)
{
// GCC 4.1 and forward supports atomic builtins
#if ((__GNUC__ > 4) || ((__GNUC__ == 4) && (__GNUC_MINOR__ >= 1)))
return __sync_val_compare_and_swap (Value, CompareValue, ExchangeValue);
#else
__asm__ __volatile__ (
" \n\t"
"push %%ebx \n\t"
"movl %2,%%ebx \n\t"
"lock \n\t"
"cmpxchg8b (%1) \n\t"
"pop %%ebx \n\t"
: "+A" (CompareValue) // %0
: "S" (Value), // %1
"r" ((UINT32) ExchangeValue), // %2
"c" ((UINT32) (ExchangeValue >> 32)) // %3
: "memory",
"cc"
);
return CompareValue;
#endif
}
/** @file
GCC inline implementation of BaseSynchronizationLib processor specific functions.
Copyright (c) 2006 - 2009, Intel Corporation<BR>
Portions copyright (c) 2008-2009 Apple Inc.<BR>
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
/**
Performs an atomic increment of an 32-bit unsigned integer.
Performs an atomic increment of the 32-bit unsigned integer specified by
Value and returns the incremented value. The increment operation must be
performed using MP safe mechanisms. The state of the return value is not
guaranteed to be MP safe.
@param Value A pointer to the 32-bit value to increment.
@return The incremented value.
**/
UINT32
EFIAPI
InternalSyncIncrement (
IN volatile UINT32 *Value
)
{
UINT32 Result;
__asm__ __volatile__ (
"lock \n\t"
"incl %2 \n\t"
"movl %2, %%eax "
: "=a" (Result), // %0
"=m" (*Value) // %1
: "m" (*Value) // %2
: "memory",
"cc"
);
return Result;
}
/**
Performs an atomic decrement of an 32-bit unsigned integer.
Performs an atomic decrement of the 32-bit unsigned integer specified by
Value and returns the decremented value. The decrement operation must be
performed using MP safe mechanisms. The state of the return value is not
guaranteed to be MP safe.
@param Value A pointer to the 32-bit value to decrement.
@return The decremented value.
**/
UINT32
EFIAPI
InternalSyncDecrement (
IN volatile UINT32 *Value
)
{
UINT32 Result;
__asm__ __volatile__ (
"lock \n\t"
"decl %2 \n\t"
"movl %2, %%eax "
: "=a" (Result), // %0
"=m" (*Value) // %1
: "m" (*Value) // %2
: "memory",
"cc"
);
return Result;
}
/**
Performs an atomic compare exchange operation on a 32-bit unsigned integer.
Performs an atomic compare exchange operation on the 32-bit unsigned integer
specified by Value. If Value is equal to CompareValue, then Value is set to
ExchangeValue and CompareValue is returned. If Value is not equal to CompareValue,
then Value is returned. The compare exchange operation must be performed using
MP safe mechanisms.
@param Value A pointer to the 32-bit value for the compare exchange
operation.
@param CompareValue 32-bit value used in compare operation.
@param ExchangeValue 32-bit value used in exchange operation.
@return The original *Value before exchange.
**/
UINT32
EFIAPI
InternalSyncCompareExchange32 (
IN OUT volatile UINT32 *Value,
IN UINT32 CompareValue,
IN UINT32 ExchangeValue
)
{
// GCC 4.1 and forward supports atomic builtins
#if ((__GNUC__ > 4) || ((__GNUC__ == 4) && (__GNUC_MINOR__ >= 1)))
return __sync_val_compare_and_swap (Value, CompareValue, ExchangeValue);
#else
__asm__ __volatile__ (
" \n\t"
"lock \n\t"
"cmpxchgl %1, %2 \n\t"
: "=a" (CompareValue) // %0
: "q" (ExchangeValue), // %1
"m" (*Value),m // %2
"0" (CompareValue) // %4
: "memory",
"cc"
);
return CompareValue;
#endif
}
/**
Performs an atomic compare exchange operation on a 64-bit unsigned integer.
Performs an atomic compare exchange operation on the 64-bit unsigned integer specified
by Value. If Value is equal to CompareValue, then Value is set to ExchangeValue and
CompareValue is returned. If Value is not equal to CompareValue, then Value is returned.
The compare exchange operation must be performed using MP safe mechanisms.
@param Value A pointer to the 64-bit value for the compare exchange
operation.
@param CompareValue 64-bit value used in compare operation.
@param ExchangeValue 64-bit value used in exchange operation.
@return The original *Value before exchange.
**/
UINT64
EFIAPI
InternalSyncCompareExchange64 (
IN OUT volatile UINT64 *Value,
IN UINT64 CompareValue,
IN UINT64 ExchangeValue
)
{
// GCC 4.1 and forward supports atomic builtins
#if ((__GNUC__ > 4) || ((__GNUC__ == 4) && (__GNUC_MINOR__ >= 1)))
return __sync_val_compare_and_swap (Value, CompareValue, ExchangeValue);
#else
__asm__ __volatile__ (
" \n\t"
"push %%ebx \n\t"
"movl %2,%%ebx \n\t"
"lock \n\t"
"cmpxchg8b (%1) \n\t"
"pop %%ebx \n\t"
: "+A" (CompareValue) // %0
: "S" (Value), // %1
"r" ((UINT32) ExchangeValue), // %2
"c" ((UINT32) (ExchangeValue >> 32)) // %3
: "memory",
"cc"
);
return CompareValue;
#endif
}

4
MdePkg/Library/BaseSynchronizationLib/SynchronizationGcc.c
View File

@ -2,7 +2,7 @@
Implementation of synchronization functions.
Copyright (c) 2006 - 2008, Intel Corporation<BR>
Portions Copyright (c) 2008-2009 Apple Inc.<BR>
Portions Copyright (c) 2008-2009 Apple Inc.<BR>
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@ -18,7 +18,7 @@
//
// GCC inline assembly for Read Write Barrier
//
#define _ReadWriteBarrier() do { __asm__ __volatile__ ("": : : "memory"); } while(0)
#define _ReadWriteBarrier() do { __asm__ __volatile__ ("": : : "memory"); } while(0)
#define SPIN_LOCK_RELEASED ((UINTN) 1)
#define SPIN_LOCK_ACQUIRED ((UINTN) 2)

384
MdePkg/Library/BaseSynchronizationLib/X64/GccInline.c
View File

@ -1,192 +1,192 @@
/** @file
GCC inline implementation of BaseSynchronizationLib processor specific functions.
Copyright (c) 2006 - 2009, Intel Corporation<BR>
Portions copyright (c) 2008-2009 Apple Inc.<BR>
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
/**
Performs an atomic increment of an 32-bit unsigned integer.
Performs an atomic increment of the 32-bit unsigned integer specified by
Value and returns the incremented value. The increment operation must be
performed using MP safe mechanisms. The state of the return value is not
guaranteed to be MP safe.
@param Value A pointer to the 32-bit value to increment.
@return The incremented value.
**/
UINT32
EFIAPI
InternalSyncIncrement (
IN volatile UINT32 *Value
)
{
UINT32 Result;
__asm__ __volatile__ (
"lock \n\t"
"incl %2 \n\t"
"mov %2, %%eax "
: "=a" (Result), // %0
"=m" (*Value) // %1
: "m" (*Value) // %2
: "memory",
"cc"
);
return Result;
}
/**
Performs an atomic decrement of an 32-bit unsigned integer.
Performs an atomic decrement of the 32-bit unsigned integer specified by
Value and returns the decremented value. The decrement operation must be
performed using MP safe mechanisms. The state of the return value is not
guaranteed to be MP safe.
@param Value A pointer to the 32-bit value to decrement.
@return The decremented value.
**/
UINT32
EFIAPI
InternalSyncDecrement (
IN volatile UINT32 *Value
)
{
UINT32 Result;
__asm__ __volatile__ (
"lock \n\t"
"decl %2 \n\t"
"mov %2, %%eax "
: "=a" (Result), // %0
"=m" (*Value) // %1
: "m" (*Value) // %2
: "memory",
"cc"
);
return Result;
}
/**
Performs an atomic compare exchange operation on a 32-bit unsigned integer.
Performs an atomic compare exchange operation on the 32-bit unsigned integer
specified by Value. If Value is equal to CompareValue, then Value is set to
ExchangeValue and CompareValue is returned. If Value is not equal to CompareValue,
then Value is returned. The compare exchange operation must be performed using
MP safe mechanisms.
@param Value A pointer to the 32-bit value for the compare exchange
operation.
@param CompareValue 32-bit value used in compare operation.
@param ExchangeValue 32-bit value used in exchange operation.
@return The original *Value before exchange.
**/
UINT32
EFIAPI
InternalSyncCompareExchange32 (
IN OUT volatile UINT32 *Value,
IN UINT32 CompareValue,
IN UINT32 ExchangeValue
)
{
// GCC 4.1 and forward supports atomic builtins
#if ((__GNUC__ > 4) || ((__GNUC__ == 4) && (__GNUC_MINOR__ >= 1)))
return __sync_val_compare_and_swap (Value, CompareValue, ExchangeValue);
#else
__asm__ __volatile__ (
"lock \n\t"
"cmpxchgl %3, %1 "
: "=a" (CompareValue), // %0
"=m" (*Value) // %1
: "a" (CompareValue), // %2
"r" (ExchangeValue), // %3
"m" (*Value)
: "memory",
"cc"
);
return CompareValue;
#endif
}
/**
Performs an atomic compare exchange operation on a 64-bit unsigned integer.
Performs an atomic compare exchange operation on the 64-bit unsigned integer specified
by Value. If Value is equal to CompareValue, then Value is set to ExchangeValue and
CompareValue is returned. If Value is not equal to CompareValue, then Value is returned.
The compare exchange operation must be performed using MP safe mechanisms.
@param Value A pointer to the 64-bit value for the compare exchange
operation.
@param CompareValue 64-bit value used in compare operation.
@param ExchangeValue 64-bit value used in exchange operation.
@return The original *Value before exchange.
**/
UINT64
EFIAPI
InternalSyncCompareExchange64 (
IN OUT volatile UINT64 *Value,
IN UINT64 CompareValue,
IN UINT64 ExchangeValue
)
{
// GCC 4.1 and forward supports atomic builtins
#if ((__GNUC__ > 4) || ((__GNUC__ == 4) && (__GNUC_MINOR__ >= 1)))
return __sync_val_compare_and_swap (Value, CompareValue, ExchangeValue);
#else
__asm__ __volatile__ (
"lock \n\t"
"cmpxchgq %3, %1 "
: "=a" (CompareValue), // %0
"=m" (*Value) // %1
: "a" (CompareValue), // %2
"r" (ExchangeValue), // %3
"m" (*Value)
: "memory",
"cc"
);
return CompareValue;
#endif
}
/** @file
GCC inline implementation of BaseSynchronizationLib processor specific functions.
Copyright (c) 2006 - 2009, Intel Corporation<BR>
Portions copyright (c) 2008-2009 Apple Inc.<BR>
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
/**
Performs an atomic increment of an 32-bit unsigned integer.
Performs an atomic increment of the 32-bit unsigned integer specified by
Value and returns the incremented value. The increment operation must be
performed using MP safe mechanisms. The state of the return value is not
guaranteed to be MP safe.
@param Value A pointer to the 32-bit value to increment.
@return The incremented value.
**/
UINT32
EFIAPI
InternalSyncIncrement (
IN volatile UINT32 *Value
)
{
UINT32 Result;
__asm__ __volatile__ (
"lock \n\t"
"incl %2 \n\t"
"mov %2, %%eax "
: "=a" (Result), // %0
"=m" (*Value) // %1
: "m" (*Value) // %2
: "memory",
"cc"
);
return Result;
}
/**
Performs an atomic decrement of an 32-bit unsigned integer.
Performs an atomic decrement of the 32-bit unsigned integer specified by
Value and returns the decremented value. The decrement operation must be
performed using MP safe mechanisms. The state of the return value is not
guaranteed to be MP safe.
@param Value A pointer to the 32-bit value to decrement.
@return The decremented value.
**/
UINT32
EFIAPI
InternalSyncDecrement (
IN volatile UINT32 *Value
)
{
UINT32 Result;
__asm__ __volatile__ (
"lock \n\t"
"decl %2 \n\t"
"mov %2, %%eax "
: "=a" (Result), // %0
"=m" (*Value) // %1
: "m" (*Value) // %2
: "memory",
"cc"
);
return Result;
}
/**
Performs an atomic compare exchange operation on a 32-bit unsigned integer.
Performs an atomic compare exchange operation on the 32-bit unsigned integer
specified by Value. If Value is equal to CompareValue, then Value is set to
ExchangeValue and CompareValue is returned. If Value is not equal to CompareValue,
then Value is returned. The compare exchange operation must be performed using
MP safe mechanisms.
@param Value A pointer to the 32-bit value for the compare exchange
operation.
@param CompareValue 32-bit value used in compare operation.
@param ExchangeValue 32-bit value used in exchange operation.
@return The original *Value before exchange.
**/
UINT32
EFIAPI
InternalSyncCompareExchange32 (
IN OUT volatile UINT32 *Value,
IN UINT32 CompareValue,
IN UINT32 ExchangeValue
)
{
// GCC 4.1 and forward supports atomic builtins
#if ((__GNUC__ > 4) || ((__GNUC__ == 4) && (__GNUC_MINOR__ >= 1)))
return __sync_val_compare_and_swap (Value, CompareValue, ExchangeValue);
#else
__asm__ __volatile__ (
"lock \n\t"
"cmpxchgl %3, %1 "
: "=a" (CompareValue), // %0
"=m" (*Value) // %1
: "a" (CompareValue), // %2
"r" (ExchangeValue), // %3
"m" (*Value)
: "memory",
"cc"
);
return CompareValue;
#endif
}
/**
Performs an atomic compare exchange operation on a 64-bit unsigned integer.
Performs an atomic compare exchange operation on the 64-bit unsigned integer specified
by Value. If Value is equal to CompareValue, then Value is set to ExchangeValue and
CompareValue is returned. If Value is not equal to CompareValue, then Value is returned.
The compare exchange operation must be performed using MP safe mechanisms.
@param Value A pointer to the 64-bit value for the compare exchange
operation.
@param CompareValue 64-bit value used in compare operation.
@param ExchangeValue 64-bit value used in exchange operation.
@return The original *Value before exchange.
**/
UINT64
EFIAPI
InternalSyncCompareExchange64 (
IN OUT volatile UINT64 *Value,
IN UINT64 CompareValue,
IN UINT64 ExchangeValue
)
{
// GCC 4.1 and forward supports atomic builtins
#if ((__GNUC__ > 4) || ((__GNUC__ == 4) && (__GNUC_MINOR__ >= 1)))
return __sync_val_compare_and_swap (Value, CompareValue, ExchangeValue);
#else
__asm__ __volatile__ (
"lock \n\t"
"cmpxchgq %3, %1 "
: "=a" (CompareValue), // %0
"=m" (*Value) // %1
: "a" (CompareValue), // %2
"r" (ExchangeValue), // %3
"m" (*Value)
: "memory",
"cc"
);
return CompareValue;
#endif
}

6
MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.c
View File

@ -2,7 +2,7 @@
UEFI Decompress Library implementation refer to UEFI specification.
Copyright (c) 2006 - 2008, Intel Corporation<BR>
Portions Copyright (c) 2008-2009 Apple Inc.<BR>
Portions Copyright (c) 2008-2009 Apple Inc.<BR>
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@ -338,7 +338,7 @@ ReadPTLen (
//
CharC = (UINT16) GetBits (Sd, nbit);
SetMem16 (&Sd->mPTTable[0] , sizeof (Sd->mPTTable), CharC);
SetMem16 (&Sd->mPTTable[0] , sizeof (Sd->mPTTable), CharC);
SetMem (Sd->mPTLen, nn, 0);
@ -417,7 +417,7 @@ ReadCLen (
CharC = (UINT16) GetBits (Sd, CBIT);
SetMem (Sd->mCLen, NC, 0);
SetMem16 (&Sd->mCTable[0], sizeof (Sd->mCTable), CharC);
SetMem16 (&Sd->mCTable[0], sizeof (Sd->mCTable), CharC);
return ;
}

4
MdePkg/MdePkg.dsc
View File

@ -2,7 +2,7 @@
# EFI/PI MdePkg Package
#
# Copyright (c) 2007 - 2009, Intel Corporation<BR>
# Portions Copyright (c) 2008-2009 Apple Inc.<BR>
# Portions Copyright (c) 2008-2009 Apple Inc.<BR>
#
# All rights reserved. This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
@ -20,7 +20,7 @@
PLATFORM_VERSION = 1.01
DSC_SPECIFICATION = 0x00010005
OUTPUT_DIRECTORY = Build/Mde
SUPPORTED_ARCHITECTURES = IA32|IPF|X64|EBC|ARM
SUPPORTED_ARCHITECTURES = IA32|IPF|X64|EBC|ARM
BUILD_TARGETS = DEBUG|RELEASE
SKUID_IDENTIFIER = DEFAULT