sravan/system76-edk2
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

ArmPkg/CpuDxe: Stack Pointer is not 8-bytes aligned in AArch32 interrupt handling

Browse Source 
See section "2.1 The need to align SP to a multiple of 8 at conforming call sites" in
"Advisory Note. SP must be 8-byte aligned on entry to AAPCS-conforming functions"
Source: http://infocenter.arm.com/help/topic/com.arm.doc.ihi0046b/IHI0046B_ABI_Advisory_1.pdf

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15553 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
Olivier Martin
2014-06-03 16:42:18 +00:00
committed by oliviermartin
parent 27331bff97
commit ec17f0f56a
4 changed files with 28 additions and 14 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
ArmPkg/Drivers/CpuDxe/AArch64/Exception.c
View File

@@ -133,7 +133,7 @@ InitializeExceptions (
// AArch64 alignment? The Vector table must be 2k-byte aligned (bottom 11 bits zero)?
//DEBUG ((EFI_D_ERROR, "vbar set addr: 0x%016lx\n",(UINTN)ExceptionHandlersStart));
//ASSERT(((UINTN)ExceptionHandlersStart & ((1 << 11)-1)) == 0);
//ASSERT(((UINTN)ExceptionHandlersStart & ARM_VECTOR_TABLE_ALIGNMENT) == 0);
// We do not copy the Exception Table at PcdGet32(PcdCpuVectorBaseAddress). We just set Vector Base Address to point into CpuDxe code.
ArmWriteVBar ((UINTN)ExceptionHandlersStart);