ArmPkg/CpuDxe: Stack Pointer is not 8-bytes aligned in AArch32 interrupt handling

See section "2.1 The need to align SP to a multiple of 8 at conforming call sites" in
"Advisory Note. SP must be 8-byte aligned on entry to AAPCS-conforming functions"
Source: http://infocenter.arm.com/help/topic/com.arm.doc.ihi0046b/IHI0046B_ABI_Advisory_1.pdf

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15553 6f19259b-4bc3-4df7-8a09-765794883524

ArmPkg/Drivers/CpuDxe/ArmV6/Exception.c

@@ -209,7 +209,7 @@ InitializeExceptions (
     ArmWriteVBar (PcdGet32(PcdCpuVectorBaseAddress));
   } else {
     // The Vector table must be 32-byte aligned
-    ASSERT(((UINT32)ExceptionHandlersStart & ((1 << 5)-1)) == 0);
+    ASSERT(((UINT32)ExceptionHandlersStart & ARM_VECTOR_TABLE_ALIGNMENT) == 0);
 
     // We do not copy the Exception Table at PcdGet32(PcdCpuVectorBaseAddress). We just set Vector Base Address to point into CpuDxe code.
     ArmWriteVBar ((UINT32)ExceptionHandlersStart);