sravan/system76-edk2
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Fixed a bug in WriteBackInvalidDataCache() that always flush cache lines even when the argument Length is zero.

Browse Source 
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@1504 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
bxing 2006-09-09 02:44:57 +00:00
parent b0e15cb260
commit ed9610eb9c
1 changed files with 17 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

26
MdePkg/Library/BaseCacheMaintenanceLib/x86Cache.c
View File

@ -14,6 +14,12 @@
**/ **/
//
// This size must be at or below the smallest cache size possible among all
// supported processors
//
#define CACHE_LINE_SIZE 0x20
/** /**
Invalidates the entire instruction cache in cache coherency domain of the Invalidates the entire instruction cache in cache coherency domain of the
calling CPU. calling CPU.
@ -118,19 +124,21 @@ WriteBackInvalidateDataCacheRange (
IN UINTN Length IN UINTN Length
) )
{ {
UINT8 (*Uint8Ptr)[32]; UINTN Start, End;
ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1); ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);
Uint8Ptr = Address; if (Length == 0) {
while (Length > sizeof (*Uint8Ptr)) { return Address;
AsmFlushCacheLine (Uint8Ptr++);
Length -= sizeof (*Uint8Ptr);
}
if (Length > 0) {
AsmFlushCacheLine (Uint8Ptr);
AsmFlushCacheLine (&(*Uint8Ptr)[Length - 1]);
} }
Start = (UINTN)Address;
End = (Start + Length + (CACHE_LINE_SIZE - 1)) & ~(CACHE_LINE_SIZE - 1);
Start &= ~(CACHE_LINE_SIZE - 1);
do {
Start = (UINTN)AsmFlushCacheLine ((VOID*)Start) + CACHE_LINE_SIZE;
} while (Start != End);
return Address; return Address;
} }