ArmPkg: update RVCT assembly functions to use new RVCT_ASM_EXPORT macro
This has the effect of splitting assembly functions into their own sections so the linker can remove unused ones to save space. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Eugene Cohen <eugene@hp.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@gmail.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19109 6f19259b-4bc3-4df7-8a09-765794883524
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abiesheuvel
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@@ -15,16 +15,15 @@
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#include <Library/ArmCpuLib.h>
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#include <Chipset/ArmCortexA9.h>
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INCLUDE AsmMacroExport.inc
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INCLUDE AsmMacroIoLib.inc
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EXPORT ArmGetScuBaseAddress
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PRESERVE8
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AREA ArmCortexA9Helper, CODE, READONLY
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// IN None
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// OUT r0 = SCU Base Address
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ArmGetScuBaseAddress
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RVCT_ASM_EXPORT ArmGetScuBaseAddress
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// Read Configuration Base Address Register. ArmCBar cannot be called to get
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// the Configuration BAR as a stack is not necessary setup. The SCU is at the
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// offset 0x0000 from the Private Memory Region.
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@@ -13,23 +13,15 @@
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// For the moment we assume this will run in SVC mode on ARMv7
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EXPORT ArmGicV3GetControlSystemRegisterEnable
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EXPORT ArmGicV3SetControlSystemRegisterEnable
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EXPORT ArmGicV3EnableInterruptInterface
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EXPORT ArmGicV3DisableInterruptInterface
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EXPORT ArmGicV3EndOfInterrupt
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EXPORT ArmGicV3AcknowledgeInterrupt
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EXPORT ArmGicV3SetPriorityMask
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EXPORT ArmGicV3SetBinaryPointer
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AREA ArmGicV3, CODE, READONLY
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INCLUDE AsmMacroExport.inc
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//UINT32
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//EFIAPI
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//ArmGicGetControlSystemRegisterEnable (
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// VOID
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// );
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ArmGicV3GetControlSystemRegisterEnable
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RVCT_ASM_EXPORT ArmGicV3GetControlSystemRegisterEnable
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mrc p15, 0, r0, c12, c12, 5 // ICC_SRE
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bx lr
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@@ -38,7 +30,7 @@ ArmGicV3GetControlSystemRegisterEnable
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//ArmGicSetControlSystemRegisterEnable (
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// IN UINT32 ControlSystemRegisterEnable
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// );
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ArmGicV3SetControlSystemRegisterEnable
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RVCT_ASM_EXPORT ArmGicV3SetControlSystemRegisterEnable
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mcr p15, 0, r0, c12, c12, 5 // ICC_SRE
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isb
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bx lr
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@@ -47,7 +39,7 @@ ArmGicV3SetControlSystemRegisterEnable
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//ArmGicV3EnableInterruptInterface (
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// VOID
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// );
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ArmGicV3EnableInterruptInterface
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RVCT_ASM_EXPORT ArmGicV3EnableInterruptInterface
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mov r0, #1
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mcr p15, 0, r0, c12, c12, 7 // ICC_IGRPEN1
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bx lr
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@@ -56,7 +48,7 @@ ArmGicV3EnableInterruptInterface
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//ArmGicV3DisableInterruptInterface (
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// VOID
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// );
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ArmGicV3DisableInterruptInterface
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RVCT_ASM_EXPORT ArmGicV3DisableInterruptInterface
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mov r0, #0
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mcr p15, 0, r0, c12, c12, 7 // ICC_IGRPEN1
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bx lr
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@@ -65,7 +57,7 @@ ArmGicV3DisableInterruptInterface
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//ArmGicV3EndOfInterrupt (
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// IN UINTN InterruptId
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// );
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ArmGicV3EndOfInterrupt
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RVCT_ASM_EXPORT ArmGicV3EndOfInterrupt
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mcr p15, 0, r0, c12, c12, 1 //ICC_EOIR1
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bx lr
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@@ -73,7 +65,7 @@ ArmGicV3EndOfInterrupt
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//ArmGicV3AcknowledgeInterrupt (
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// VOID
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// );
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ArmGicV3AcknowledgeInterrupt
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RVCT_ASM_EXPORT ArmGicV3AcknowledgeInterrupt
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mrc p15, 0, r0, c12, c8, 0 //ICC_IAR1
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bx lr
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@@ -81,7 +73,7 @@ ArmGicV3AcknowledgeInterrupt
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//ArmGicV3SetPriorityMask (
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// IN UINTN Priority
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// );
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ArmGicV3SetPriorityMask
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RVCT_ASM_EXPORT ArmGicV3SetPriorityMask
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mcr p15, 0, r0, c4, c6, 0 //ICC_PMR
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bx lr
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@@ -89,7 +81,7 @@ ArmGicV3SetPriorityMask
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//ArmGicV3SetBinaryPointer (
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// IN UINTN BinaryPoint
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// );
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ArmGicV3SetBinaryPointer
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RVCT_ASM_EXPORT ArmGicV3SetBinaryPointer
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mcr p15, 0, r0, c12, c12, 3 //ICC_BPR1
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bx lr
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