ArmPkg: update RVCT assembly functions to use new RVCT_ASM_EXPORT macro
This has the effect of splitting assembly functions into their own sections so the linker can remove unused ones to save space. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Eugene Cohen <eugene@hp.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@gmail.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19109 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
Eugene Cohen
committed by
abiesheuvel
abiesheuvel
parent
e04671e81a
commit
efda177513
@@ -14,27 +14,13 @@
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//------------------------------------------------------------------------------
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EXPORT ArmIsMpCore
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EXPORT ArmHasMpExtensions
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EXPORT ArmEnableAsynchronousAbort
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EXPORT ArmDisableAsynchronousAbort
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EXPORT ArmEnableIrq
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EXPORT ArmDisableIrq
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EXPORT ArmEnableFiq
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EXPORT ArmDisableFiq
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EXPORT ArmEnableInterrupts
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EXPORT ArmDisableInterrupts
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EXPORT ReadCCSIDR
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EXPORT ReadCLIDR
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EXPORT ArmReadNsacr
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EXPORT ArmWriteNsacr
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AREA ArmLibSupportV7, CODE, READONLY
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INCLUDE AsmMacroExport.inc
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//------------------------------------------------------------------------------
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ArmIsMpCore
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RVCT_ASM_EXPORT ArmIsMpCore
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mrc p15,0,R0,c0,c0,5
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// Get Multiprocessing extension (bit31) & U bit (bit30)
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and R0, R0, #0xC0000000
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@@ -44,48 +30,48 @@ ArmIsMpCore
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movne R0, #0
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bx LR
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ArmHasMpExtensions
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RVCT_ASM_EXPORT ArmHasMpExtensions
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mrc p15,0,R0,c0,c0,5
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// Get Multiprocessing extension (bit31)
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lsr R0, R0, #31
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bx LR
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ArmEnableAsynchronousAbort
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RVCT_ASM_EXPORT ArmEnableAsynchronousAbort
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cpsie a
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isb
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bx LR
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ArmDisableAsynchronousAbort
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RVCT_ASM_EXPORT ArmDisableAsynchronousAbort
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cpsid a
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isb
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bx LR
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ArmEnableIrq
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RVCT_ASM_EXPORT ArmEnableIrq
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cpsie i
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isb
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bx LR
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ArmDisableIrq
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RVCT_ASM_EXPORT ArmDisableIrq
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cpsid i
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isb
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bx LR
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ArmEnableFiq
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RVCT_ASM_EXPORT ArmEnableFiq
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cpsie f
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isb
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bx LR
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ArmDisableFiq
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RVCT_ASM_EXPORT ArmDisableFiq
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cpsid f
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isb
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bx LR
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ArmEnableInterrupts
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RVCT_ASM_EXPORT ArmEnableInterrupts
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cpsie if
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isb
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bx LR
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ArmDisableInterrupts
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RVCT_ASM_EXPORT ArmDisableInterrupts
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cpsid if
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isb
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bx LR
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@@ -94,7 +80,7 @@ ArmDisableInterrupts
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// ReadCCSIDR (
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// IN UINT32 CSSELR
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// )
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ReadCCSIDR
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RVCT_ASM_EXPORT ReadCCSIDR
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mcr p15,2,r0,c0,c0,0 ; Write Cache Size Selection Register (CSSELR)
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isb
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mrc p15,1,r0,c0,c0,0 ; Read current CP15 Cache Size ID Register (CCSIDR)
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@@ -104,15 +90,15 @@ ReadCCSIDR
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// ReadCLIDR (
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// IN UINT32 CSSELR
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// )
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ReadCLIDR
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RVCT_ASM_EXPORT ReadCLIDR
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mrc p15,1,r0,c0,c0,1 ; Read CP15 Cache Level ID Register
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bx lr
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ArmReadNsacr
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RVCT_ASM_EXPORT ArmReadNsacr
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mrc p15, 0, r0, c1, c1, 2
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bx lr
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ArmWriteNsacr
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RVCT_ASM_EXPORT ArmWriteNsacr
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mcr p15, 0, r0, c1, c1, 2
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bx lr
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@@ -12,107 +12,87 @@
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//
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//------------------------------------------------------------------------------
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EXPORT ArmReadCntFrq
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EXPORT ArmWriteCntFrq
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EXPORT ArmReadCntPct
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EXPORT ArmReadCntkCtl
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EXPORT ArmWriteCntkCtl
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EXPORT ArmReadCntpTval
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EXPORT ArmWriteCntpTval
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EXPORT ArmReadCntpCtl
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EXPORT ArmWriteCntpCtl
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EXPORT ArmReadCntvTval
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EXPORT ArmWriteCntvTval
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EXPORT ArmReadCntvCtl
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EXPORT ArmWriteCntvCtl
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EXPORT ArmReadCntvCt
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EXPORT ArmReadCntpCval
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EXPORT ArmWriteCntpCval
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EXPORT ArmReadCntvCval
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EXPORT ArmWriteCntvCval
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EXPORT ArmReadCntvOff
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EXPORT ArmWriteCntvOff
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AREA ArmV7ArchTimerSupport, CODE, READONLY
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INCLUDE AsmMacroExport.inc
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PRESERVE8
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ArmReadCntFrq
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RVCT_ASM_EXPORT ArmReadCntFrq
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mrc p15, 0, r0, c14, c0, 0 ; Read CNTFRQ
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bx lr
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ArmWriteCntFrq
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RVCT_ASM_EXPORT ArmWriteCntFrq
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mcr p15, 0, r0, c14, c0, 0 ; Write to CNTFRQ
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bx lr
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ArmReadCntPct
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RVCT_ASM_EXPORT ArmReadCntPct
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mrrc p15, 0, r0, r1, c14 ; Read CNTPT (Physical counter register)
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bx lr
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ArmReadCntkCtl
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RVCT_ASM_EXPORT ArmReadCntkCtl
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mrc p15, 0, r0, c14, c1, 0 ; Read CNTK_CTL (Timer PL1 Control Register)
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bx lr
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ArmWriteCntkCtl
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RVCT_ASM_EXPORT ArmWriteCntkCtl
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mcr p15, 0, r0, c14, c1, 0 ; Write to CNTK_CTL (Timer PL1 Control Register)
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bx lr
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ArmReadCntpTval
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RVCT_ASM_EXPORT ArmReadCntpTval
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mrc p15, 0, r0, c14, c2, 0 ; Read CNTP_TVAL (PL1 physical timer value register)
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bx lr
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ArmWriteCntpTval
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RVCT_ASM_EXPORT ArmWriteCntpTval
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mcr p15, 0, r0, c14, c2, 0 ; Write to CNTP_TVAL (PL1 physical timer value register)
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bx lr
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ArmReadCntpCtl
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RVCT_ASM_EXPORT ArmReadCntpCtl
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mrc p15, 0, r0, c14, c2, 1 ; Read CNTP_CTL (PL1 Physical Timer Control Register)
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bx lr
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ArmWriteCntpCtl
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RVCT_ASM_EXPORT ArmWriteCntpCtl
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mcr p15, 0, r0, c14, c2, 1 ; Write to CNTP_CTL (PL1 Physical Timer Control Register)
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bx lr
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ArmReadCntvTval
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RVCT_ASM_EXPORT ArmReadCntvTval
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mrc p15, 0, r0, c14, c3, 0 ; Read CNTV_TVAL (Virtual Timer Value register)
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bx lr
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ArmWriteCntvTval
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RVCT_ASM_EXPORT ArmWriteCntvTval
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mcr p15, 0, r0, c14, c3, 0 ; Write to CNTV_TVAL (Virtual Timer Value register)
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bx lr
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ArmReadCntvCtl
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RVCT_ASM_EXPORT ArmReadCntvCtl
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mrc p15, 0, r0, c14, c3, 1 ; Read CNTV_CTL (Virtual Timer Control Register)
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bx lr
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ArmWriteCntvCtl
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RVCT_ASM_EXPORT ArmWriteCntvCtl
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mcr p15, 0, r0, c14, c3, 1 ; Write to CNTV_CTL (Virtual Timer Control Register)
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bx lr
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ArmReadCntvCt
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RVCT_ASM_EXPORT ArmReadCntvCt
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mrrc p15, 1, r0, r1, c14 ; Read CNTVCT (Virtual Count Register)
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bx lr
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ArmReadCntpCval
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RVCT_ASM_EXPORT ArmReadCntpCval
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mrrc p15, 2, r0, r1, c14 ; Read CNTP_CTVAL (Physical Timer Compare Value Register)
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bx lr
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ArmWriteCntpCval
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RVCT_ASM_EXPORT ArmWriteCntpCval
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mcrr p15, 2, r0, r1, c14 ; Write to CNTP_CTVAL (Physical Timer Compare Value Register)
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bx lr
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ArmReadCntvCval
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RVCT_ASM_EXPORT ArmReadCntvCval
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mrrc p15, 3, r0, r1, c14 ; Read CNTV_CTVAL (Virtual Timer Compare Value Register)
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bx lr
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ArmWriteCntvCval
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RVCT_ASM_EXPORT ArmWriteCntvCval
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mcrr p15, 3, r0, r1, c14 ; write to CNTV_CTVAL (Virtual Timer Compare Value Register)
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bx lr
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ArmReadCntvOff
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RVCT_ASM_EXPORT ArmReadCntvOff
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mrrc p15, 4, r0, r1, c14 ; Read CNTVOFF (virtual Offset register)
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bx lr
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ArmWriteCntvOff
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RVCT_ASM_EXPORT ArmWriteCntvOff
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mcrr p15, 4, r0, r1, c14 ; Write to CNTVOFF (Virtual Offset register)
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bx lr
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@@ -13,43 +13,8 @@
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//
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//------------------------------------------------------------------------------
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EXPORT ArmInvalidateInstructionCache
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EXPORT ArmInvalidateDataCacheEntryByMVA
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EXPORT ArmCleanDataCacheEntryByMVA
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EXPORT ArmCleanInvalidateDataCacheEntryByMVA
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EXPORT ArmInvalidateDataCacheEntryBySetWay
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EXPORT ArmCleanDataCacheEntryBySetWay
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EXPORT ArmCleanInvalidateDataCacheEntryBySetWay
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EXPORT ArmEnableMmu
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EXPORT ArmDisableMmu
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EXPORT ArmDisableCachesAndMmu
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EXPORT ArmMmuEnabled
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EXPORT ArmEnableDataCache
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EXPORT ArmDisableDataCache
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EXPORT ArmEnableInstructionCache
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EXPORT ArmDisableInstructionCache
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EXPORT ArmEnableSWPInstruction
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EXPORT ArmEnableBranchPrediction
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EXPORT ArmDisableBranchPrediction
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EXPORT ArmSetLowVectors
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EXPORT ArmSetHighVectors
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EXPORT ArmV7AllDataCachesOperation
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EXPORT ArmDataMemoryBarrier
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EXPORT ArmDataSynchronizationBarrier
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EXPORT ArmInstructionSynchronizationBarrier
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EXPORT ArmReadVBar
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EXPORT ArmWriteVBar
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EXPORT ArmEnableVFP
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EXPORT ArmCallWFI
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EXPORT ArmReadCbar
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EXPORT ArmReadMpidr
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EXPORT ArmReadTpidrurw
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EXPORT ArmWriteTpidrurw
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EXPORT ArmIsArchTimerImplemented
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EXPORT ArmReadIdPfr1
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EXPORT ArmReadIdMmfr0
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AREA ArmV7Support, CODE, READONLY
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INCLUDE AsmMacroExport.inc
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PRESERVE8
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DC_ON EQU ( 0x1:SHL:2 )
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@@ -60,41 +25,41 @@ CTRL_B_BIT EQU (1 << 7)
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CTRL_I_BIT EQU (1 << 12)
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ArmInvalidateDataCacheEntryByMVA
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RVCT_ASM_EXPORT ArmInvalidateDataCacheEntryByMVA
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mcr p15, 0, r0, c7, c6, 1 ; invalidate single data cache line
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bx lr
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ArmCleanDataCacheEntryByMVA
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RVCT_ASM_EXPORT ArmCleanDataCacheEntryByMVA
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mcr p15, 0, r0, c7, c10, 1 ; clean single data cache line
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bx lr
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ArmCleanInvalidateDataCacheEntryByMVA
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RVCT_ASM_EXPORT ArmCleanInvalidateDataCacheEntryByMVA
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mcr p15, 0, r0, c7, c14, 1 ; clean and invalidate single data cache line
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bx lr
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ArmInvalidateDataCacheEntryBySetWay
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RVCT_ASM_EXPORT ArmInvalidateDataCacheEntryBySetWay
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mcr p15, 0, r0, c7, c6, 2 ; Invalidate this line
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bx lr
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ArmCleanInvalidateDataCacheEntryBySetWay
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RVCT_ASM_EXPORT ArmCleanInvalidateDataCacheEntryBySetWay
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mcr p15, 0, r0, c7, c14, 2 ; Clean and Invalidate this line
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bx lr
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ArmCleanDataCacheEntryBySetWay
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RVCT_ASM_EXPORT ArmCleanDataCacheEntryBySetWay
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mcr p15, 0, r0, c7, c10, 2 ; Clean this line
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bx lr
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ArmInvalidateInstructionCache
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RVCT_ASM_EXPORT ArmInvalidateInstructionCache
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mcr p15,0,R0,c7,c5,0 ;Invalidate entire instruction cache
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isb
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bx LR
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ArmEnableMmu
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RVCT_ASM_EXPORT ArmEnableMmu
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mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
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orr R0,R0,#1 ; Set SCTLR.M bit : Enable MMU
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mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)
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@@ -102,7 +67,7 @@ ArmEnableMmu
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isb
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bx LR
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ArmDisableMmu
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RVCT_ASM_EXPORT ArmDisableMmu
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mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
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bic R0,R0,#1 ; Clear SCTLR.M bit : Disable MMU
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mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)
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@@ -113,7 +78,7 @@ ArmDisableMmu
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isb
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bx LR
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ArmDisableCachesAndMmu
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RVCT_ASM_EXPORT ArmDisableCachesAndMmu
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mrc p15, 0, r0, c1, c0, 0 ; Get control register
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bic r0, r0, #CTRL_M_BIT ; Disable MMU
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bic r0, r0, #CTRL_C_BIT ; Disable D Cache
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@@ -123,12 +88,12 @@ ArmDisableCachesAndMmu
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isb
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bx LR
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ArmMmuEnabled
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RVCT_ASM_EXPORT ArmMmuEnabled
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mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
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and R0,R0,#1
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bx LR
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ArmEnableDataCache
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RVCT_ASM_EXPORT ArmEnableDataCache
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ldr R1,=DC_ON ; Specify SCTLR.C bit : (Data) Cache enable bit
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mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
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orr R0,R0,R1 ; Set SCTLR.C bit : Data and unified caches enabled
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@@ -137,7 +102,7 @@ ArmEnableDataCache
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isb
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bx LR
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ArmDisableDataCache
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RVCT_ASM_EXPORT ArmDisableDataCache
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ldr R1,=DC_ON ; Specify SCTLR.C bit : (Data) Cache enable bit
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mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
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bic R0,R0,R1 ; Clear SCTLR.C bit : Data and unified caches disabled
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@@ -146,7 +111,7 @@ ArmDisableDataCache
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isb
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bx LR
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ArmEnableInstructionCache
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RVCT_ASM_EXPORT ArmEnableInstructionCache
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ldr R1,=IC_ON ; Specify SCTLR.I bit : Instruction cache enable bit
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mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
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orr R0,R0,R1 ; Set SCTLR.I bit : Instruction caches enabled
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@@ -155,7 +120,7 @@ ArmEnableInstructionCache
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isb
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bx LR
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ArmDisableInstructionCache
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RVCT_ASM_EXPORT ArmDisableInstructionCache
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ldr R1,=IC_ON ; Specify SCTLR.I bit : Instruction cache enable bit
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mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
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BIC R0,R0,R1 ; Clear SCTLR.I bit : Instruction caches disabled
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@@ -163,14 +128,14 @@ ArmDisableInstructionCache
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isb
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bx LR
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ArmEnableSWPInstruction
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RVCT_ASM_EXPORT ArmEnableSWPInstruction
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mrc p15, 0, r0, c1, c0, 0
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orr r0, r0, #0x00000400
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mcr p15, 0, r0, c1, c0, 0
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isb
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bx LR
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ArmEnableBranchPrediction
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RVCT_ASM_EXPORT ArmEnableBranchPrediction
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mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
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orr r0, r0, #0x00000800 ;
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mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
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@@ -178,7 +143,7 @@ ArmEnableBranchPrediction
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isb
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bx LR
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ArmDisableBranchPrediction
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RVCT_ASM_EXPORT ArmDisableBranchPrediction
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mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
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bic r0, r0, #0x00000800 ;
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mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
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@@ -186,21 +151,21 @@ ArmDisableBranchPrediction
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isb
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bx LR
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ArmSetLowVectors
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RVCT_ASM_EXPORT ArmSetLowVectors
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mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
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bic r0, r0, #0x00002000 ; clear V bit
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mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
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isb
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bx LR
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ArmSetHighVectors
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RVCT_ASM_EXPORT ArmSetHighVectors
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mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
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orr r0, r0, #0x00002000 ; Set V bit
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mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
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isb
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bx LR
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ArmV7AllDataCachesOperation
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RVCT_ASM_EXPORT ArmV7AllDataCachesOperation
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stmfd SP!,{r4-r12, LR}
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mov R1, R0 ; Save Function call in R1
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mrc p15, 1, R6, c0, c0, 1 ; Read CLIDR
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@@ -249,24 +214,24 @@ Finished
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ldmfd SP!, {r4-r12, lr}
|
||||
bx LR
|
||||
|
||||
ArmDataMemoryBarrier
|
||||
RVCT_ASM_EXPORT ArmDataMemoryBarrier
|
||||
dmb
|
||||
bx LR
|
||||
|
||||
ArmDataSynchronizationBarrier
|
||||
RVCT_ASM_EXPORT ArmDataSynchronizationBarrier
|
||||
dsb
|
||||
bx LR
|
||||
|
||||
ArmInstructionSynchronizationBarrier
|
||||
RVCT_ASM_EXPORT ArmInstructionSynchronizationBarrier
|
||||
isb
|
||||
bx LR
|
||||
|
||||
ArmReadVBar
|
||||
RVCT_ASM_EXPORT ArmReadVBar
|
||||
// Set the Address of the Vector Table in the VBAR register
|
||||
mrc p15, 0, r0, c12, c0, 0
|
||||
bx lr
|
||||
|
||||
ArmWriteVBar
|
||||
RVCT_ASM_EXPORT ArmWriteVBar
|
||||
// Set the Address of the Vector Table in the VBAR register
|
||||
mcr p15, 0, r0, c12, c0, 0
|
||||
// Ensure the SCTLR.V bit is clear
|
||||
@@ -276,7 +241,7 @@ ArmWriteVBar
|
||||
isb
|
||||
bx lr
|
||||
|
||||
ArmEnableVFP
|
||||
RVCT_ASM_EXPORT ArmEnableVFP
|
||||
// Read CPACR (Coprocessor Access Control Register)
|
||||
mrc p15, 0, r0, c1, c0, 2
|
||||
// Enable VPF access (Full Access to CP10, CP11) (V* instructions)
|
||||
@@ -289,37 +254,37 @@ ArmEnableVFP
|
||||
mcr p10,#0x7,r0,c8,c0,#0
|
||||
bx lr
|
||||
|
||||
ArmCallWFI
|
||||
RVCT_ASM_EXPORT ArmCallWFI
|
||||
wfi
|
||||
bx lr
|
||||
|
||||
//Note: Return 0 in Uniprocessor implementation
|
||||
ArmReadCbar
|
||||
RVCT_ASM_EXPORT ArmReadCbar
|
||||
mrc p15, 4, r0, c15, c0, 0 //Read Configuration Base Address Register
|
||||
bx lr
|
||||
|
||||
ArmReadMpidr
|
||||
RVCT_ASM_EXPORT ArmReadMpidr
|
||||
mrc p15, 0, r0, c0, c0, 5 ; read MPIDR
|
||||
bx lr
|
||||
|
||||
ArmReadTpidrurw
|
||||
RVCT_ASM_EXPORT ArmReadTpidrurw
|
||||
mrc p15, 0, r0, c13, c0, 2 ; read TPIDRURW
|
||||
bx lr
|
||||
|
||||
ArmWriteTpidrurw
|
||||
RVCT_ASM_EXPORT ArmWriteTpidrurw
|
||||
mcr p15, 0, r0, c13, c0, 2 ; write TPIDRURW
|
||||
bx lr
|
||||
|
||||
ArmIsArchTimerImplemented
|
||||
RVCT_ASM_EXPORT ArmIsArchTimerImplemented
|
||||
mrc p15, 0, r0, c0, c1, 1 ; Read ID_PFR1
|
||||
and r0, r0, #0x000F0000
|
||||
bx lr
|
||||
|
||||
ArmReadIdPfr1
|
||||
RVCT_ASM_EXPORT ArmReadIdPfr1
|
||||
mrc p15, 0, r0, c0, c1, 1 ; Read ID_PFR1 Register
|
||||
bx lr
|
||||
|
||||
ArmReadIdMmfr0
|
||||
RVCT_ASM_EXPORT ArmReadIdMmfr0
|
||||
mrc p15, 0, r0, c0, c1, 4 ; Read ID_MMFR0 Register
|
||||
bx lr
|
||||
|
||||
|
||||
Reference in New Issue
Block a user