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ArmPkg: update RVCT assembly functions to use new RVCT_ASM_EXPORT macro

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This has the effect of splitting assembly functions into their own sections
so the linker can remove unused ones to save space.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Eugene Cohen <eugene@hp.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@gmail.com>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19109 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
Eugene Cohen
2015-12-03 20:28:02 +00:00
committed by abiesheuvel
parent e04671e81a
commit efda177513
27 changed files with 151 additions and 272 deletions
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44
ArmPkg/Library/ArmLib/ArmV7/ArmLibSupportV7.asm
View File

@@ -14,27 +14,13 @@
//------------------------------------------------------------------------------
EXPORT ArmIsMpCore
EXPORT ArmHasMpExtensions
EXPORT ArmEnableAsynchronousAbort
EXPORT ArmDisableAsynchronousAbort
EXPORT ArmEnableIrq
EXPORT ArmDisableIrq
EXPORT ArmEnableFiq
EXPORT ArmDisableFiq
EXPORT ArmEnableInterrupts
EXPORT ArmDisableInterrupts
EXPORT ReadCCSIDR
EXPORT ReadCLIDR
EXPORT ArmReadNsacr
EXPORT ArmWriteNsacr
AREA ArmLibSupportV7, CODE, READONLY
INCLUDE AsmMacroExport.inc
//------------------------------------------------------------------------------
ArmIsMpCore
RVCT_ASM_EXPORT ArmIsMpCore
mrc p15,0,R0,c0,c0,5
// Get Multiprocessing extension (bit31) & U bit (bit30)
and R0, R0, #0xC0000000
@@ -44,48 +30,48 @@ ArmIsMpCore
movne R0, #0
bx LR
ArmHasMpExtensions
RVCT_ASM_EXPORT ArmHasMpExtensions
mrc p15,0,R0,c0,c0,5
// Get Multiprocessing extension (bit31)
lsr R0, R0, #31
bx LR
ArmEnableAsynchronousAbort
RVCT_ASM_EXPORT ArmEnableAsynchronousAbort
cpsie a
isb
bx LR
ArmDisableAsynchronousAbort
RVCT_ASM_EXPORT ArmDisableAsynchronousAbort
cpsid a
isb
bx LR
ArmEnableIrq
RVCT_ASM_EXPORT ArmEnableIrq
cpsie i
isb
bx LR
ArmDisableIrq
RVCT_ASM_EXPORT ArmDisableIrq
cpsid i
isb
bx LR
ArmEnableFiq
RVCT_ASM_EXPORT ArmEnableFiq
cpsie f
isb
bx LR
ArmDisableFiq
RVCT_ASM_EXPORT ArmDisableFiq
cpsid f
isb
bx LR
ArmEnableInterrupts
RVCT_ASM_EXPORT ArmEnableInterrupts
cpsie if
isb
bx LR
ArmDisableInterrupts
RVCT_ASM_EXPORT ArmDisableInterrupts
cpsid if
isb
bx LR
@@ -94,7 +80,7 @@ ArmDisableInterrupts
// ReadCCSIDR (
// IN UINT32 CSSELR
// )
ReadCCSIDR
RVCT_ASM_EXPORT ReadCCSIDR
mcr p15,2,r0,c0,c0,0 ; Write Cache Size Selection Register (CSSELR)
isb
mrc p15,1,r0,c0,c0,0 ; Read current CP15 Cache Size ID Register (CCSIDR)
@@ -104,15 +90,15 @@ ReadCCSIDR
// ReadCLIDR (
// IN UINT32 CSSELR
// )
ReadCLIDR
RVCT_ASM_EXPORT ReadCLIDR
mrc p15,1,r0,c0,c0,1 ; Read CP15 Cache Level ID Register
bx lr
ArmReadNsacr
RVCT_ASM_EXPORT ArmReadNsacr
mrc p15, 0, r0, c1, c1, 2
bx lr
ArmWriteNsacr
RVCT_ASM_EXPORT ArmWriteNsacr
mcr p15, 0, r0, c1, c1, 2
bx lr