ArmPkg: update RVCT assembly functions to use new RVCT_ASM_EXPORT macro
This has the effect of splitting assembly functions into their own sections so the linker can remove unused ones to save space. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Eugene Cohen <eugene@hp.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@gmail.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19109 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
Eugene Cohen
committed by
abiesheuvel
abiesheuvel
parent
e04671e81a
commit
efda177513
@@ -17,62 +17,36 @@
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INCLUDE AsmMacroIoLib.inc
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EXPORT ArmReadMidr
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EXPORT ArmCacheInfo
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EXPORT ArmGetInterruptState
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EXPORT ArmGetFiqState
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EXPORT ArmGetTTBR0BaseAddress
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EXPORT ArmSetTTBR0
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EXPORT ArmSetDomainAccessControl
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EXPORT CPSRMaskInsert
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EXPORT CPSRRead
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EXPORT ArmReadCpacr
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EXPORT ArmWriteCpacr
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EXPORT ArmWriteAuxCr
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EXPORT ArmReadAuxCr
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EXPORT ArmInvalidateTlb
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EXPORT ArmUpdateTranslationTableEntry
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EXPORT ArmReadScr
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EXPORT ArmWriteScr
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EXPORT ArmReadMVBar
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EXPORT ArmWriteMVBar
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EXPORT ArmReadHVBar
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EXPORT ArmWriteHVBar
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EXPORT ArmCallWFE
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EXPORT ArmCallSEV
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EXPORT ArmReadSctlr
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EXPORT ArmReadCpuActlr
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EXPORT ArmWriteCpuActlr
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AREA ArmLibSupport, CODE, READONLY
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INCLUDE AsmMacroExport.inc
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ArmReadMidr
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RVCT_ASM_EXPORT ArmReadMidr
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mrc p15,0,R0,c0,c0,0
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bx LR
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ArmCacheInfo
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RVCT_ASM_EXPORT ArmCacheInfo
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mrc p15,0,R0,c0,c0,1
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bx LR
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ArmGetInterruptState
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RVCT_ASM_EXPORT ArmGetInterruptState
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mrs R0,CPSR
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tst R0,#0x80 // Check if IRQ is enabled.
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moveq R0,#1
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movne R0,#0
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bx LR
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ArmGetFiqState
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RVCT_ASM_EXPORT ArmGetFiqState
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mrs R0,CPSR
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tst R0,#0x40 // Check if FIQ is enabled.
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moveq R0,#1
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movne R0,#0
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bx LR
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ArmSetDomainAccessControl
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RVCT_ASM_EXPORT ArmSetDomainAccessControl
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mcr p15,0,r0,c3,c0,0
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bx lr
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CPSRMaskInsert // on entry, r0 is the mask and r1 is the field to insert
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RVCT_ASM_EXPORT CPSRMaskInsert
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stmfd sp!, {r4-r12, lr} // save all the banked registers
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mov r3, sp // copy the stack pointer into a non-banked register
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mrs r2, cpsr // read the cpsr
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@@ -85,33 +59,33 @@ CPSRMaskInsert // on entry, r0 is the mask and r1 is the field to insert
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ldmfd sp!, {r4-r12, lr} // restore registers
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bx lr // return (hopefully thumb-safe!) // return (hopefully thumb-safe!)
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CPSRRead
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RVCT_ASM_EXPORT CPSRRead
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mrs r0, cpsr
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bx lr
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ArmReadCpacr
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RVCT_ASM_EXPORT ArmReadCpacr
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mrc p15, 0, r0, c1, c0, 2
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bx lr
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ArmWriteCpacr
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RVCT_ASM_EXPORT ArmWriteCpacr
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mcr p15, 0, r0, c1, c0, 2
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isb
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bx lr
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ArmWriteAuxCr
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RVCT_ASM_EXPORT ArmWriteAuxCr
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mcr p15, 0, r0, c1, c0, 1
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bx lr
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ArmReadAuxCr
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RVCT_ASM_EXPORT ArmReadAuxCr
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mrc p15, 0, r0, c1, c0, 1
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bx lr
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ArmSetTTBR0
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RVCT_ASM_EXPORT ArmSetTTBR0
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mcr p15,0,r0,c2,c0,0
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isb
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bx lr
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ArmGetTTBR0BaseAddress
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RVCT_ASM_EXPORT ArmGetTTBR0BaseAddress
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mrc p15,0,r0,c2,c0,0
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LoadConstantToReg(0xFFFFC000, r1)
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and r0, r0, r1
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@@ -124,7 +98,7 @@ ArmGetTTBR0BaseAddress
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// IN VOID *TranslationTableEntry // R0
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// IN VOID *MVA // R1
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// );
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ArmUpdateTranslationTableEntry
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RVCT_ASM_EXPORT ArmUpdateTranslationTableEntry
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mcr p15,0,R0,c7,c14,1 // DCCIMVAC Clean data cache by MVA
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dsb
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mcr p15,0,R1,c8,c7,1 // TLBIMVA TLB Invalidate MVA
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@@ -133,7 +107,7 @@ ArmUpdateTranslationTableEntry
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isb
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bx lr
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ArmInvalidateTlb
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RVCT_ASM_EXPORT ArmInvalidateTlb
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mov r0,#0
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mcr p15,0,r0,c8,c7,0
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mcr p15,0,R9,c7,c5,6 // BPIALL Invalidate Branch predictor array. R9 == NoOp
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@@ -141,48 +115,48 @@ ArmInvalidateTlb
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isb
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bx lr
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ArmReadScr
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RVCT_ASM_EXPORT ArmReadScr
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mrc p15, 0, r0, c1, c1, 0
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bx lr
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ArmWriteScr
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RVCT_ASM_EXPORT ArmWriteScr
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mcr p15, 0, r0, c1, c1, 0
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bx lr
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ArmReadHVBar
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RVCT_ASM_EXPORT ArmReadHVBar
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mrc p15, 4, r0, c12, c0, 0
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bx lr
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ArmWriteHVBar
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RVCT_ASM_EXPORT ArmWriteHVBar
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mcr p15, 4, r0, c12, c0, 0
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bx lr
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ArmReadMVBar
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RVCT_ASM_EXPORT ArmReadMVBar
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mrc p15, 0, r0, c12, c0, 1
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bx lr
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ArmWriteMVBar
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RVCT_ASM_EXPORT ArmWriteMVBar
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mcr p15, 0, r0, c12, c0, 1
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bx lr
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ArmCallWFE
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RVCT_ASM_EXPORT ArmCallWFE
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wfe
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bx lr
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ArmCallSEV
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RVCT_ASM_EXPORT ArmCallSEV
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sev
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bx lr
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ArmReadSctlr
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RVCT_ASM_EXPORT ArmReadSctlr
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mrc p15, 0, r0, c1, c0, 0 // Read SCTLR into R0 (Read control register configuration data)
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bx lr
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ArmReadCpuActlr
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RVCT_ASM_EXPORT ArmReadCpuActlr
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mrc p15, 0, r0, c1, c0, 1
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bx lr
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ArmWriteCpuActlr
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RVCT_ASM_EXPORT ArmWriteCpuActlr
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mcr p15, 0, r0, c1, c0, 1
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dsb
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isb
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