ArmPkg|EmbeddedPkg: make PcdCpuVectorBaseAddress 64 bits wide
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Leo Duran <leo.duran@amd.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
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Ard Biesheuvel
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91673dfdfe
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f0bbcdf80d
@@ -60,7 +60,7 @@
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# On ARM Architecture with the Security Extension, the address for the
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# Vector Table can be mapped anywhere in the memory map. It means we can
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# point the Exception Vector Table to its location in CpuDxe.
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# By default we copy the Vector Table at PcdGet32(PcdCpuVectorBaseAddress)
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# By default we copy the Vector Table at PcdGet64(PcdCpuVectorBaseAddress)
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gArmTokenSpaceGuid.PcdRelocateVectorTable|TRUE|BOOLEAN|0x00000022
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# Set this PCD to TRUE if the Exception Vector is changed to add debugger support before
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# it has been configured by the CPU DXE
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@@ -90,7 +90,7 @@
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# This PCD will free the unallocated buffers if their size reach this threshold.
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# We set the default value to 512MB.
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gArmTokenSpaceGuid.PcdArmFreeUncachedMemorySizeThreshold|0x20000000|UINT64|0x00000003
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gArmTokenSpaceGuid.PcdCpuVectorBaseAddress|0xffff0000|UINT32|0x00000004
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gArmTokenSpaceGuid.PcdCpuVectorBaseAddress|0xffff0000|UINT64|0x00000004
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gArmTokenSpaceGuid.PcdCpuResetAddress|0x00000000|UINT32|0x00000005
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#
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@@ -103,7 +103,7 @@ InitializeCpuExceptionHandlers(
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// if we are requested to copy exceptin handlers to another location
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if (gArmRelocateVectorTable) {
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VectorBase = PcdGet32(PcdCpuVectorBaseAddress);
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VectorBase = PcdGet64(PcdCpuVectorBaseAddress);
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Status = CopyExceptionHandlers(VectorBase);
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}
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@@ -118,7 +118,7 @@ InitializeCpuExceptionHandlers(
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// for encapsulated FVs.
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ASSERT(((UINTN)ExceptionHandlersStart & gExceptionVectorAlignmentMask) == 0);
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// We do not copy the Exception Table at PcdGet32(PcdCpuVectorBaseAddress). We just set Vector
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// We do not copy the Exception Table at PcdGet64(PcdCpuVectorBaseAddress). We just set Vector
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// Base Address to point into CpuDxe code.
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VectorBase = (UINTN)ExceptionHandlersStart;
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