UefiCpuPkg: Simplify the struct definition of CPU_EXCEPTION_INIT_DATA
CPU_EXCEPTION_INIT_DATA is now an internal implementation of CpuExceptionHandlerLib. Union can be removed since Ia32 and X64 have the same definition. Also, two fields (Revision and InitDefaultHandlers)are useless, can be removed. Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
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@@ -1,7 +1,7 @@
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/** @file
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x64 CPU Exception Handler.
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Copyright (c) 2012 - 2019, Intel Corporation. All rights reserved.<BR>
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Copyright (c) 2012 - 2022, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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@@ -136,16 +136,15 @@ ArchSetupExceptionStack (
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UINTN GdtSize;
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if ((StackSwitchData == NULL) ||
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(StackSwitchData->Ia32.Revision != CPU_EXCEPTION_INIT_DATA_REV) ||
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(StackSwitchData->X64.KnownGoodStackTop == 0) ||
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(StackSwitchData->X64.KnownGoodStackSize == 0) ||
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(StackSwitchData->X64.StackSwitchExceptions == NULL) ||
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(StackSwitchData->X64.StackSwitchExceptionNumber == 0) ||
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(StackSwitchData->X64.StackSwitchExceptionNumber > CPU_EXCEPTION_NUM) ||
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(StackSwitchData->X64.GdtTable == NULL) ||
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(StackSwitchData->X64.IdtTable == NULL) ||
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(StackSwitchData->X64.ExceptionTssDesc == NULL) ||
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(StackSwitchData->X64.ExceptionTss == NULL))
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(StackSwitchData->KnownGoodStackTop == 0) ||
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(StackSwitchData->KnownGoodStackSize == 0) ||
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(StackSwitchData->StackSwitchExceptions == NULL) ||
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(StackSwitchData->StackSwitchExceptionNumber == 0) ||
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(StackSwitchData->StackSwitchExceptionNumber > CPU_EXCEPTION_NUM) ||
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(StackSwitchData->GdtTable == NULL) ||
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(StackSwitchData->IdtTable == NULL) ||
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(StackSwitchData->ExceptionTssDesc == NULL) ||
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(StackSwitchData->ExceptionTss == NULL))
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{
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return EFI_INVALID_PARAMETER;
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}
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@@ -155,16 +154,16 @@ ArchSetupExceptionStack (
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// one or newly allocated, has enough space to hold descriptors for exception
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// task-state segments.
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//
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if (((UINTN)StackSwitchData->X64.GdtTable & (IA32_GDT_ALIGNMENT - 1)) != 0) {
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if (((UINTN)StackSwitchData->GdtTable & (IA32_GDT_ALIGNMENT - 1)) != 0) {
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return EFI_INVALID_PARAMETER;
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}
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if ((UINTN)StackSwitchData->X64.ExceptionTssDesc < (UINTN)(StackSwitchData->X64.GdtTable)) {
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if ((UINTN)StackSwitchData->ExceptionTssDesc < (UINTN)(StackSwitchData->GdtTable)) {
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return EFI_INVALID_PARAMETER;
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}
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if (((UINTN)StackSwitchData->X64.ExceptionTssDesc + StackSwitchData->X64.ExceptionTssDescSize) >
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((UINTN)(StackSwitchData->X64.GdtTable) + StackSwitchData->X64.GdtTableSize))
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if (((UINTN)StackSwitchData->ExceptionTssDesc + StackSwitchData->ExceptionTssDescSize) >
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((UINTN)(StackSwitchData->GdtTable) + StackSwitchData->GdtTableSize))
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{
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return EFI_INVALID_PARAMETER;
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}
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@@ -172,20 +171,20 @@ ArchSetupExceptionStack (
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//
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// One task gate descriptor and one task-state segment are needed.
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//
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if (StackSwitchData->X64.ExceptionTssDescSize < sizeof (IA32_TSS_DESCRIPTOR)) {
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if (StackSwitchData->ExceptionTssDescSize < sizeof (IA32_TSS_DESCRIPTOR)) {
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return EFI_INVALID_PARAMETER;
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}
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if (StackSwitchData->X64.ExceptionTssSize < sizeof (IA32_TASK_STATE_SEGMENT)) {
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if (StackSwitchData->ExceptionTssSize < sizeof (IA32_TASK_STATE_SEGMENT)) {
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return EFI_INVALID_PARAMETER;
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}
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//
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// Interrupt stack table supports only 7 vectors.
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//
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TssDesc = StackSwitchData->X64.ExceptionTssDesc;
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Tss = StackSwitchData->X64.ExceptionTss;
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if (StackSwitchData->X64.StackSwitchExceptionNumber > ARRAY_SIZE (Tss->IST)) {
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TssDesc = StackSwitchData->ExceptionTssDesc;
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Tss = StackSwitchData->ExceptionTss;
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if (StackSwitchData->StackSwitchExceptionNumber > ARRAY_SIZE (Tss->IST)) {
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return EFI_INVALID_PARAMETER;
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}
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@@ -196,19 +195,19 @@ ArchSetupExceptionStack (
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AsmReadGdtr (&Gdtr);
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GdtSize = (UINTN)TssDesc + sizeof (IA32_TSS_DESCRIPTOR) -
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(UINTN)(StackSwitchData->X64.GdtTable);
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if ((UINTN)StackSwitchData->X64.GdtTable != Gdtr.Base) {
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CopyMem (StackSwitchData->X64.GdtTable, (VOID *)Gdtr.Base, Gdtr.Limit + 1);
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Gdtr.Base = (UINTN)StackSwitchData->X64.GdtTable;
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(UINTN)(StackSwitchData->GdtTable);
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if ((UINTN)StackSwitchData->GdtTable != Gdtr.Base) {
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CopyMem (StackSwitchData->GdtTable, (VOID *)Gdtr.Base, Gdtr.Limit + 1);
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Gdtr.Base = (UINTN)StackSwitchData->GdtTable;
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Gdtr.Limit = (UINT16)GdtSize - 1;
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}
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if ((UINTN)StackSwitchData->X64.IdtTable != Idtr.Base) {
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Idtr.Base = (UINTN)StackSwitchData->X64.IdtTable;
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if ((UINTN)StackSwitchData->IdtTable != Idtr.Base) {
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Idtr.Base = (UINTN)StackSwitchData->IdtTable;
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}
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if (StackSwitchData->X64.IdtTableSize > 0) {
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Idtr.Limit = (UINT16)(StackSwitchData->X64.IdtTableSize - 1);
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if (StackSwitchData->IdtTableSize > 0) {
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Idtr.Limit = (UINT16)(StackSwitchData->IdtTableSize - 1);
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}
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//
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@@ -232,20 +231,20 @@ ArchSetupExceptionStack (
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// Fixup exception task descriptor and task-state segment
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//
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ZeroMem (Tss, sizeof (*Tss));
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StackTop = StackSwitchData->X64.KnownGoodStackTop - CPU_STACK_ALIGNMENT;
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StackTop = StackSwitchData->KnownGoodStackTop - CPU_STACK_ALIGNMENT;
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StackTop = (UINTN)ALIGN_POINTER (StackTop, CPU_STACK_ALIGNMENT);
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IdtTable = StackSwitchData->X64.IdtTable;
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for (Index = 0; Index < StackSwitchData->X64.StackSwitchExceptionNumber; ++Index) {
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IdtTable = StackSwitchData->IdtTable;
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for (Index = 0; Index < StackSwitchData->StackSwitchExceptionNumber; ++Index) {
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//
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// Fixup IST
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//
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Tss->IST[Index] = StackTop;
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StackTop -= StackSwitchData->X64.KnownGoodStackSize;
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StackTop -= StackSwitchData->KnownGoodStackSize;
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//
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// Set the IST field to enable corresponding IST
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//
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Vector = StackSwitchData->X64.StackSwitchExceptions[Index];
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Vector = StackSwitchData->StackSwitchExceptions[Index];
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if ((Vector >= CPU_EXCEPTION_NUM) ||
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(Vector >= (Idtr.Limit + 1) / sizeof (IA32_IDT_GATE_DESCRIPTOR)))
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{
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@@ -263,7 +262,7 @@ ArchSetupExceptionStack (
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//
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// Load current task
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//
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AsmWriteTr ((UINT16)((UINTN)StackSwitchData->X64.ExceptionTssDesc - Gdtr.Base));
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AsmWriteTr ((UINT16)((UINTN)StackSwitchData->ExceptionTssDesc - Gdtr.Base));
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//
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// Publish IDT
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