UefiCpuPkg: RISC-V: Support MMU with SV39/48/57 mode
During CpuDxe initialization, MMU will be setup with the highest mode that HW supports. Signed-off-by: Tuan Phan <tphan@ventanamicro.com> Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com> Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
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@@ -15,11 +15,13 @@
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#include <Protocol/Cpu.h>
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#include <Protocol/RiscVBootProtocol.h>
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#include <Library/BaseRiscVSbiLib.h>
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#include <Library/BaseRiscVMmuLib.h>
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#include <Library/BaseLib.h>
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#include <Library/CpuExceptionHandlerLib.h>
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#include <Library/DebugLib.h>
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#include <Library/UefiBootServicesTableLib.h>
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#include <Library/UefiDriverEntryPoint.h>
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#include <Register/RiscV64/RiscVEncoding.h>
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/**
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Flush CPU data cache. If the instruction cache is fully coherent
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